1 /* Declarations for Intel 80386 opcode table 2 Copyright (C) 2007-2026 Free Software Foundation, Inc. 3 4 This file is part of the GNU opcodes library. 5 6 This library is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 It is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GAS; see the file COPYING. If not, write to the Free 18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 19 02110-1301, USA. */ 20 21 #include "opcode/i386.h" 22 #include <limits.h> 23 #ifndef CHAR_BIT 24 #define CHAR_BIT 8 25 #endif 26 27 /* Position of cpu flags bitfiled. */ 28 29 enum i386_cpu 30 { 31 /* i186 or better required */ 32 Cpu186 = 0, 33 /* i286 or better required */ 34 Cpu286, 35 /* i386 or better required */ 36 Cpu386, 37 /* i486 or better required */ 38 Cpu486, 39 /* i585 or better required */ 40 Cpu586, 41 /* i686 or better required */ 42 Cpu686, 43 /* CMOV Instruction support required */ 44 CpuCMOV, 45 /* FXSR Instruction support required */ 46 CpuFXSR, 47 /* CLFLUSH Instruction support required */ 48 CpuClflush, 49 /* NOP Instruction support required */ 50 CpuNop, 51 /* SYSCALL Instructions support required */ 52 CpuSYSCALL, 53 /* Floating point support required */ 54 Cpu8087, 55 /* i686 and floating point support required */ 56 Cpu687, 57 /* SSE3 and floating point support required */ 58 CpuFISTTP, 59 /* MMX support required */ 60 CpuMMX, 61 /* SSE support required */ 62 CpuSSE, 63 /* SSE2 support required */ 64 CpuSSE2, 65 /* SSE3 support required */ 66 CpuSSE3, 67 /* VIA PadLock required */ 68 CpuPadLock, 69 /* Zhaoxin PadLock RNG2 required */ 70 CpuPadLockRNG2, 71 /* Zhaoxin PadLock PHE2 required */ 72 CpuPadLockPHE2, 73 /* Zhaoxin PadLock XMODX required */ 74 CpuPadLockXMODX, 75 /* Zhaoxin GMI SM2 required */ 76 CpuGMISM2, 77 /* Zhaoxin GMI CCS required */ 78 CpuGMICCS, 79 /* AMD Secure Virtual Machine Ext-s required */ 80 CpuSVME, 81 /* VMX Instructions required */ 82 CpuVMX, 83 /* SMX Instructions required */ 84 CpuSMX, 85 /* SSSE3 support required */ 86 CpuSSSE3, 87 /* SSE4a support required */ 88 CpuSSE4a, 89 /* LZCNT support required */ 90 CpuLZCNT, 91 /* POPCNT support required */ 92 CpuPOPCNT, 93 /* MONITOR support required */ 94 CpuMONITOR, 95 /* SSE4.1 support required */ 96 CpuSSE4_1, 97 /* SSE4.2 support required */ 98 CpuSSE4_2, 99 /* AVX2 support required */ 100 CpuAVX2, 101 /* Intel AVX-512 Conflict Detection Instructions support required */ 102 CpuAVX512CD, 103 /* Intel AVX-512 Exponential and Reciprocal Instructions support 104 required */ 105 CpuAVX512ER, 106 /* Intel AVX-512 Prefetch Instructions support required */ 107 CpuAVX512PF, 108 /* Intel AVX-512 DQ Instructions support required. */ 109 CpuAVX512DQ, 110 /* Intel AVX-512 BW Instructions support required. */ 111 CpuAVX512BW, 112 /* Intel IAMCU support required */ 113 CpuIAMCU, 114 /* Xsave/xrstor New Instructions support required */ 115 CpuXsave, 116 /* Xsaveopt New Instructions support required */ 117 CpuXsaveopt, 118 /* AES support required */ 119 CpuAES, 120 /* PCLMULQDQ support required */ 121 CpuPCLMULQDQ, 122 /* FMA support required */ 123 CpuFMA, 124 /* FMA4 support required */ 125 CpuFMA4, 126 /* XOP support required */ 127 CpuXOP, 128 /* LWP support required */ 129 CpuLWP, 130 /* BMI support required */ 131 CpuBMI, 132 /* TBM support required */ 133 CpuTBM, 134 /* MOVBE Instruction support required */ 135 CpuMovbe, 136 /* CMPXCHG16B instruction support required. */ 137 CpuCX16, 138 /* LAHF/SAHF instruction support required (in 64-bit mode). */ 139 CpuLAHF_SAHF, 140 /* EPT Instructions required */ 141 CpuEPT, 142 /* RDTSCP Instruction support required */ 143 CpuRdtscp, 144 /* FSGSBASE Instructions required */ 145 CpuFSGSBase, 146 /* RDRND Instructions required */ 147 CpuRdRnd, 148 /* F16C Instructions required */ 149 CpuF16C, 150 /* Intel BMI2 support required */ 151 CpuBMI2, 152 /* RTM support required */ 153 CpuRTM, 154 /* INVPCID Instructions required */ 155 CpuINVPCID, 156 /* VMFUNC Instruction required */ 157 CpuVMFUNC, 158 /* Intel MPX Instructions required */ 159 CpuMPX, 160 /* RDRSEED instruction required. */ 161 CpuRDSEED, 162 /* Multi-presisionn add-carry instructions are required. */ 163 CpuADX, 164 /* Supports prefetchw and prefetch instructions. */ 165 CpuPRFCHW, 166 /* SMAP instructions required. */ 167 CpuSMAP, 168 /* SHA instructions required. */ 169 CpuSHA, 170 /* SHA512 instructions required. */ 171 CpuSHA512, 172 /* SM3 instructions required. */ 173 CpuSM3, 174 /* SM4 instructions required. */ 175 CpuSM4, 176 /* CLFLUSHOPT instruction required */ 177 CpuClflushOpt, 178 /* XSAVES/XRSTORS instruction required */ 179 CpuXSAVES, 180 /* XSAVEC instruction required */ 181 CpuXSAVEC, 182 /* PREFETCHWT1 instruction required */ 183 CpuPREFETCHWT1, 184 /* SE1 instruction required */ 185 CpuSE1, 186 /* CLWB instruction required */ 187 CpuCLWB, 188 /* Intel AVX-512 IFMA Instructions support required. */ 189 CpuAVX512IFMA, 190 /* Intel AVX-512 VBMI Instructions support required. */ 191 CpuAVX512VBMI, 192 /* Intel AVX-512 4FMAPS Instructions support required. */ 193 CpuAVX512_4FMAPS, 194 /* Intel AVX-512 4VNNIW Instructions support required. */ 195 CpuAVX512_4VNNIW, 196 /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ 197 CpuAVX512_VPOPCNTDQ, 198 /* Intel AVX-512 VBMI2 Instructions support required. */ 199 CpuAVX512_VBMI2, 200 /* Intel AVX-512 VNNI Instructions support required. */ 201 CpuAVX512_VNNI, 202 /* Intel AVX-512 BITALG Instructions support required. */ 203 CpuAVX512_BITALG, 204 /* Intel AVX-512 BF16 Instructions support required. */ 205 CpuAVX512_BF16, 206 /* Intel AVX-512 VP2INTERSECT Instructions support required. */ 207 CpuAVX512_VP2INTERSECT, 208 /* AMD AVX-512 BMM Instructions support required. */ 209 CpuAVX512_BMM, 210 /* TDX Instructions support required. */ 211 CpuTDX, 212 /* Intel AVX VNNI Instructions support required. */ 213 CpuAVX_VNNI, 214 /* Intel AVX-512 FP16 Instructions support required. */ 215 CpuAVX512_FP16, 216 /* PREFETCHI instruction required */ 217 CpuPREFETCHI, 218 /* Intel AVX IFMA Instructions support required. */ 219 CpuAVX_IFMA, 220 /* Intel AVX VNNI-INT8 Instructions support required. */ 221 CpuAVX_VNNI_INT8, 222 /* Intel AVX VNNI-INT16 Instructions support required. */ 223 CpuAVX_VNNI_INT16, 224 /* Intel CMPccXADD instructions support required. */ 225 CpuCMPCCXADD, 226 /* Intel WRMSRNS Instructions support required */ 227 CpuWRMSRNS, 228 /* Intel MSRLIST Instructions support required. */ 229 CpuMSRLIST, 230 /* Intel AVX NE CONVERT Instructions support required. */ 231 CpuAVX_NE_CONVERT, 232 /* Intel RAO INT Instructions support required. */ 233 CpuRAO_INT, 234 /* fred instruction required */ 235 CpuFRED, 236 /* lkgs instruction required */ 237 CpuLKGS, 238 /* Intel USER_MSR Instruction support required. */ 239 CpuUSER_MSR, 240 /* Intel MSR_IMM Instructions support required. */ 241 CpuMSR_IMM, 242 /* Intel MOVRS Instructions support required. */ 243 CpuMOVRS, 244 /* mwaitx instruction required */ 245 CpuMWAITX, 246 /* Clzero instruction required */ 247 CpuCLZERO, 248 /* OSPKE instruction required */ 249 CpuOSPKE, 250 /* RDPID instruction required */ 251 CpuRDPID, 252 /* PTWRITE instruction required */ 253 CpuPTWRITE, 254 /* CET instructions support required */ 255 CpuIBT, 256 CpuSHSTK, 257 /* AMX-INT8 instructions required */ 258 CpuAMX_INT8, 259 /* AMX-BF16 instructions required */ 260 CpuAMX_BF16, 261 /* AMX-FP16 instructions required */ 262 CpuAMX_FP16, 263 /* AMX-COMPLEX instructions required. */ 264 CpuAMX_COMPLEX, 265 /* AMX-TF32 Instructions support required. */ 266 CpuAMX_TF32, 267 /* AMX-FP8 instructions required */ 268 CpuAMX_FP8, 269 /* AMX-MOVRS Instructions support required. */ 270 CpuAMX_MOVRS, 271 /* AMX-AVX512 Instructions support required. */ 272 CpuAMX_AVX512, 273 /* AMX-TILE instructions required */ 274 CpuAMX_TILE, 275 /* GFNI instructions required */ 276 CpuGFNI, 277 /* VAES instructions required */ 278 CpuVAES, 279 /* VPCLMULQDQ instructions required */ 280 CpuVPCLMULQDQ, 281 /* WBNOINVD instructions required */ 282 CpuWBNOINVD, 283 /* PCONFIG instructions required */ 284 CpuPCONFIG, 285 /* PBNDKB instructions required. */ 286 CpuPBNDKB, 287 /* WAITPKG instructions required */ 288 CpuWAITPKG, 289 /* UINTR instructions required */ 290 CpuUINTR, 291 /* CLDEMOTE instruction required */ 292 CpuCLDEMOTE, 293 /* MOVDIRI instruction support required */ 294 CpuMOVDIRI, 295 /* MOVDIRR64B instruction required */ 296 CpuMOVDIR64B, 297 /* ENQCMD instruction required */ 298 CpuENQCMD, 299 /* SERIALIZE instruction required */ 300 CpuSERIALIZE, 301 /* RDPRU instruction required */ 302 CpuRDPRU, 303 /* MCOMMIT instruction required */ 304 CpuMCOMMIT, 305 /* SEV-ES instruction(s) required */ 306 CpuSEV_ES, 307 /* TSXLDTRK instruction required */ 308 CpuTSXLDTRK, 309 /* KL instruction support required */ 310 CpuKL, 311 /* WideKL instruction support required */ 312 CpuWideKL, 313 /* HRESET instruction required */ 314 CpuHRESET, 315 /* INVLPGB instructions required */ 316 CpuINVLPGB, 317 /* TLBSYNC instructions required */ 318 CpuTLBSYNC, 319 /* SNP instructions required */ 320 CpuSNP, 321 /* RMPQUERY instruction required */ 322 CpuRMPQUERY, 323 /* RMPREAD instruction required */ 324 CpuRMPREAD, 325 /* Intel APX New Conditional Instructions support required. */ 326 CpuAPX_NCI, 327 /* Intel APX Non-Destructive Destination support required. */ 328 CpuAPX_NDD, 329 /* Intel APX No-Flags-update support required. */ 330 CpuAPX_NF, 331 332 /* NOTE: These items, which can be combined with other ISA flags above, need 333 to remain second to last and in sync with CPU_FLAGS_COMMON. */ 334 335 /* i287 support required */ 336 Cpu287, 337 CpuAttrEnums = Cpu287, 338 /* i387 support required */ 339 Cpu387, 340 /* 3dnow! support required */ 341 Cpu3dnow, 342 /* 3dnow! Extensions support required */ 343 Cpu3dnowA, 344 /* 64bit support required */ 345 Cpu64, 346 /* AVX support required */ 347 CpuAVX, 348 /* HLE support required */ 349 CpuHLE, 350 /* Intel AVX-512 Foundation Instructions support required */ 351 CpuAVX512F, 352 /* Intel AVX-512 VL Instructions support required. */ 353 CpuAVX512VL, 354 /* Intel APX_F Instructions support required. */ 355 CpuAPX_F, 356 /* Intel AVX10.2 Instructions support required. */ 357 CpuAVX10_2, 358 /* Intel AMX-TRANSPOSE Instructions support required. */ 359 CpuAMX_TRANSPOSE, 360 /* Not supported in the 64bit mode */ 361 CpuNo64, 362 363 /* NOTE: This item needs to remain last. */ 364 365 /* The last bitfield in i386_cpu_flags. */ 366 CpuMax = CpuNo64 367 }; 368 369 #define CpuNumOfUints \ 370 (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) 371 #define CpuNumOfBits \ 372 (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) 373 374 #define CpuIsaBits 8 375 #define CpuAttrNumOfUints \ 376 ((CpuIsaBits + CpuMax - CpuAttrEnums) / sizeof (unsigned int) / CHAR_BIT + 1) 377 #define CpuAttrNumOfBits \ 378 (CpuAttrNumOfUints * sizeof (unsigned int) * CHAR_BIT) 379 380 /* If you get a compiler error for zero width of an unused field, 381 comment the respective one out. */ 382 #define CpuUnused (CpuMax + 1) 383 #define CpuAttrUnused (CpuIsaBits + CpuMax + 1 - CpuAttrEnums) 384 385 #define CPU_FLAGS_COMMON \ 386 unsigned int cpu287:1, \ 387 cpu387:1, \ 388 cpu3dnow:1, \ 389 cpu3dnowa:1, \ 390 cpu64:1, \ 391 cpuavx:1, \ 392 cpuhle:1, \ 393 cpuavx512f:1, \ 394 cpuavx512vl:1, \ 395 cpuapx_f:1, \ 396 cpuavx10_2:1, \ 397 cpuamx_transpose:1, \ 398 /* NOTE: This field needs to remain last. */ \ 399 cpuno64:1 400 401 typedef union i386_cpu_attr 402 { 403 struct 404 { 405 unsigned int isa:CpuIsaBits; 406 CPU_FLAGS_COMMON; 407 #ifdef CpuAttrUnused 408 unsigned int unused:(CpuAttrNumOfBits - CpuAttrUnused); 409 #endif 410 } bitfield; 411 unsigned int array[CpuAttrNumOfUints]; 412 } i386_cpu_attr; 413 414 /* We can check if an instruction is available with array instead 415 of bitfield. */ 416 typedef union i386_cpu_flags 417 { 418 struct 419 { 420 unsigned int cpui186:1; 421 unsigned int cpui286:1; 422 unsigned int cpui386:1; 423 unsigned int cpui486:1; 424 unsigned int cpui586:1; 425 unsigned int cpui686:1; 426 unsigned int cpucmov:1; 427 unsigned int cpufxsr:1; 428 unsigned int cpuclflush:1; 429 unsigned int cpunop:1; 430 unsigned int cpusyscall:1; 431 unsigned int cpu8087:1; 432 unsigned int cpu687:1; 433 unsigned int cpufisttp:1; 434 unsigned int cpummx:1; 435 unsigned int cpusse:1; 436 unsigned int cpusse2:1; 437 unsigned int cpusse3:1; 438 unsigned int cpupadlock:1; 439 unsigned int cpupadlockrng2:1; 440 unsigned int cpupadlockphe2:1; 441 unsigned int cpupadlockxmodx:1; 442 unsigned int cpugmism2:1; 443 unsigned int cpugmiccs:1; 444 unsigned int cpusvme:1; 445 unsigned int cpuvmx:1; 446 unsigned int cpusmx:1; 447 unsigned int cpussse3:1; 448 unsigned int cpusse4a:1; 449 unsigned int cpulzcnt:1; 450 unsigned int cpupopcnt:1; 451 unsigned int cpumonitor:1; 452 unsigned int cpusse4_1:1; 453 unsigned int cpusse4_2:1; 454 unsigned int cpuavx2:1; 455 unsigned int cpuavx512cd:1; 456 unsigned int cpuavx512er:1; 457 unsigned int cpuavx512pf:1; 458 unsigned int cpuavx512dq:1; 459 unsigned int cpuavx512bw:1; 460 unsigned int cpuiamcu:1; 461 unsigned int cpuxsave:1; 462 unsigned int cpuxsaveopt:1; 463 unsigned int cpuaes:1; 464 unsigned int cpupclmulqdq:1; 465 unsigned int cpufma:1; 466 unsigned int cpufma4:1; 467 unsigned int cpuxop:1; 468 unsigned int cpulwp:1; 469 unsigned int cpubmi:1; 470 unsigned int cputbm:1; 471 unsigned int cpumovbe:1; 472 unsigned int cpucx16:1; 473 unsigned int cpulahf_sahf:1; 474 unsigned int cpuept:1; 475 unsigned int cpurdtscp:1; 476 unsigned int cpufsgsbase:1; 477 unsigned int cpurdrnd:1; 478 unsigned int cpuf16c:1; 479 unsigned int cpubmi2:1; 480 unsigned int cpurtm:1; 481 unsigned int cpuinvpcid:1; 482 unsigned int cpuvmfunc:1; 483 unsigned int cpumpx:1; 484 unsigned int cpurdseed:1; 485 unsigned int cpuadx:1; 486 unsigned int cpuprfchw:1; 487 unsigned int cpusmap:1; 488 unsigned int cpusha:1; 489 unsigned int cpusha512:1; 490 unsigned int cpusm3:1; 491 unsigned int cpusm4:1; 492 unsigned int cpuclflushopt:1; 493 unsigned int cpuxsaves:1; 494 unsigned int cpuxsavec:1; 495 unsigned int cpuprefetchwt1:1; 496 unsigned int cpuse1:1; 497 unsigned int cpuclwb:1; 498 unsigned int cpuavx512ifma:1; 499 unsigned int cpuavx512vbmi:1; 500 unsigned int cpuavx512_4fmaps:1; 501 unsigned int cpuavx512_4vnniw:1; 502 unsigned int cpuavx512_vpopcntdq:1; 503 unsigned int cpuavx512_vbmi2:1; 504 unsigned int cpuavx512_vnni:1; 505 unsigned int cpuavx512_bitalg:1; 506 unsigned int cpuavx512_bf16:1; 507 unsigned int cpuavx512_vp2intersect:1; 508 unsigned int cpuavx512_bmm:1; 509 unsigned int cputdx:1; 510 unsigned int cpuavx_vnni:1; 511 unsigned int cpuavx512_fp16:1; 512 unsigned int cpuprefetchi:1; 513 unsigned int cpuavx_ifma:1; 514 unsigned int cpuavx_vnni_int8:1; 515 unsigned int cpuavx_vnni_int16:1; 516 unsigned int cpucmpccxadd:1; 517 unsigned int cpuwrmsrns:1; 518 unsigned int cpumsrlist:1; 519 unsigned int cpuavx_ne_convert:1; 520 unsigned int cpurao_int:1; 521 unsigned int cpufred:1; 522 unsigned int cpulkgs:1; 523 unsigned int cpuuser_msr:1; 524 unsigned int cpumsr_imm:1; 525 unsigned int cpumovrs:1; 526 unsigned int cpumwaitx:1; 527 unsigned int cpuclzero:1; 528 unsigned int cpuospke:1; 529 unsigned int cpurdpid:1; 530 unsigned int cpuptwrite:1; 531 unsigned int cpuibt:1; 532 unsigned int cpushstk:1; 533 unsigned int cpuamx_int8:1; 534 unsigned int cpuamx_bf16:1; 535 unsigned int cpuamx_fp16:1; 536 unsigned int cpuamx_complex:1; 537 unsigned int cpuamx_tf32:1; 538 unsigned int cpuamx_fp8:1; 539 unsigned int cpuamx_movrs:1; 540 unsigned int cpuamx_avx512:1; 541 unsigned int cpuamx_tile:1; 542 unsigned int cpugfni:1; 543 unsigned int cpuvaes:1; 544 unsigned int cpuvpclmulqdq:1; 545 unsigned int cpuwbnoinvd:1; 546 unsigned int cpupconfig:1; 547 unsigned int cpupbndkb:1; 548 unsigned int cpuwaitpkg:1; 549 unsigned int cpuuintr:1; 550 unsigned int cpucldemote:1; 551 unsigned int cpumovdiri:1; 552 unsigned int cpumovdir64b:1; 553 unsigned int cpuenqcmd:1; 554 unsigned int cpuserialize:1; 555 unsigned int cpurdpru:1; 556 unsigned int cpumcommit:1; 557 unsigned int cpusev_es:1; 558 unsigned int cputsxldtrk:1; 559 unsigned int cpukl:1; 560 unsigned int cpuwidekl:1; 561 unsigned int cpuhreset:1; 562 unsigned int cpuinvlpgb:1; 563 unsigned int cputlbsync:1; 564 unsigned int cpusnp:1; 565 unsigned int cpurmpquery:1; 566 unsigned int cpurmpread:1; 567 unsigned int cpuapx_nci:1; 568 unsigned int cpuapx_ndd:1; 569 unsigned int cpuapx_nf:1; 570 CPU_FLAGS_COMMON; 571 #ifdef CpuUnused 572 unsigned int unused:(CpuNumOfBits - CpuUnused); 573 #endif 574 } bitfield; 575 unsigned int array[CpuNumOfUints]; 576 } i386_cpu_flags; 577 578 /* Position of opcode_modifier bits. */ 579 580 enum 581 { 582 /* has direction bit. */ 583 D = 0, 584 /* set if operands can be both bytes and words/dwords/qwords, encoded the 585 canonical way; the base_opcode field should hold the encoding for byte 586 operands */ 587 W, 588 /* load form instruction. Must be placed before store form. */ 589 Load, 590 /* insn has a modrm byte. */ 591 Modrm, 592 /* special case for jump insns; value has to be 1 */ 593 #define JUMP 1 594 /* call and jump */ 595 #define JUMP_DWORD 2 596 /* loop and jecxz */ 597 #define JUMP_BYTE 3 598 /* special case for intersegment leaps/calls */ 599 #define JUMP_INTERSEGMENT 4 600 /* absolute address for jump */ 601 #define JUMP_ABSOLUTE 5 602 Jump, 603 /* FP insn memory format bit, sized by 0x4 */ 604 FloatMF, 605 /* needs size prefix if in 32-bit mode */ 606 #define SIZE16 1 607 /* needs size prefix if in 16-bit mode */ 608 #define SIZE32 2 609 /* needs size prefix if in 64-bit mode */ 610 #define SIZE64 3 611 Size, 612 /* Check that operand sizes match. */ 613 CheckOperandSize, 614 /* any memory size */ 615 #define ANY_SIZE 1 616 /* fake an extra reg operand for clr, imul and special register 617 processing for some instructions. */ 618 #define REG_KLUDGE 2 619 /* deprecated fp insn, gets a warning */ 620 #define UGH 3 621 /* An implicit xmm0 as the first operand */ 622 #define IMPLICIT_1ST_XMM0 4 623 /* One of the operands denotes a sequence of registers, with insn-dependent 624 constraint on the first register number. It implicitly denotes e.g. the 625 register group of {x,y,z}mmN - {x,y,z}mm(N + 3), in which case N ought to 626 be a multiple of 4. 627 */ 628 #define IMPLICIT_GROUP 5 629 /* Default mask isn't allowed. */ 630 #define NO_DEFAULT_MASK 6 631 /* Address prefix changes register operand */ 632 #define ADDR_PREFIX_OP_REG 7 633 /* Instrucion requires that destination must be distinct from source 634 registers. */ 635 #define DISTINCT_DEST 8 636 /* Instruction updates stack pointer implicitly. */ 637 #define IMPLICIT_STACK_OP 9 638 /* Instruction zeroes upper part of register. */ 639 #define ZERO_UPPER 10 640 /* Instruction support SCC. */ 641 #define SCC 11 642 /* Instruction requires EVEX.NF to be 1. */ 643 #define EVEX_NF 12 644 OperandConstraint, 645 /* instruction ignores operand size prefix and in Intel mode ignores 646 mnemonic size suffix check. */ 647 #define IGNORESIZE 1 648 /* default insn size depends on mode */ 649 #define DEFAULTSIZE 2 650 MnemonicSize, 651 /* b suffix on instruction illegal */ 652 No_bSuf, 653 /* w suffix on instruction illegal */ 654 No_wSuf, 655 /* l suffix on instruction illegal */ 656 No_lSuf, 657 /* s suffix on instruction illegal */ 658 No_sSuf, 659 /* q suffix on instruction illegal */ 660 No_qSuf, 661 /* instruction needs FWAIT */ 662 FWait, 663 /* IsString provides for a quick test for string instructions, and 664 its actual value also indicates which of the operands (if any) 665 requires use of the %es segment. */ 666 #define IS_STRING_ES_OP0 2 667 #define IS_STRING_ES_OP1 3 668 IsString, 669 /* RegMem is for instructions with a modrm byte where the register 670 destination operand should be encoded in the mod and regmem fields. 671 Normally, it will be encoded in the reg field. We add a RegMem 672 flag to indicate that it should be encoded in the regmem field. */ 673 RegMem, 674 /* quick test if branch instruction is MPX supported */ 675 BNDPrefixOk, 676 #define PrefixNone 0 677 #define PrefixRep 1 678 #define PrefixRepe 2 679 #define PrefixHLERelease 3 /* Okay with an XRELEASE (0xf3) prefix. */ 680 #define PrefixNoTrack 4 681 /* Prefixes implying "LOCK okay" must come after Lock. All others have 682 to come before. */ 683 #define PrefixLock 5 684 #define PrefixHLELock 6 /* Okay with a LOCK prefix. */ 685 #define PrefixHLEAny 7 /* Okay with or without a LOCK prefix. */ 686 PrefixOk, 687 /* opcode is a prefix */ 688 IsPrefix, 689 /* instruction has extension in 8 bit imm */ 690 ImmExt, 691 /* instruction don't need Rex64 prefix. */ 692 NoRex64, 693 /* insn has VEX prefix: 694 1: 128bit VEX prefix (or operand dependent). 695 2: 256bit VEX prefix. 696 3: Scalar VEX prefix. 697 */ 698 #define VEX128 1 699 #define VEX256 2 700 #define VEXScalar 3 701 Vex, 702 /* How to encode VEX.vvvv: 703 1: VEX.vvvv encodes the src1 register operand. 704 2: VEX.vvvv encodes the src2 register operand. 705 3: VEX.vvvv encodes the dest register operand. 706 */ 707 #define VexVVVV_SRC1 1 708 #define VexVVVV_SRC2 2 709 #define VexVVVV_DST 3 710 711 VexVVVV, 712 /* How the VEX.W bit is used: 713 0: Set by the REX.W bit. 714 1: VEX.W0. Should always be 0. 715 2: VEX.W1. Should always be 1. 716 3: VEX.WIG. The VEX.W bit is ignored. 717 */ 718 #define VEXW0 1 719 #define VEXW1 2 720 #define VEXWIG 3 721 VexW, 722 /* Opcode prefix (values chosen to be usable directly in 723 VEX/XOP/EVEX pp fields): 724 0: None 725 1: Add 0x66 opcode prefix. 726 2: Add 0xf3 opcode prefix. 727 3: Add 0xf2 opcode prefix. 728 */ 729 #define PREFIX_NONE 0 730 #define PREFIX_0X66 1 731 #define PREFIX_0XF3 2 732 #define PREFIX_0XF2 3 733 OpcodePrefix, 734 /* Instruction with a mandatory SIB byte: 735 1: 128bit vector register. 736 2: 256bit vector register. 737 3: 512bit vector register. 738 */ 739 #define VECSIB128 1 740 #define VECSIB256 2 741 #define VECSIB512 3 742 #define SIBMEM 4 743 SIB, 744 745 /* SSE to AVX support required */ 746 SSE2AVX, 747 748 /* insn has EVEX prefix: 749 1: 512bit EVEX prefix. 750 2: 128bit EVEX prefix. 751 3: 256bit EVEX prefix. 752 4: Length-ignored (LIG) EVEX prefix. 753 5: Length determined from actual operands. 754 6: L'L = 3 (reserved, .insn only) 755 */ 756 #define EVEX512 1 757 #define EVEX128 2 758 #define EVEX256 3 759 #define EVEXLIG 4 760 #define EVEXDYN 5 761 #define EVEX_L3 6 762 EVex, 763 764 /* AVX512 masking support */ 765 Masking, 766 767 /* AVX512 broadcast support. The number of bytes to broadcast is 768 1 << (Broadcast - 1): 769 1: Byte broadcast. 770 2: Word broadcast. 771 3: Dword broadcast. 772 4: Qword broadcast. 773 */ 774 #define BYTE_BROADCAST 1 775 #define WORD_BROADCAST 2 776 #define DWORD_BROADCAST 3 777 #define QWORD_BROADCAST 4 778 Broadcast, 779 780 /* Static rounding control is supported. */ 781 StaticRounding, 782 783 /* Supress All Exceptions is supported. */ 784 SAE, 785 786 /* Compressed Disp8*N attribute. */ 787 #define DISP8_SHIFT_VL 7 788 Disp8MemShift, 789 790 /* Support encoding optimization. */ 791 Optimize, 792 793 /* Language dialect. NOTE: Order matters! */ 794 #define INTEL_SYNTAX 1 795 #define ATT_SYNTAX 2 796 #define ATT_MNEMONIC 3 797 Dialect, 798 799 /* Mnemonic suffix permitted in Intel syntax. */ 800 IntelSuffix, 801 802 /* ISA64: Don't change the order without other code adjustments. 803 0: Common to AMD64 and Intel64. 804 1: AMD64. 805 2: Intel64. 806 3: Only in Intel64. 807 */ 808 #define AMD64 1 809 #define INTEL64 2 810 #define INTEL64ONLY 3 811 ISA64, 812 813 /* egprs (r16-r31) on instruction illegal. We also use it to judge 814 whether the instruction supports pseudo-prefix {rex2}. */ 815 NoEgpr, 816 817 /* No CSPAZO flags update indication. */ 818 NF, 819 820 /* Instrucion requires REX2 prefix. */ 821 Rex2, 822 823 /* The last bitfield in i386_opcode_modifier. */ 824 Opcode_Modifier_Num 825 }; 826 827 typedef struct i386_opcode_modifier 828 { 829 unsigned int d:1; 830 unsigned int w:1; 831 unsigned int load:1; 832 unsigned int modrm:1; 833 unsigned int jump:3; 834 unsigned int floatmf:1; 835 unsigned int size:2; 836 unsigned int checkoperandsize:1; 837 unsigned int operandconstraint:4; 838 unsigned int mnemonicsize:2; 839 unsigned int no_bsuf:1; 840 unsigned int no_wsuf:1; 841 unsigned int no_lsuf:1; 842 unsigned int no_ssuf:1; 843 unsigned int no_qsuf:1; 844 unsigned int fwait:1; 845 unsigned int isstring:2; 846 unsigned int regmem:1; 847 unsigned int bndprefixok:1; 848 unsigned int prefixok:3; 849 unsigned int isprefix:1; 850 unsigned int immext:1; 851 unsigned int norex64:1; 852 unsigned int vex:2; 853 unsigned int vexvvvv:2; 854 unsigned int vexw:2; 855 unsigned int opcodeprefix:2; 856 unsigned int sib:3; 857 unsigned int sse2avx:1; 858 unsigned int evex:3; 859 unsigned int masking:1; 860 unsigned int broadcast:3; 861 unsigned int staticrounding:1; 862 unsigned int sae:1; 863 unsigned int disp8memshift:3; 864 unsigned int optimize:1; 865 unsigned int dialect:2; 866 unsigned int intelsuffix:1; 867 unsigned int isa64:2; 868 unsigned int noegpr:1; 869 unsigned int nf:1; 870 unsigned int rex2:1; 871 } i386_opcode_modifier; 872 873 /* Operand classes. */ 874 875 #define CLASS_WIDTH 4 876 enum operand_class 877 { 878 ClassNone, 879 Reg, /* GPRs, distinguished by operand size */ 880 SReg, /* Segment register */ 881 RegFP, /* FP regs */ 882 RegCR, /* Control register */ 883 RegDR, /* Debug register */ 884 RegTR, /* Test register */ 885 RegMMX, /* MMX register */ 886 RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */ 887 RegMask, /* Vector Mask register */ 888 RegBND, /* Bound register */ 889 }; 890 891 /* Special operand instances. */ 892 893 #define INSTANCE_WIDTH 3 894 enum operand_instance 895 { 896 InstanceNone, 897 Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */ 898 RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */ 899 RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */ 900 RegB, /* %bl / %bx / %ebx / %rbx */ 901 }; 902 903 /* Position of operand_type bits. */ 904 905 enum 906 { 907 /* Class and Instance */ 908 ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1, 909 /* 1 bit immediate */ 910 Imm1, 911 /* 8 bit immediate */ 912 Imm8, 913 /* 8 bit immediate sign extended */ 914 Imm8S, 915 /* 16 bit immediate */ 916 Imm16, 917 /* 32 bit immediate */ 918 Imm32, 919 /* 32 bit immediate sign extended */ 920 Imm32S, 921 /* 64 bit immediate */ 922 Imm64, 923 /* 8bit/16bit/32bit displacements are used in different ways, 924 depending on the instruction. For jumps, they specify the 925 size of the PC relative displacement, for instructions with 926 memory operand, they specify the size of the offset relative 927 to the base register, and for instructions with memory offset 928 such as `mov 1234,%al' they specify the size of the offset 929 relative to the segment base. */ 930 /* 8 bit displacement */ 931 Disp8, 932 /* 16 bit displacement */ 933 Disp16, 934 /* 32 bit displacement (64-bit: sign-extended) */ 935 Disp32, 936 /* 64 bit displacement */ 937 Disp64, 938 /* Register which can be used for base or index in memory operand. */ 939 BaseIndex, 940 /* BYTE size. */ 941 Byte, 942 /* WORD size. 2 byte */ 943 Word, 944 /* DWORD size. 4 byte */ 945 Dword, 946 /* FWORD size. 6 byte */ 947 Fword, 948 /* QWORD size. 8 byte */ 949 Qword, 950 /* TBYTE size. 10 byte */ 951 Tbyte, 952 /* XMMWORD size. */ 953 Xmmword, 954 /* YMMWORD size. */ 955 Ymmword, 956 /* ZMMWORD size. */ 957 Zmmword, 958 /* TMMWORD size. */ 959 Tmmword, 960 /* Unspecified memory size. */ 961 Unspecified, 962 963 /* The number of bits in i386_operand_type. */ 964 OTNum 965 }; 966 967 #define OTNumOfUints \ 968 ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1) 969 #define OTNumOfBits \ 970 (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) 971 972 /* If you get a compiler error for zero width of the unused field, 973 comment it out. */ 974 #define OTUnused OTNum 975 976 typedef union i386_operand_type 977 { 978 struct 979 { 980 unsigned int class:CLASS_WIDTH; 981 unsigned int instance:INSTANCE_WIDTH; 982 unsigned int imm1:1; 983 unsigned int imm8:1; 984 unsigned int imm8s:1; 985 unsigned int imm16:1; 986 unsigned int imm32:1; 987 unsigned int imm32s:1; 988 unsigned int imm64:1; 989 unsigned int disp8:1; 990 unsigned int disp16:1; 991 unsigned int disp32:1; 992 unsigned int disp64:1; 993 unsigned int baseindex:1; 994 unsigned int byte:1; 995 unsigned int word:1; 996 unsigned int dword:1; 997 unsigned int fword:1; 998 unsigned int qword:1; 999 unsigned int tbyte:1; 1000 unsigned int xmmword:1; 1001 unsigned int ymmword:1; 1002 unsigned int zmmword:1; 1003 unsigned int tmmword:1; 1004 unsigned int unspecified:1; 1005 #ifdef OTUnused 1006 unsigned int unused:(OTNumOfBits - OTUnused); 1007 #endif 1008 } bitfield; 1009 unsigned int array[OTNumOfUints]; 1010 } i386_operand_type; 1011 1012 typedef struct insn_template 1013 { 1014 /* instruction name sans width suffix ("mov" for movl insns) */ 1015 unsigned int mnem_off; 1016 1017 /* Bitfield arrangement is such that individual fields can be easily 1018 extracted (in native builds at least) - either by at most a masking 1019 operation (base_opcode, operands), or by just a (signed) right shift 1020 (extension_opcode). Please try to maintain this property. */ 1021 1022 /* base_opcode is the fundamental opcode byte without optional 1023 prefix(es). */ 1024 unsigned int base_opcode:16; 1025 #define Opcode_D 0x2 /* Direction bit: 1026 set if Reg --> Regmem; 1027 unset if Regmem --> Reg. */ 1028 #define Opcode_FloatR 0x8 /* ModR/M bit to swap src/dest for float insns. */ 1029 #define Opcode_FloatD 0x4 /* Direction bit for float insns. */ 1030 #define Opcode_ExtD 0x1 /* Direction bit for extended opcode space insns. */ 1031 #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ 1032 /* The next value is arbitrary, as long as it's non-zero and distinct 1033 from all other values above. */ 1034 #define Opcode_VexW 0xf /* Operand order controlled by VEX.W. */ 1035 1036 /* how many operands */ 1037 unsigned int operands:3; 1038 1039 /* opcode space */ 1040 unsigned int opcode_space:4; 1041 /* Opcode encoding space (values chosen to be usable directly in 1042 VEX/XOP mmmmm and EVEX mmm fields): 1043 0: Base opcode space. 1044 1: 0F opcode prefix / space. 1045 2: 0F38 opcode prefix / space. 1046 3: 0F3A opcode prefix / space. 1047 4: MAP4 opcode prefix / space. 1048 5: MAP5 opcode prefix / space. 1049 6: MAP6 opcode prefix / space. 1050 7: MAP7 opcode prefix / space. 1051 8: XOP 08 opcode space. 1052 9: XOP 09 opcode space. 1053 A: XOP 0A opcode space. 1054 */ 1055 #define SPACE_BASE 0 1056 #define SPACE_0F 1 1057 #define SPACE_0F38 2 1058 #define SPACE_0F3A 3 1059 #define SPACE_MAP4 4 1060 #define SPACE_MAP5 5 1061 #define SPACE_MAP6 6 1062 #define SPACE_MAP7 7 1063 #define SPACE_XOP08 8 1064 #define SPACE_XOP09 9 1065 #define SPACE_XOP0A 0xA 1066 1067 /* (Fake) base opcode value for pseudo prefixes. */ 1068 #define PSEUDO_PREFIX 0 1069 1070 /* extension_opcode is the 3 bit extension for group <n> insns. 1071 This field is also used to store the 8-bit opcode suffix for the 1072 AMD 3DNow! instructions. 1073 If this template has no extension opcode (the usual case) use None 1074 Instructions */ 1075 signed int extension_opcode:9; 1076 #define None (-1) /* If no extension_opcode is possible. */ 1077 1078 /* Pseudo prefixes. */ 1079 #define Prefix_Disp8 0 /* {disp8} */ 1080 #define Prefix_Disp16 1 /* {disp16} */ 1081 #define Prefix_Disp32 2 /* {disp32} */ 1082 #define Prefix_Load 3 /* {load} */ 1083 #define Prefix_Store 4 /* {store} */ 1084 #define Prefix_VEX 5 /* {vex} */ 1085 #define Prefix_VEX3 6 /* {vex3} */ 1086 #define Prefix_EVEX 7 /* {evex} */ 1087 #define Prefix_REX 8 /* {rex} */ 1088 #define Prefix_REX2 9 /* {rex2} */ 1089 #define Prefix_NoOptimize 10 /* {nooptimize} */ 1090 #define Prefix_NF 11 /* {nf} */ 1091 #define Prefix_NoImm8s 12 /* {noimm8s} */ 1092 1093 /* the bits in opcode_modifier are used to generate the final opcode from 1094 the base_opcode. These bits also are used to detect alternate forms of 1095 the same instruction */ 1096 i386_opcode_modifier opcode_modifier; 1097 1098 /* cpu feature attributes */ 1099 i386_cpu_attr cpu, cpu_any; 1100 1101 /* operand_types[i] describes the type of operand i. This is made 1102 by OR'ing together all of the possible type masks. (e.g. 1103 'operand_types[i] = Reg|Imm' specifies that operand i can be 1104 either a register or an immediate operand. */ 1105 i386_operand_type operand_types[MAX_OPERANDS]; 1106 } 1107 insn_template; 1108 1109 /* these are for register name --> number & type hash lookup */ 1110 typedef struct 1111 { 1112 char reg_name[8]; 1113 i386_operand_type reg_type; 1114 unsigned char reg_flags; 1115 #define RegRex 0x1 /* Extended register. */ 1116 #define RegRex64 0x2 /* Extended 8 bit register. */ 1117 #define RegVRex 0x4 /* Extended vector register. */ 1118 #define RegRex2 0x8 /* Extended GPRs R16R31 register. */ 1119 unsigned char reg_num; 1120 #define RegIP ((unsigned char ) ~0) 1121 /* EIZ and RIZ are fake index registers. */ 1122 #define RegIZ (RegIP - 1) 1123 /* FLAT is a fake segment register (Intel mode). */ 1124 #define RegFlat ((unsigned char) ~0) 1125 unsigned char dw2_regnum[2]; 1126 #define Dw2Inval 0xff 1127 } 1128 reg_entry; 1129
Indexes created Mon Jun 29 00:24:49 UTC 2026