| /src/sys/arch/arm/nvidia/ |
| soc_tegra124.c | 74 for (u_int cpuindex = 1; cpuindex < arm_cpu_max; cpuindex++) { local in function:tegra124_mpstart
82 tegra_pmc_power(tegra_cpu_pmu[cpuindex], true);
86 if (cpu_hatched_p(cpuindex))
93 cpuindex);
|
| /src/sys/arch/riscv/fdt/ |
| cpu_fdt.c | 77 u_int cpuindex = 1; local in function:riscv_fdt_cpu_bootstrap
115 KASSERT(cpuindex < MAXCPUS);
116 cpu_hartindex[hartid] = cpuindex++;
132 u_int cpuindex = 1; local in function:riscv_fdt_cpu_mpstart
146 struct sbiret sbiret = sbi_hart_start(hartid, entry, cpuindex);
166 if (cpu_hatched_p(cpuindex))
173 hartid, cpuindex);
176 cpuindex++;
|
| /src/sys/arch/arm/vexpress/ |
| vexpress_platform.c | 141 for (u_int cpuindex = 1; cpuindex < arm_cpu_max; cpuindex++) { local in function:vexpress_a15_smp_init
144 if (cpu_hatched_p(cpuindex))
151 cpuindex);
|
| /src/sys/arch/evbarm/bcm53xx/ |
| bcm53xx_machdep.c | 243 for (u_int cpuindex = 1; cpuindex < arm_cpu_max; cpuindex++) { local in function:bcm53xx_mpstart
246 if (cpu_hatched_p(cpuindex))
253 cpuindex);
|
| /src/sys/arch/arm/fdt/ |
| cpu_fdt.c | 146 u_int cpuindex; local in function:arm_fdt_cpu_bootstrap
163 cpuindex = 1;
174 KASSERT(cpuindex < MAXCPUS);
175 cpu_mpidr[cpuindex] = mpidr;
176 cpu_dcache_wb_range((vaddr_t)&cpu_mpidr[cpuindex],
177 sizeof(cpu_mpidr[cpuindex]));
179 cpuindex++;
224 u_int cpuindex, i; local in function:arm_fdt_cpu_mpstart
238 cpuindex = 1;
269 if (cpu_hatched_p(cpuindex))
[all...] |
| /src/sys/arch/arm/acpi/ |
| cpu_acpi.c | 115 const u_int cpuindex = device_unit(self); local in function:cpu_acpi_attach
118 cpu_mpidr[cpuindex] = mpidr;
119 cpu_dcache_wb_range((vaddr_t)&cpu_mpidr[cpuindex],
120 sizeof(cpu_mpidr[cpuindex]));
132 if (cpu_hatched_p(cpuindex))
|
| /src/sys/arch/riscv/riscv/ |
| cpu_subr.c | 119 for (u_int cpuindex = 1; cpuindex < ncpu; cpuindex++) { local in function:cpu_boot_secondary_processors
120 if (!cpu_hatched_p(cpuindex))
123 const size_t off = cpuindex / CPUINDEX_DIVISOR;
124 const u_long bit = __BIT(cpuindex % CPUINDEX_DIVISOR);
131 struct cpu_info *ci = &cpu_info_store[cpuindex];
141 cpu_hatched_p(u_int cpuindex)
143 const u_int off = cpuindex / CPUINDEX_DIVISOR;
144 const u_int bit = cpuindex % CPUINDEX_DIVISOR
[all...] |
| /src/sys/arch/arm/samsung/ |
| exynos_platform.c | 106 u_int cpuindex, n; local in function:exynos5800_mpstart
142 cpuindex = 1;
166 started |= __BIT(cpuindex);
171 aprint_error("cpu%d: WARNING: AP failed to power on\n", cpuindex);
183 if (cpu_hatched_p(cpuindex))
188 aprint_error("cpu%d: WARNING: AP failed to start\n", cpuindex);
191 cpuindex++;
|
| /src/sys/arch/arm/xilinx/ |
| zynq_platform.c | 196 const u_int cpuindex = 1; local in function:zynq_platform_mpstart
198 if (cpu_hatched_p(cpuindex)) {
204 cpuindex);
|
| /src/sys/arch/arm/cortex/ |
| gicv3.c | 720 for (int cpuindex = 0; cpuindex < ncpu; cpuindex++) { local in function:gicv3_lpi_init
721 gicv3_dma_alloc(sc, &sc->sc_lpipend[cpuindex], lpipend_sz, 0x10000);
722 KASSERT((sc->sc_lpipend[cpuindex].segs[0].ds_addr & ~GICR_PENDBASER_Physical_Address) == 0);
|
| /src/sys/dev/ic/ |
| nvme.c | 1861 u_int cpuindex = cpu_index((bp && bp->b_ci) ? bp->b_ci : curcpu()); local in function:nvme_ccb_get_bio
1869 struct nvme_queue *q = sc->sc_q[(cpuindex + qoff) % sc->sc_nq];
|
