HomeSort by: relevance | last modified time | path
    Searched defs:csr (Results 1 - 25 of 161) sorted by relevancy

1 2 3 4 5 6 7

  /src/sys/arch/ews4800mips/stand/common/
cons_zs.c 50 zs_set_addr(uint32_t csr, uint32_t data, int clock)
53 zs.csr = (volatile uint8_t *)csr;
65 *zs.csr = reg; \
66 *zs.csr = val; \
92 *zs.csr = ZSWR0_RESET_STATUS;
93 *zs.csr = ZSWR0_RESET_STATUS;
103 int csr, data; local in function:zs_cngetc
106 csr = *zs.csr;
117 int csr, data; local in function:zs_cnscan
131 int csr; local in function:zs_cnputc
    [all...]
  /src/sys/arch/pmax/pmax/
dec_3100.c 239 uint16_t csr; local in function:dec_3100_errintr
241 csr = *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR);
243 if (csr & KN01_CSR_MERR) {
248 csr = (csr & ~KN01_CSR_MBZ) | 0xff;
249 *(volatile uint16_t *)MIPS_PHYS_TO_KSEG1(KN01_SYS_CSR) = csr;
dec_3max.c 130 uint32_t csr; local in function:dec_3max_init
153 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR);
154 csr &= ~(KN02_CSR_WRESERVED|KN02_CSR_IOINTEN|KN02_CSR_CORRECT|0xff);
155 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
227 uint32_t csr; local in function:dec_3max_intr_establish
239 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) &
241 csr |= (kn02intrs[i].intrbit << 16);
242 *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR) = csr;
256 uint32_t csr; local in function:dec_3max_intr
262 csr = *(volatile uint32_t *)MIPS_PHYS_TO_KSEG1(KN02_SYS_CSR)
317 uint32_t erradr, csr; local in function:dec_3max_errintr
    [all...]
  /src/sys/dev/pci/
bha_pci.c 97 pcireg_t csr; local in function:bha_pci_attach
127 csr = pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
129 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_IO_ENABLE);
dpt_pci.c 88 pcireg_t csr; local in function:dpt_pci_attach
114 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
116 csr | PCI_COMMAND_MASTER_ENABLE);
fwohci_pci.c 102 uint32_t csr; local in function:fwohci_pci_attach
125 csr = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
126 csr |= PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE;
127 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, csr);
ohci_pci.c 91 pcireg_t csr; local in function:ohci_pci_attach
105 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
107 printf("csr: %08x\n", csr);
109 if ((csr & PCI_COMMAND_MEM_ENABLE) == 0) {
132 csr | PCI_COMMAND_MASTER_ENABLE);
  /src/sys/arch/powerpc/ibm4xx/pci/
pci_machdep.c 199 pcireg_t csr; local in function:ibm4xx_pci_conf_hook
202 csr = ibm4xx_pci_conf_read(v, tag, PCI_CLASS_REG);
203 csr |= (PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1))
205 ibm4xx_pci_conf_write(v, tag, PCI_CLASS_REG, csr);
  /src/sys/arch/atari/pci/
pci_milan.c 172 uint32_t csr; local in function:milan_vga_init
177 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
178 csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
179 csr |= PCI_COMMAND_MASTER_ENABLE;
180 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
pci_tseng.c 84 uint32_t csr; local in function:tseng_init
93 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
94 csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
95 csr |= PCI_COMMAND_MASTER_ENABLE;
96 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
pci_hades.c 231 uint32_t csr; local in function:ati_vga_init
236 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
237 csr |= (PCI_COMMAND_MEM_ENABLE|PCI_COMMAND_IO_ENABLE);
238 csr |= PCI_COMMAND_MASTER_ENABLE;
239 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
  /src/sys/arch/sh3/dev/
adc.c 75 ADC_(CSR) = 0;
124 uint8_t csr; local in function:adc_sample_channel
141 csr = ADC_(CSR);
142 if ((csr & SH7709_ADCSR_ADST) != 0) {
144 snprintb(bits, sizeof(bits), SH7709_ADCSR_BITS, csr);
145 printf("adc_sample_channel(%d): CSR=%s", chan, bits);
155 ADC_(CSR) = chan | SH7709_ADCSR_ADST | SH7709_ADCSR_CKS;
158 csr = ADC_(CSR);
    [all...]
  /src/sys/arch/cobalt/stand/boot/
zs.c 140 uint8_t csr; local in function:zs_putc
143 csr = zs_read(dev, ZS_CSR);
144 } while ((csr & ZSRR0_TX_READY) == 0);
152 uint8_t csr, data; local in function:zs_getc
155 csr = zs_read(dev, ZS_CSR);
156 } while ((csr & ZSRR0_RX_READY) == 0);
165 uint8_t csr, data; local in function:zs_scan
167 csr = zs_read(dev, ZS_CSR);
168 if ((csr & ZSRR0_RX_READY) == 0)
  /src/sys/arch/amiga/dev/
mlhsc.c 183 u_char csr; local in function:mlhsc_dma_xfer_in
190 csr = *dev->sci_bus_csr;
191 __USE(csr);
193 QPRINTF(("mlhdma_in %d, csr=%02x\n", len, csr));
209 len, csr, wait);
245 len, csr, wait);
269 u_char csr; local in function:mlhsc_dma_xfer_out
273 csr = *dev->sci_bus_csr;
274 __USE(csr);
    [all...]
  /src/sys/arch/mvmeppc/isa/
mkclock_isa.c 80 uint8_t csr, ocsr; local in function:mkclock_isa_match
117 csr = ocsr | MK48TXX_CSR_READ;
118 mkclock_isa_nvwr(sc, MK48T18_CLKOFF + MK48TXX_ICSR, csr);
120 if (mkclock_isa_nvrd(sc, MK48T18_CLKOFF + MK48TXX_ICSR) != csr)
131 mkclock_isa_nvwr(sc, MK48T18_CLKOFF + MK48TXX_ICSR, csr);
  /src/sys/dev/cardbus/
fwohci_cardbus.c 93 pcireg_t csr; local in function:fwohci_cardbus_attach
120 csr = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
122 csr | PCI_COMMAND_MASTER_ENABLE | PCI_COMMAND_MEM_ENABLE);
ohci_cardbus.c 110 pcireg_t csr; local in function:ohci_cardbus_attach
134 csr = Cardbus_conf_read(ct, ca->ca_tag, PCI_COMMAND_STATUS_REG);
136 csr | PCI_COMMAND_MASTER_ENABLE
  /src/sys/dev/sbus/
dma_sbus.c 176 uint32_t csr; local in function:dmaattach_sbus
179 * set the appropriate bit in the ledma csr so that it
185 csr = L64854_GCSR(sc);
187 csr |= E_TP_AUI;
189 csr &= ~E_TP_AUI;
192 csr |= E_TP_AUI;
194 L64854_SCSR(sc, csr);
  /src/sys/arch/sun3/dev/
dma.c 156 printf("%s: line %d: CSR = 0x%x\n", \
206 uint32_t csr; local in function:dma_reset
212 csr = DMA_GCSR(sc);
214 csr |= D_RESET; /* reset DMA */
215 DMA_SCSR(sc, csr);
219 csr = DMA_GCSR(sc);
220 csr &= ~D_RESET; /* de-assert reset line */
221 DMA_SCSR(sc, csr);
230 csr = DMA_GCSR(sc);
231 csr |= D_INT_EN; /* enable interrupts *
248 uint32_t csr; local in function:dma_setup
311 uint32_t csr; local in function:espdmaintr
    [all...]
  /src/sys/dev/ic/
mk48txx.c 110 uint8_t csr; local in function:mk48txx_gettime_ymdhms
115 csr = (*sc->sc_nvrd)(sc, clkoff + MK48TXX_ICSR);
116 csr |= MK48TXX_CSR_READ;
117 (*sc->sc_nvwr)(sc, clkoff + MK48TXX_ICSR, csr);
128 year += 100*bcdtobin(csr & MK48TXX_CSR_CENT_MASK);
139 csr = (*sc->sc_nvrd)(sc, clkoff + MK48TXX_ICSR);
140 csr &= ~MK48TXX_CSR_READ;
141 (*sc->sc_nvwr)(sc, clkoff + MK48TXX_ICSR, csr);
155 uint8_t csr; local in function:mk48txx_settime_ymdhms
173 csr = (*sc->sc_nvrd)(sc, clkoff + MK48TXX_ICSR)
    [all...]
  /src/sys/arch/cobalt/pci/
pci_machdep.c 275 pcireg_t csr; local in function:pci_conf_hook
280 csr = pci_conf_read(pc, tag, APO_VIAIDECONF);
282 csr | APO_IDECONF_EN(1));
  /src/sys/arch/evbarm/imx31/
imx31lk_pcic.c 146 uint16_t csr; local in function:imx31lk_pcic_read
148 csr = bus_space_read_2(iot, ioh, SCOOP_CSR);
152 if (csr & SCP_CSR_MISSING)
  /src/sys/arch/hp300/hp300/
clock.c 111 volatile u_char csr; local in function:hp300_calibrate_delay
142 csr = clk->clk_sr;
143 if (csr & CLK_INT1) {
157 csr = clk->clk_sr;
158 } while ((csr & CLK_INT1) == 0);
  /src/sys/arch/sparc/dev/
esp_obio.c 322 uint32_t csr; local in function:esp_dma_stop
324 csr = L64854_GCSR(esc->sc_dma);
325 csr &= ~D_EN_DMA;
326 L64854_SCSR(esc->sc_dma, csr);
  /src/sys/arch/zaurus/dev/
scoop_pcic.c 167 uint16_t csr; local in function:scoop_pcic_read
169 csr = bus_space_read_2(iot, ioh, SCOOP_CSR);
173 if (csr & SCP_CSR_MISSING)

Completed in 23 milliseconds

1 2 3 4 5 6 7