| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/disp/ |
| nouveau_nvkm_engine_disp_hdmigm200.c | 36 const u32 ctrl = scdc & 0x3; local in function:gm200_hdmi_scdc
38 nvkm_mask(device, 0x61c5bc + hoff, 0x00000003, ctrl);
|
| nouveau_nvkm_engine_disp_dmacgp102.c | 38 int ctrl = chan->chid.ctrl; local in function:gp102_disp_dmac_init
42 nvkm_wr32(device, 0x611494 + (ctrl * 0x0010), chan->push);
43 nvkm_wr32(device, 0x611498 + (ctrl * 0x0010), 0x00010000);
44 nvkm_wr32(device, 0x61149c + (ctrl * 0x0010), 0x00000001);
45 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000010, 0x00000010);
46 nvkm_wr32(device, 0x640000 + (ctrl * 0x1000), 0x00000000);
47 nvkm_wr32(device, 0x610490 + (ctrl * 0x0010), 0x00000013);
51 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x80000000))
55 nvkm_rd32(device, 0x610490 + (ctrl * 0x10)))
[all...] |
| nouveau_nvkm_engine_disp_hdmig84.c | 36 const u32 ctrl = 0x40000000 * enable | local in function:g84_hdmi_ctrl
47 if (!(ctrl & 0x40000000)) {
95 nvkm_mask(device, 0x6165a4 + hoff, 0x5f1f007f, ctrl);
|
| nouveau_nvkm_engine_disp_hdmigf119.c | 36 const u32 ctrl = 0x40000000 * enable | local in function:gf119_hdmi_ctrl
46 if (!(ctrl & 0x40000000)) {
86 nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl);
|
| nouveau_nvkm_engine_disp_hdmigk104.c | 36 const u32 ctrl = 0x40000000 * enable | local in function:gk104_hdmi_ctrl
47 if (!(ctrl & 0x40000000)) {
86 nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl);
|
| nouveau_nvkm_engine_disp_hdmigt215.c | 36 const u32 ctrl = 0x40000000 * enable | local in function:gt215_hdmi_ctrl
47 if (!(ctrl & 0x40000000)) {
95 nvkm_mask(device, 0x61c5a4 + soff, 0x5f1f007f, ctrl);
|
| nouveau_nvkm_engine_disp_hdmigv100.c | 34 const u32 ctrl = 0x40000000 * enable | local in function:gv100_hdmi_ctrl
45 if (!(ctrl & 0x40000000)) {
89 nvkm_mask(device, 0x6165c0 + hoff, 0x401f007f, ctrl);
|
| nouveau_nvkm_engine_disp_dacgf119.c | 42 u32 ctrl = nvkm_rd32(device, 0x640180 + coff); local in function:gf119_dac_state
44 state->proto_evo = (ctrl & 0x00000f00) >> 8;
52 state->head = ctrl & 0x0000000f;
|
| nouveau_nvkm_engine_disp_dmacgf119.c | 48 int ctrl = chan->chid.ctrl; local in function:gf119_disp_dmac_fini
52 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00001010, 0x00001000);
53 nvkm_mask(device, 0x610490 + (ctrl * 0x0010), 0x00000003, 0x00000000);
55 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x001e0000))
59 nvkm_rd32(device, 0x610490 + (ctrl * 0x10)));
68 int ctrl = chan->chid.ctrl; local in function:gf119_disp_dmac_init
72 nvkm_wr32(device, 0x610494 + (ctrl * 0x0010), chan->push);
73 nvkm_wr32(device, 0x610498 + (ctrl * 0x0010), 0x00010000)
[all...] |
| nouveau_nvkm_engine_disp_piocgf119.c | 40 int ctrl = chan->chid.ctrl; local in function:gf119_disp_pioc_fini
43 nvkm_mask(device, 0x610490 + (ctrl * 0x10), 0x00000001, 0x00000000);
45 if (!(nvkm_rd32(device, 0x610490 + (ctrl * 0x10)) & 0x00030000))
49 nvkm_rd32(device, 0x610490 + (ctrl * 0x10)));
59 int ctrl = chan->chid.ctrl; local in function:gf119_disp_pioc_init
63 nvkm_wr32(device, 0x610490 + (ctrl * 0x10), 0x00000001);
65 u32 tmp = nvkm_rd32(device, 0x610490 + (ctrl * 0x10));
70 nvkm_rd32(device, 0x610490 + (ctrl * 0x10)))
[all...] |
| nouveau_nvkm_engine_disp_piocnv50.c | 40 int ctrl = chan->chid.ctrl; local in function:nv50_disp_pioc_fini
43 nvkm_mask(device, 0x610200 + (ctrl * 0x10), 0x00000001, 0x00000000);
45 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000))
49 nvkm_rd32(device, 0x610200 + (ctrl * 0x10)));
59 int ctrl = chan->chid.ctrl; local in function:nv50_disp_pioc_init
62 nvkm_wr32(device, 0x610200 + (ctrl * 0x10), 0x00002000);
64 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x00030000))
68 nvkm_rd32(device, 0x610200 + (ctrl * 0x10)))
[all...] |
| nouveau_nvkm_engine_disp_dacnv50.c | 93 u32 ctrl = nvkm_rd32(device, 0x610b58 + coff); local in function:nv50_dac_state
95 state->proto_evo = (ctrl & 0x00000f00) >> 8;
103 state->head = ctrl & 0x00000003;
|
| nouveau_nvkm_engine_disp_dmacnv50.c | 89 int ctrl = chan->chid.ctrl; local in function:nv50_disp_dmac_fini
93 nvkm_mask(device, 0x610200 + (ctrl * 0x0010), 0x00001010, 0x00001000);
94 nvkm_mask(device, 0x610200 + (ctrl * 0x0010), 0x00000003, 0x00000000);
96 if (!(nvkm_rd32(device, 0x610200 + (ctrl * 0x10)) & 0x001e0000))
100 nvkm_rd32(device, 0x610200 + (ctrl * 0x10)));
109 int ctrl = chan->chid.ctrl; local in function:nv50_disp_dmac_init
113 nvkm_wr32(device, 0x610204 + (ctrl * 0x0010), chan->push);
114 nvkm_wr32(device, 0x610208 + (ctrl * 0x0010), 0x00010000)
[all...] |
| nouveau_nvkm_engine_disp_sorgv100.c | 67 u32 ctrl = nvkm_rd32(device, 0x680300 + coff); local in function:gv100_sor_state
69 state->proto_evo = (ctrl & 0x00000f00) >> 8;
82 state->head = ctrl & 0x000000ff;
95 .ctrl = gv100_hdmi_ctrl,
|
| nouveau_nvkm_engine_disp_sornv50.c | 76 u32 ctrl = nvkm_rd32(device, 0x610b70 + coff); local in function:nv50_sor_state
78 state->proto_evo = (ctrl & 0x00000f00) >> 8;
89 state->head = ctrl & 0x00000003;
|
| nouveau_nvkm_engine_disp_piornv50.c | 78 nv50_pior_depth(struct nvkm_ior *ior, struct nvkm_ior_state *state, u32 ctrl)
88 switch ((ctrl & 0x000f0000) >> 16) {
107 u32 ctrl = nvkm_rd32(device, 0x610b80 + coff); local in function:nv50_pior_state
109 state->proto_evo = (ctrl & 0x00000f00) >> 8;
118 state->head = ctrl & 0x00000003;
119 nv50_pior_depth(pior, state, ctrl);
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/fb/ |
| ramnv40.h | 11 u32 ctrl; member in struct:nv40_ram
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/ |
| nouveau_debugfs.h | 14 struct nvif_object ctrl; member in struct:nouveau_debugfs
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/therm/ |
| nouveau_nvkm_subdev_therm_gt215.c | 38 u32 ctrl = nvkm_rd32(device, 0x00e720); local in function:gt215_therm_fan_sense
39 if (ctrl & 0x00000001)
|
| /src/sys/arch/arm/arm32/ |
| arm11_pmc.c | 117 uint32_t ctrl; local in function:delay
131 ctrl = arm11_pmc_ctrl_read();
132 if (ctrl & ARM11_PMCCTL_CCR) {
137 ctrl &= ~(ARM11_PMCCTL_CR0|ARM11_PMCCTL_CR1);
138 arm11_pmc_ctrl_write(ctrl);
|
| cortex_pmc.c | 84 uint32_t ctrl; local in function:delay
105 ctrl = armreg_pmovsr_read();
106 if (ctrl & CORTEX_CNTOFL_C) {
|
| /src/sys/arch/arm/iomd/ |
| iomd_dma.c | 61 static struct dma_ctrl ctrl[6]; variable in typeref:struct:dma_ctrl[6]
290 struct dma_ctrl *dp = &ctrl[ch];
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv50/ |
| core.h | 30 void (*ctrl)(struct nv50_core *, int or, u32 ctrl, member in struct:nv50_core_func::nv50_outp_func
|
| /src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/i2c/ |
| nouveau_nvkm_subdev_i2c_auxg94.c | 51 u32 ctrl, timeout; local in function:g94_i2c_aux_init
56 ctrl = nvkm_rd32(device, 0x00e4e4 + (aux->ch * 0x50));
59 AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl);
62 } while (ctrl & 0x03010000);
68 ctrl = nvkm_rd32(device, 0x00e4e4 + (aux->ch * 0x50));
71 AUX_ERR(&aux->base, "magic wait %08x", ctrl);
75 } while ((ctrl & 0x03000000) != urep);
87 u32 ctrl, stat, timeout, retries = 0; local in function:g94_i2c_aux_xfer
112 ctrl = nvkm_rd32(device, 0x00e4e4 + base);
113 ctrl &= ~0x0001f1ff
[all...] |
| nouveau_nvkm_subdev_i2c_auxgm200.c | 51 u32 ctrl, timeout; local in function:gm200_i2c_aux_init
56 ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50));
59 AUX_ERR(&aux->base, "begin idle timeout %08x", ctrl);
62 } while (ctrl & 0x03010000);
68 ctrl = nvkm_rd32(device, 0x00d954 + (aux->ch * 0x50));
71 AUX_ERR(&aux->base, "magic wait %08x", ctrl);
75 } while ((ctrl & 0x03000000) != urep);
87 u32 ctrl, stat, timeout, retries = 0; local in function:gm200_i2c_aux_xfer
112 ctrl = nvkm_rd32(device, 0x00d954 + base);
113 ctrl &= ~0x0001f1ff
[all...] |
