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      1 /*	$NetBSD: edid.h,v 1.2 2021/12/18 23:45:31 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice (including the next
     14  * paragraph) shall be included in all copies or substantial portions of the
     15  * Software.
     16  *
     17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
     21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
     22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
     23  * SOFTWARE.
     24  *
     25  * Authors:
     26  *    Ke Yu
     27  *    Zhiyuan Lv <zhiyuan.lv (at) intel.com>
     28  *
     29  * Contributors:
     30  *    Terrence Xu <terrence.xu (at) intel.com>
     31  *    Changbin Du <changbin.du (at) intel.com>
     32  *    Bing Niu <bing.niu (at) intel.com>
     33  *    Zhi Wang <zhi.a.wang (at) intel.com>
     34  *
     35  */
     36 
     37 #ifndef _GVT_EDID_H_
     38 #define _GVT_EDID_H_
     39 
     40 #include <linux/types.h>
     41 
     42 struct intel_vgpu;
     43 
     44 #define EDID_SIZE		128
     45 #define EDID_ADDR		0x50 /* Linux hvm EDID addr */
     46 
     47 #define GVT_AUX_NATIVE_WRITE			0x8
     48 #define GVT_AUX_NATIVE_READ			0x9
     49 #define GVT_AUX_I2C_WRITE			0x0
     50 #define GVT_AUX_I2C_READ			0x1
     51 #define GVT_AUX_I2C_STATUS			0x2
     52 #define GVT_AUX_I2C_MOT				0x4
     53 #define GVT_AUX_I2C_REPLY_ACK			0x0
     54 
     55 struct intel_vgpu_edid_data {
     56 	bool data_valid;
     57 	unsigned char edid_block[EDID_SIZE];
     58 };
     59 
     60 enum gmbus_cycle_type {
     61 	GMBUS_NOCYCLE	= 0x0,
     62 	NIDX_NS_W	= 0x1,
     63 	IDX_NS_W	= 0x3,
     64 	GMBUS_STOP	= 0x4,
     65 	NIDX_STOP	= 0x5,
     66 	IDX_STOP	= 0x7
     67 };
     68 
     69 /*
     70  * States of GMBUS
     71  *
     72  * GMBUS0-3 could be related to the EDID virtualization. Another two GMBUS
     73  * registers, GMBUS4 (interrupt mask) and GMBUS5 (2 byte indes register), are
     74  * not considered here. Below describes the usage of GMBUS registers that are
     75  * cared by the EDID virtualization
     76  *
     77  * GMBUS0:
     78  *      R/W
     79  *      port selection. value of bit0 - bit2 corresponds to the GPIO registers.
     80  *
     81  * GMBUS1:
     82  *      R/W Protect
     83  *      Command and Status.
     84  *      bit0 is the direction bit: 1 is read; 0 is write.
     85  *      bit1 - bit7 is slave 7-bit address.
     86  *      bit16 - bit24 total byte count (ignore?)
     87  *
     88  * GMBUS2:
     89  *      Most of bits are read only except bit 15 (IN_USE)
     90  *      Status register
     91  *      bit0 - bit8 current byte count
     92  *      bit 11: hardware ready;
     93  *
     94  * GMBUS3:
     95  *      Read/Write
     96  *      Data for transfer
     97  */
     98 
     99 /* From hw specs, Other phases like START, ADDRESS, INDEX
    100  * are invisible to GMBUS MMIO interface. So no definitions
    101  * in below enum types
    102  */
    103 enum gvt_gmbus_phase {
    104 	GMBUS_IDLE_PHASE = 0,
    105 	GMBUS_DATA_PHASE,
    106 	GMBUS_WAIT_PHASE,
    107 	//GMBUS_STOP_PHASE,
    108 	GMBUS_MAX_PHASE
    109 };
    110 
    111 struct intel_vgpu_i2c_gmbus {
    112 	unsigned int total_byte_count; /* from GMBUS1 */
    113 	enum gmbus_cycle_type cycle_type;
    114 	enum gvt_gmbus_phase phase;
    115 };
    116 
    117 struct intel_vgpu_i2c_aux_ch {
    118 	bool i2c_over_aux_ch;
    119 	bool aux_ch_mot;
    120 };
    121 
    122 enum i2c_state {
    123 	I2C_NOT_SPECIFIED = 0,
    124 	I2C_GMBUS = 1,
    125 	I2C_AUX_CH = 2
    126 };
    127 
    128 /* I2C sequences cannot interleave.
    129  * GMBUS and AUX_CH sequences cannot interleave.
    130  */
    131 struct intel_vgpu_i2c_edid {
    132 	enum i2c_state state;
    133 
    134 	unsigned int port;
    135 	bool slave_selected;
    136 	bool edid_available;
    137 	unsigned int current_edid_read;
    138 
    139 	struct intel_vgpu_i2c_gmbus gmbus;
    140 	struct intel_vgpu_i2c_aux_ch aux_ch;
    141 };
    142 
    143 void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu);
    144 
    145 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
    146 		unsigned int offset, void *p_data, unsigned int bytes);
    147 
    148 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
    149 		unsigned int offset, void *p_data, unsigned int bytes);
    150 
    151 void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
    152 		int port_idx,
    153 		unsigned int offset,
    154 		void *p_data);
    155 
    156 #endif /*_GVT_EDID_H_*/
    157