1 /* $NetBSD: amdgpu_hw_ddc.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_hw_ddc.c,v 1.3 2021/12/19 12:02:39 riastradh Exp $"); 30 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 34 #include "dm_services.h" 35 36 #include "include/gpio_interface.h" 37 #include "include/gpio_types.h" 38 #include "hw_gpio.h" 39 #include "hw_ddc.h" 40 41 #include "reg_helper.h" 42 #include "gpio_regs.h" 43 44 45 #undef FN 46 #define FN(reg_name, field_name) \ 47 ddc->shifts->field_name, ddc->masks->field_name 48 49 #define CTX \ 50 ddc->base.base.ctx 51 #define REG(reg)\ 52 (ddc->regs->reg) 53 54 struct gpio; 55 56 static void dal_hw_ddc_destruct( 57 struct hw_ddc *pin) 58 { 59 dal_hw_gpio_destruct(&pin->base); 60 } 61 62 static void dal_hw_ddc_destroy( 63 struct hw_gpio_pin **ptr) 64 { 65 struct hw_ddc *pin = HW_DDC_FROM_BASE(*ptr); 66 67 dal_hw_ddc_destruct(pin); 68 69 kfree(pin); 70 71 *ptr = NULL; 72 } 73 74 static enum gpio_result set_config( 75 struct hw_gpio_pin *ptr, 76 const struct gpio_config_data *config_data) 77 { 78 struct hw_ddc *ddc = HW_DDC_FROM_BASE(ptr); 79 struct hw_gpio *hw_gpio = NULL; 80 uint32_t regval; 81 uint32_t ddc_data_pd_en = 0; 82 uint32_t ddc_clk_pd_en = 0; 83 uint32_t aux_pad_mode = 0; 84 85 hw_gpio = &ddc->base; 86 87 if (hw_gpio == NULL) { 88 ASSERT_CRITICAL(false); 89 return GPIO_RESULT_NULL_HANDLE; 90 } 91 92 regval = REG_GET_3(gpio.MASK_reg, 93 DC_GPIO_DDC1DATA_PD_EN, &ddc_data_pd_en, 94 DC_GPIO_DDC1CLK_PD_EN, &ddc_clk_pd_en, 95 AUX_PAD1_MODE, &aux_pad_mode); 96 97 switch (config_data->config.ddc.type) { 98 case GPIO_DDC_CONFIG_TYPE_MODE_I2C: 99 /* On plug-in, there is a transient level on the pad 100 * which must be discharged through the internal pull-down. 101 * Enable internal pull-down, 2.5msec discharge time 102 * is required for detection of AUX mode */ 103 if (hw_gpio->base.en != GPIO_DDC_LINE_VIP_PAD) { 104 if (!ddc_data_pd_en || !ddc_clk_pd_en) { 105 106 REG_SET_2(gpio.MASK_reg, regval, 107 DC_GPIO_DDC1DATA_PD_EN, 1, 108 DC_GPIO_DDC1CLK_PD_EN, 1); 109 110 if (config_data->type == 111 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 112 msleep(3); 113 } 114 } else { 115 uint32_t reg2 __unused; 116 uint32_t sda_pd_dis = 0; 117 uint32_t scl_pd_dis = 0; 118 119 reg2 = REG_GET_2(gpio.MASK_reg, 120 DC_GPIO_SDA_PD_DIS, &sda_pd_dis, 121 DC_GPIO_SCL_PD_DIS, &scl_pd_dis); 122 123 if (sda_pd_dis) { 124 REG_SET(gpio.MASK_reg, regval, 125 DC_GPIO_SDA_PD_DIS, 0); 126 127 if (config_data->type == 128 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 129 msleep(3); 130 } 131 132 if (!scl_pd_dis) { 133 REG_SET(gpio.MASK_reg, regval, 134 DC_GPIO_SCL_PD_DIS, 1); 135 136 if (config_data->type == 137 GPIO_CONFIG_TYPE_I2C_AUX_DUAL_MODE) 138 msleep(3); 139 } 140 } 141 142 if (aux_pad_mode) { 143 /* let pins to get de-asserted 144 * before setting pad to I2C mode */ 145 if (config_data->config.ddc.data_en_bit_present || 146 config_data->config.ddc.clock_en_bit_present) 147 /* [anaumov] in DAL2, there was 148 * dc_service_delay_in_microseconds(2000); */ 149 msleep(2); 150 151 /* set the I2C pad mode */ 152 /* read the register again, 153 * some bits may have been changed */ 154 REG_UPDATE(gpio.MASK_reg, 155 AUX_PAD1_MODE, 0); 156 } 157 158 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { 159 REG_UPDATE(dc_gpio_aux_ctrl_5, DDC_PAD_I2CMODE, 1); 160 } 161 //set DC_IO_aux_rxsel = 2'b01 162 if (ddc->regs->phy_aux_cntl != 0) { 163 REG_UPDATE(phy_aux_cntl, AUX_PAD_RXSEL, 1); 164 } 165 return GPIO_RESULT_OK; 166 case GPIO_DDC_CONFIG_TYPE_MODE_AUX: 167 /* set the AUX pad mode */ 168 if (!aux_pad_mode) { 169 REG_SET(gpio.MASK_reg, regval, 170 AUX_PAD1_MODE, 1); 171 } 172 if (ddc->regs->dc_gpio_aux_ctrl_5 != 0) { 173 REG_UPDATE(dc_gpio_aux_ctrl_5, 174 DDC_PAD_I2CMODE, 0); 175 } 176 177 return GPIO_RESULT_OK; 178 case GPIO_DDC_CONFIG_TYPE_POLL_FOR_CONNECT: 179 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 180 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 181 REG_UPDATE_3(ddc_setup, 182 DC_I2C_DDC1_ENABLE, 1, 183 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1, 184 DC_I2C_DDC1_EDID_DETECT_MODE, 0); 185 return GPIO_RESULT_OK; 186 } 187 break; 188 case GPIO_DDC_CONFIG_TYPE_POLL_FOR_DISCONNECT: 189 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 190 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 191 REG_UPDATE_3(ddc_setup, 192 DC_I2C_DDC1_ENABLE, 1, 193 DC_I2C_DDC1_EDID_DETECT_ENABLE, 1, 194 DC_I2C_DDC1_EDID_DETECT_MODE, 1); 195 return GPIO_RESULT_OK; 196 } 197 break; 198 case GPIO_DDC_CONFIG_TYPE_DISABLE_POLLING: 199 if ((hw_gpio->base.en >= GPIO_DDC_LINE_DDC1) && 200 (hw_gpio->base.en <= GPIO_DDC_LINE_DDC_VGA)) { 201 REG_UPDATE_2(ddc_setup, 202 DC_I2C_DDC1_ENABLE, 0, 203 DC_I2C_DDC1_EDID_DETECT_ENABLE, 0); 204 return GPIO_RESULT_OK; 205 } 206 break; 207 } 208 209 BREAK_TO_DEBUGGER(); 210 211 return GPIO_RESULT_NON_SPECIFIC_ERROR; 212 } 213 214 static const struct hw_gpio_pin_funcs funcs = { 215 .destroy = dal_hw_ddc_destroy, 216 .open = dal_hw_gpio_open, 217 .get_value = dal_hw_gpio_get_value, 218 .set_value = dal_hw_gpio_set_value, 219 .set_config = set_config, 220 .change_mode = dal_hw_gpio_change_mode, 221 .close = dal_hw_gpio_close, 222 }; 223 224 static void dal_hw_ddc_construct( 225 struct hw_ddc *ddc, 226 enum gpio_id id, 227 uint32_t en, 228 struct dc_context *ctx) 229 { 230 dal_hw_gpio_construct(&ddc->base, id, en, ctx); 231 ddc->base.base.funcs = &funcs; 232 } 233 234 void dal_hw_ddc_init( 235 struct hw_ddc **hw_ddc, 236 struct dc_context *ctx, 237 enum gpio_id id, 238 uint32_t en) 239 { 240 if ((en < GPIO_DDC_LINE_MIN) || (en > GPIO_DDC_LINE_MAX)) { 241 ASSERT_CRITICAL(false); 242 *hw_ddc = NULL; 243 } 244 245 *hw_ddc = kzalloc(sizeof(struct hw_ddc), GFP_KERNEL); 246 if (!*hw_ddc) { 247 ASSERT_CRITICAL(false); 248 return; 249 } 250 251 dal_hw_ddc_construct(*hw_ddc, id, en, ctx); 252 } 253 254 struct hw_gpio_pin *dal_hw_ddc_get_pin(struct gpio *gpio) 255 { 256 struct hw_ddc *hw_ddc = dal_gpio_get_ddc(gpio); 257 258 return &hw_ddc->base.base; 259 } 260
Indexes created Sun Sep 21 19:09:51 GMT 2025