1 /* $NetBSD: amdgpu_irq_service_dcn10.c,v 1.2 2021/12/18 23:45:06 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_irq_service_dcn10.c,v 1.2 2021/12/18 23:45:06 riastradh Exp $"); 30 31 #include <linux/slab.h> 32 33 #include "dm_services.h" 34 35 #include "include/logger_interface.h" 36 37 #include "../dce110/irq_service_dce110.h" 38 39 #include "dcn/dcn_1_0_offset.h" 40 #include "dcn/dcn_1_0_sh_mask.h" 41 #include "soc15_hw_ip.h" 42 #include "vega10_ip_offset.h" 43 44 #include "irq_service_dcn10.h" 45 46 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" 47 48 enum dc_irq_source to_dal_irq_source_dcn10( 49 struct irq_service *irq_service, 50 uint32_t src_id, 51 uint32_t ext_id) 52 { 53 switch (src_id) { 54 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP: 55 return DC_IRQ_SOURCE_VBLANK1; 56 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP: 57 return DC_IRQ_SOURCE_VBLANK2; 58 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP: 59 return DC_IRQ_SOURCE_VBLANK3; 60 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP: 61 return DC_IRQ_SOURCE_VBLANK4; 62 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP: 63 return DC_IRQ_SOURCE_VBLANK5; 64 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP: 65 return DC_IRQ_SOURCE_VBLANK6; 66 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 67 return DC_IRQ_SOURCE_VUPDATE1; 68 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 69 return DC_IRQ_SOURCE_VUPDATE2; 70 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 71 return DC_IRQ_SOURCE_VUPDATE3; 72 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 73 return DC_IRQ_SOURCE_VUPDATE4; 74 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 75 return DC_IRQ_SOURCE_VUPDATE5; 76 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT: 77 return DC_IRQ_SOURCE_VUPDATE6; 78 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT: 79 return DC_IRQ_SOURCE_PFLIP1; 80 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT: 81 return DC_IRQ_SOURCE_PFLIP2; 82 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT: 83 return DC_IRQ_SOURCE_PFLIP3; 84 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT: 85 return DC_IRQ_SOURCE_PFLIP4; 86 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT: 87 return DC_IRQ_SOURCE_PFLIP5; 88 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT: 89 return DC_IRQ_SOURCE_PFLIP6; 90 91 case DCN_1_0__SRCID__DC_HPD1_INT: 92 /* generic src_id for all HPD and HPDRX interrupts */ 93 switch (ext_id) { 94 case DCN_1_0__CTXID__DC_HPD1_INT: 95 return DC_IRQ_SOURCE_HPD1; 96 case DCN_1_0__CTXID__DC_HPD2_INT: 97 return DC_IRQ_SOURCE_HPD2; 98 case DCN_1_0__CTXID__DC_HPD3_INT: 99 return DC_IRQ_SOURCE_HPD3; 100 case DCN_1_0__CTXID__DC_HPD4_INT: 101 return DC_IRQ_SOURCE_HPD4; 102 case DCN_1_0__CTXID__DC_HPD5_INT: 103 return DC_IRQ_SOURCE_HPD5; 104 case DCN_1_0__CTXID__DC_HPD6_INT: 105 return DC_IRQ_SOURCE_HPD6; 106 case DCN_1_0__CTXID__DC_HPD1_RX_INT: 107 return DC_IRQ_SOURCE_HPD1RX; 108 case DCN_1_0__CTXID__DC_HPD2_RX_INT: 109 return DC_IRQ_SOURCE_HPD2RX; 110 case DCN_1_0__CTXID__DC_HPD3_RX_INT: 111 return DC_IRQ_SOURCE_HPD3RX; 112 case DCN_1_0__CTXID__DC_HPD4_RX_INT: 113 return DC_IRQ_SOURCE_HPD4RX; 114 case DCN_1_0__CTXID__DC_HPD5_RX_INT: 115 return DC_IRQ_SOURCE_HPD5RX; 116 case DCN_1_0__CTXID__DC_HPD6_RX_INT: 117 return DC_IRQ_SOURCE_HPD6RX; 118 default: 119 return DC_IRQ_SOURCE_INVALID; 120 } 121 break; 122 123 default: 124 return DC_IRQ_SOURCE_INVALID; 125 } 126 } 127 128 static bool hpd_ack( 129 struct irq_service *irq_service, 130 const struct irq_source_info *info) 131 { 132 uint32_t addr = info->status_reg; 133 uint32_t value = dm_read_reg(irq_service->ctx, addr); 134 uint32_t current_status = 135 get_reg_field_value( 136 value, 137 HPD0_DC_HPD_INT_STATUS, 138 DC_HPD_SENSE_DELAYED); 139 140 dal_irq_service_ack_generic(irq_service, info); 141 142 value = dm_read_reg(irq_service->ctx, info->enable_reg); 143 144 set_reg_field_value( 145 value, 146 current_status ? 0 : 1, 147 HPD0_DC_HPD_INT_CONTROL, 148 DC_HPD_INT_POLARITY); 149 150 dm_write_reg(irq_service->ctx, info->enable_reg, value); 151 152 return true; 153 } 154 155 static const struct irq_source_info_funcs hpd_irq_info_funcs = { 156 .set = NULL, 157 .ack = hpd_ack 158 }; 159 160 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = { 161 .set = NULL, 162 .ack = NULL 163 }; 164 165 static const struct irq_source_info_funcs pflip_irq_info_funcs = { 166 .set = NULL, 167 .ack = NULL 168 }; 169 170 static const struct irq_source_info_funcs vblank_irq_info_funcs = { 171 .set = NULL, 172 .ack = NULL 173 }; 174 175 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = { 176 .set = NULL, 177 .ack = NULL 178 }; 179 180 #define BASE_INNER(seg) \ 181 DCE_BASE__INST0_SEG ## seg 182 183 #define BASE(seg) \ 184 BASE_INNER(seg) 185 186 #define SRI(reg_name, block, id)\ 187 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 188 mm ## block ## id ## _ ## reg_name 189 190 191 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ 192 .enable_reg = SRI(reg1, block, reg_num),\ 193 .enable_mask = \ 194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 195 .enable_value = {\ 196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ 197 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ 198 },\ 199 .ack_reg = SRI(reg2, block, reg_num),\ 200 .ack_mask = \ 201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ 202 .ack_value = \ 203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ 204 205 #define hpd_int_entry(reg_num)\ 206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\ 207 IRQ_REG_ENTRY(HPD, reg_num,\ 208 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\ 209 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\ 210 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 211 .funcs = &hpd_irq_info_funcs\ 212 } 213 214 #define hpd_rx_int_entry(reg_num)\ 215 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\ 216 IRQ_REG_ENTRY(HPD, reg_num,\ 217 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\ 218 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\ 219 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\ 220 .funcs = &hpd_rx_irq_info_funcs\ 221 } 222 #define pflip_int_entry(reg_num)\ 223 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\ 224 IRQ_REG_ENTRY(HUBPREQ, reg_num,\ 225 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\ 226 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\ 227 .funcs = &pflip_irq_info_funcs\ 228 } 229 230 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic 231 * of DCE's DC_IRQ_SOURCE_VUPDATEx. 232 */ 233 #define vupdate_no_lock_int_entry(reg_num)\ 234 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\ 235 IRQ_REG_ENTRY(OTG, reg_num,\ 236 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\ 237 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\ 238 .funcs = &vupdate_no_lock_irq_info_funcs\ 239 } 240 241 #define vblank_int_entry(reg_num)\ 242 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\ 243 IRQ_REG_ENTRY(OTG, reg_num,\ 244 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\ 245 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\ 246 .funcs = &vblank_irq_info_funcs\ 247 } 248 249 #define dummy_irq_entry() \ 250 {\ 251 .funcs = &dummy_irq_info_funcs\ 252 } 253 254 #define i2c_int_entry(reg_num) \ 255 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry() 256 257 #define dp_sink_int_entry(reg_num) \ 258 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry() 259 260 #define gpio_pad_int_entry(reg_num) \ 261 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry() 262 263 #define dc_underflow_int_entry(reg_num) \ 264 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry() 265 266 static const struct irq_source_info_funcs dummy_irq_info_funcs = { 267 .set = dal_irq_service_dummy_set, 268 .ack = dal_irq_service_dummy_ack 269 }; 270 271 static const struct irq_source_info 272 irq_source_info_dcn10[DAL_IRQ_SOURCES_NUMBER] = { 273 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(), 274 hpd_int_entry(0), 275 hpd_int_entry(1), 276 hpd_int_entry(2), 277 hpd_int_entry(3), 278 hpd_int_entry(4), 279 hpd_int_entry(5), 280 hpd_rx_int_entry(0), 281 hpd_rx_int_entry(1), 282 hpd_rx_int_entry(2), 283 hpd_rx_int_entry(3), 284 hpd_rx_int_entry(4), 285 hpd_rx_int_entry(5), 286 i2c_int_entry(1), 287 i2c_int_entry(2), 288 i2c_int_entry(3), 289 i2c_int_entry(4), 290 i2c_int_entry(5), 291 i2c_int_entry(6), 292 dp_sink_int_entry(1), 293 dp_sink_int_entry(2), 294 dp_sink_int_entry(3), 295 dp_sink_int_entry(4), 296 dp_sink_int_entry(5), 297 dp_sink_int_entry(6), 298 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(), 299 pflip_int_entry(0), 300 pflip_int_entry(1), 301 pflip_int_entry(2), 302 pflip_int_entry(3), 303 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(), 304 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(), 305 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(), 306 gpio_pad_int_entry(0), 307 gpio_pad_int_entry(1), 308 gpio_pad_int_entry(2), 309 gpio_pad_int_entry(3), 310 gpio_pad_int_entry(4), 311 gpio_pad_int_entry(5), 312 gpio_pad_int_entry(6), 313 gpio_pad_int_entry(7), 314 gpio_pad_int_entry(8), 315 gpio_pad_int_entry(9), 316 gpio_pad_int_entry(10), 317 gpio_pad_int_entry(11), 318 gpio_pad_int_entry(12), 319 gpio_pad_int_entry(13), 320 gpio_pad_int_entry(14), 321 gpio_pad_int_entry(15), 322 gpio_pad_int_entry(16), 323 gpio_pad_int_entry(17), 324 gpio_pad_int_entry(18), 325 gpio_pad_int_entry(19), 326 gpio_pad_int_entry(20), 327 gpio_pad_int_entry(21), 328 gpio_pad_int_entry(22), 329 gpio_pad_int_entry(23), 330 gpio_pad_int_entry(24), 331 gpio_pad_int_entry(25), 332 gpio_pad_int_entry(26), 333 gpio_pad_int_entry(27), 334 gpio_pad_int_entry(28), 335 gpio_pad_int_entry(29), 336 gpio_pad_int_entry(30), 337 dc_underflow_int_entry(1), 338 dc_underflow_int_entry(2), 339 dc_underflow_int_entry(3), 340 dc_underflow_int_entry(4), 341 dc_underflow_int_entry(5), 342 dc_underflow_int_entry(6), 343 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(), 344 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(), 345 vupdate_no_lock_int_entry(0), 346 vupdate_no_lock_int_entry(1), 347 vupdate_no_lock_int_entry(2), 348 vupdate_no_lock_int_entry(3), 349 vupdate_no_lock_int_entry(4), 350 vupdate_no_lock_int_entry(5), 351 vblank_int_entry(0), 352 vblank_int_entry(1), 353 vblank_int_entry(2), 354 vblank_int_entry(3), 355 vblank_int_entry(4), 356 vblank_int_entry(5), 357 }; 358 359 static const struct irq_service_funcs irq_service_funcs_dcn10 = { 360 .to_dal_irq_source = to_dal_irq_source_dcn10 361 }; 362 363 static void dcn10_irq_construct( 364 struct irq_service *irq_service, 365 struct irq_service_init_data *init_data) 366 { 367 dal_irq_service_construct(irq_service, init_data); 368 369 irq_service->info = irq_source_info_dcn10; 370 irq_service->funcs = &irq_service_funcs_dcn10; 371 } 372 373 struct irq_service *dal_irq_service_dcn10_create( 374 struct irq_service_init_data *init_data) 375 { 376 struct irq_service *irq_service = kzalloc(sizeof(*irq_service), 377 GFP_KERNEL); 378 379 if (!irq_service) 380 return NULL; 381 382 dcn10_irq_construct(irq_service, init_data); 383 return irq_service; 384 } 385
Indexes created Mon Sep 22 21:09:42 GMT 2025