1 /* $NetBSD: intel_guc_fwif.h,v 1.2 2021/12/18 23:45:31 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: MIT */ 4 /* 5 * Copyright 2014-2019 Intel Corporation 6 */ 7 8 #ifndef _INTEL_GUC_FWIF_H 9 #define _INTEL_GUC_FWIF_H 10 11 #include <linux/bits.h> 12 #include <linux/compiler.h> 13 #include <linux/types.h> 14 15 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 16 #define GUC_CLIENT_PRIORITY_HIGH 1 17 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 18 #define GUC_CLIENT_PRIORITY_NORMAL 3 19 #define GUC_CLIENT_PRIORITY_NUM 4 20 21 #define GUC_MAX_STAGE_DESCRIPTORS 1024 22 #define GUC_INVALID_STAGE_ID GUC_MAX_STAGE_DESCRIPTORS 23 24 #define GUC_RENDER_ENGINE 0 25 #define GUC_VIDEO_ENGINE 1 26 #define GUC_BLITTER_ENGINE 2 27 #define GUC_VIDEOENHANCE_ENGINE 3 28 #define GUC_VIDEO_ENGINE2 4 29 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1) 30 31 #define GUC_MAX_ENGINE_CLASSES 5 32 #define GUC_MAX_INSTANCES_PER_CLASS 16 33 34 #define GUC_DOORBELL_INVALID 256 35 36 #define GUC_WQ_SIZE (PAGE_SIZE * 2) 37 38 /* Work queue item header definitions */ 39 #define WQ_STATUS_ACTIVE 1 40 #define WQ_STATUS_SUSPENDED 2 41 #define WQ_STATUS_CMD_ERROR 3 42 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 43 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 44 #define WQ_TYPE_SHIFT 0 45 #define WQ_TYPE_BATCH_BUF (0x1 << WQ_TYPE_SHIFT) 46 #define WQ_TYPE_PSEUDO (0x2 << WQ_TYPE_SHIFT) 47 #define WQ_TYPE_INORDER (0x3 << WQ_TYPE_SHIFT) 48 #define WQ_TYPE_NOOP (0x4 << WQ_TYPE_SHIFT) 49 #define WQ_TARGET_SHIFT 10 50 #define WQ_LEN_SHIFT 16 51 #define WQ_NO_WCFLUSH_WAIT (1 << 27) 52 #define WQ_PRESENT_WORKLOAD (1 << 28) 53 54 #define WQ_RING_TAIL_SHIFT 20 55 #define WQ_RING_TAIL_MAX 0x7FF /* 2^11 QWords */ 56 #define WQ_RING_TAIL_MASK (WQ_RING_TAIL_MAX << WQ_RING_TAIL_SHIFT) 57 58 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 59 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 60 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 61 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 62 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 63 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 64 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 65 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 66 67 /* New GuC control data */ 68 #define GUC_CTL_CTXINFO 0 69 #define GUC_CTL_CTXNUM_IN16_SHIFT 0 70 #define GUC_CTL_BASE_ADDR_SHIFT 12 71 72 #define GUC_CTL_LOG_PARAMS 1 73 #define GUC_LOG_VALID (1 << 0) 74 #define GUC_LOG_NOTIFY_ON_HALF_FULL (1 << 1) 75 #define GUC_LOG_ALLOC_IN_MEGABYTE (1 << 3) 76 #define GUC_LOG_CRASH_SHIFT 4 77 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) 78 #define GUC_LOG_DPC_SHIFT 6 79 #define GUC_LOG_DPC_MASK (0x7 << GUC_LOG_DPC_SHIFT) 80 #define GUC_LOG_ISR_SHIFT 9 81 #define GUC_LOG_ISR_MASK (0x7 << GUC_LOG_ISR_SHIFT) 82 #define GUC_LOG_BUF_ADDR_SHIFT 12 83 84 #define GUC_CTL_WA 2 85 #define GUC_CTL_FEATURE 3 86 #define GUC_CTL_DISABLE_SCHEDULER (1 << 14) 87 88 #define GUC_CTL_DEBUG 4 89 #define GUC_LOG_VERBOSITY_SHIFT 0 90 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 91 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 92 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 93 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 94 /* Verbosity range-check limits, without the shift */ 95 #define GUC_LOG_VERBOSITY_MIN 0 96 #define GUC_LOG_VERBOSITY_MAX 3 97 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 98 #define GUC_LOG_DESTINATION_MASK (3 << 4) 99 #define GUC_LOG_DISABLED (1 << 6) 100 #define GUC_PROFILE_ENABLED (1 << 7) 101 102 #define GUC_CTL_ADS 5 103 #define GUC_ADS_ADDR_SHIFT 1 104 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) 105 106 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 107 108 /* Work item for submitting workloads into work queue of GuC. */ 109 struct guc_wq_item { 110 u32 header; 111 u32 context_desc; 112 u32 submit_element_info; 113 u32 fence_id; 114 } __packed; 115 116 struct guc_process_desc { 117 u32 stage_id; 118 u64 db_base_addr; 119 u32 head; 120 u32 tail; 121 u32 error_offset; 122 u64 wq_base_addr; 123 u32 wq_size_bytes; 124 u32 wq_status; 125 u32 engine_presence; 126 u32 priority; 127 u32 reserved[30]; 128 } __packed; 129 130 /* engine id and context id is packed into guc_execlist_context.context_id*/ 131 #define GUC_ELC_CTXID_OFFSET 0 132 #define GUC_ELC_ENGINE_OFFSET 29 133 134 /* The execlist context including software and HW information */ 135 struct guc_execlist_context { 136 u32 context_desc; 137 u32 context_id; 138 u32 ring_status; 139 u32 ring_lrca; 140 u32 ring_begin; 141 u32 ring_end; 142 u32 ring_next_free_location; 143 u32 ring_current_tail_pointer_value; 144 u8 engine_state_submit_value; 145 u8 engine_state_wait_value; 146 u16 pagefault_count; 147 u16 engine_submit_queue_count; 148 } __packed; 149 150 /* 151 * This structure describes a stage set arranged for a particular communication 152 * between uKernel (GuC) and Driver (KMD). Technically, this is known as a 153 * "GuC Context descriptor" in the specs, but we use the term "stage descriptor" 154 * to avoid confusion with all the other things already named "context" in the 155 * driver. A static pool of these descriptors are stored inside a GEM object 156 * (stage_desc_pool) which is held for the entire lifetime of our interaction 157 * with the GuC, being allocated before the GuC is loaded with its firmware. 158 */ 159 struct guc_stage_desc { 160 u32 sched_common_area; 161 u32 stage_id; 162 u32 pas_id; 163 u8 engines_used; 164 u64 db_trigger_cpu; 165 u32 db_trigger_uk; 166 u64 db_trigger_phy; 167 u16 db_id; 168 169 struct guc_execlist_context lrc[GUC_MAX_ENGINES_NUM]; 170 171 u8 attribute; 172 173 u32 priority; 174 175 u32 wq_sampled_tail_offset; 176 u32 wq_total_submit_enqueues; 177 178 u32 process_desc; 179 u32 wq_addr; 180 u32 wq_size; 181 182 u32 engine_presence; 183 184 u8 engine_suspended; 185 186 u8 reserved0[3]; 187 u64 reserved1[1]; 188 189 u64 desc_private; 190 } __packed; 191 192 /** 193 * DOC: CTB based communication 194 * 195 * The CTB (command transport buffer) communication between Host and GuC 196 * is based on u32 data stream written to the shared buffer. One buffer can 197 * be used to transmit data only in one direction (one-directional channel). 198 * 199 * Current status of the each buffer is stored in the buffer descriptor. 200 * Buffer descriptor holds tail and head fields that represents active data 201 * stream. The tail field is updated by the data producer (sender), and head 202 * field is updated by the data consumer (receiver):: 203 * 204 * +------------+ 205 * | DESCRIPTOR | +=================+============+========+ 206 * +============+ | | MESSAGE(s) | | 207 * | address |--------->+=================+============+========+ 208 * +------------+ 209 * | head | ^-----head--------^ 210 * +------------+ 211 * | tail | ^---------tail-----------------^ 212 * +------------+ 213 * | size | ^---------------size--------------------^ 214 * +------------+ 215 * 216 * Each message in data stream starts with the single u32 treated as a header, 217 * followed by optional set of u32 data that makes message specific payload:: 218 * 219 * +------------+---------+---------+---------+ 220 * | MESSAGE | 221 * +------------+---------+---------+---------+ 222 * | msg[0] | [1] | ... | [n-1] | 223 * +------------+---------+---------+---------+ 224 * | MESSAGE | MESSAGE PAYLOAD | 225 * + HEADER +---------+---------+---------+ 226 * | | 0 | ... | n | 227 * +======+=====+=========+=========+=========+ 228 * | 31:16| code| | | | 229 * +------+-----+ | | | 230 * | 15:5|flags| | | | 231 * +------+-----+ | | | 232 * | 4:0| len| | | | 233 * +------+-----+---------+---------+---------+ 234 * 235 * ^-------------len-------------^ 236 * 237 * The message header consists of: 238 * 239 * - **len**, indicates length of the message payload (in u32) 240 * - **code**, indicates message code 241 * - **flags**, holds various bits to control message handling 242 */ 243 244 /* 245 * Describes single command transport buffer. 246 * Used by both guc-master and clients. 247 */ 248 struct guc_ct_buffer_desc { 249 u32 addr; /* gfx address */ 250 u64 host_private; /* host private data */ 251 u32 size; /* size in bytes */ 252 u32 head; /* offset updated by GuC*/ 253 u32 tail; /* offset updated by owner */ 254 u32 is_in_error; /* error indicator */ 255 u32 fence; /* fence updated by GuC */ 256 u32 status; /* status updated by GuC */ 257 u32 owner; /* id of the channel owner */ 258 u32 owner_sub_id; /* owner-defined field for extra tracking */ 259 u32 reserved[5]; 260 } __packed; 261 262 /* Type of command transport buffer */ 263 #define INTEL_GUC_CT_BUFFER_TYPE_SEND 0x0u 264 #define INTEL_GUC_CT_BUFFER_TYPE_RECV 0x1u 265 266 /* 267 * Definition of the command transport message header (DW0) 268 * 269 * bit[4..0] message len (in dwords) 270 * bit[7..5] reserved 271 * bit[8] response (G2H only) 272 * bit[8] write fence to desc (H2G only) 273 * bit[9] write status to H2G buff (H2G only) 274 * bit[10] send status back via G2H (H2G only) 275 * bit[15..11] reserved 276 * bit[31..16] action code 277 */ 278 #define GUC_CT_MSG_LEN_SHIFT 0 279 #define GUC_CT_MSG_LEN_MASK 0x1F 280 #define GUC_CT_MSG_IS_RESPONSE (1 << 8) 281 #define GUC_CT_MSG_WRITE_FENCE_TO_DESC (1 << 8) 282 #define GUC_CT_MSG_WRITE_STATUS_TO_BUFF (1 << 9) 283 #define GUC_CT_MSG_SEND_STATUS (1 << 10) 284 #define GUC_CT_MSG_ACTION_SHIFT 16 285 #define GUC_CT_MSG_ACTION_MASK 0xFFFF 286 287 #define GUC_FORCEWAKE_RENDER (1 << 0) 288 #define GUC_FORCEWAKE_MEDIA (1 << 1) 289 290 #define GUC_POWER_UNSPECIFIED 0 291 #define GUC_POWER_D0 1 292 #define GUC_POWER_D1 2 293 #define GUC_POWER_D2 3 294 #define GUC_POWER_D3 4 295 296 /* Scheduling policy settings */ 297 298 /* Reset engine upon preempt failure */ 299 #define POLICY_RESET_ENGINE (1<<0) 300 /* Preempt to idle on quantum expiry */ 301 #define POLICY_PREEMPT_TO_IDLE (1<<1) 302 303 #define POLICY_MAX_NUM_WI 15 304 #define POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 305 #define POLICY_DEFAULT_EXECUTION_QUANTUM_US 1000000 306 #define POLICY_DEFAULT_PREEMPTION_TIME_US 500000 307 #define POLICY_DEFAULT_FAULT_TIME_US 250000 308 309 struct guc_policy { 310 /* Time for one workload to execute. (in micro seconds) */ 311 u32 execution_quantum; 312 /* Time to wait for a preemption request to completed before issuing a 313 * reset. (in micro seconds). */ 314 u32 preemption_time; 315 /* How much time to allow to run after the first fault is observed. 316 * Then preempt afterwards. (in micro seconds) */ 317 u32 fault_time; 318 u32 policy_flags; 319 u32 reserved[8]; 320 } __packed; 321 322 struct guc_policies { 323 struct guc_policy policy[GUC_CLIENT_PRIORITY_NUM][GUC_MAX_ENGINE_CLASSES]; 324 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; 325 /* In micro seconds. How much time to allow before DPC processing is 326 * called back via interrupt (to prevent DPC queue drain starving). 327 * Typically 1000s of micro seconds (example only, not granularity). */ 328 u32 dpc_promote_time; 329 330 /* Must be set to take these new values. */ 331 u32 is_valid; 332 333 /* Max number of WIs to process per call. A large value may keep CS 334 * idle. */ 335 u32 max_num_work_items; 336 337 u32 reserved[4]; 338 } __packed; 339 340 /* GuC MMIO reg state struct */ 341 342 343 #define GUC_REGSET_MAX_REGISTERS 64 344 #define GUC_S3_SAVE_SPACE_PAGES 10 345 346 struct guc_mmio_reg { 347 u32 offset; 348 u32 value; 349 u32 flags; 350 #define GUC_REGSET_MASKED (1 << 0) 351 } __packed; 352 353 struct guc_mmio_regset { 354 struct guc_mmio_reg registers[GUC_REGSET_MAX_REGISTERS]; 355 u32 values_valid; 356 u32 number_of_registers; 357 } __packed; 358 359 /* GuC register sets */ 360 struct guc_mmio_reg_state { 361 struct guc_mmio_regset engine_reg[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 362 u32 reserved[98]; 363 } __packed; 364 365 /* HW info */ 366 struct guc_gt_system_info { 367 u32 slice_enabled; 368 u32 rcs_enabled; 369 u32 reserved0; 370 u32 bcs_enabled; 371 u32 vdbox_enable_mask; 372 u32 vdbox_sfc_support_mask; 373 u32 vebox_enable_mask; 374 u32 reserved[9]; 375 } __packed; 376 377 /* Clients info */ 378 struct guc_ct_pool_entry { 379 struct guc_ct_buffer_desc desc; 380 u32 reserved[7]; 381 } __packed; 382 383 #define GUC_CT_POOL_SIZE 2 384 385 struct guc_clients_info { 386 u32 clients_num; 387 u32 reserved0[13]; 388 u32 ct_pool_addr; 389 u32 ct_pool_count; 390 u32 reserved[4]; 391 } __packed; 392 393 /* GuC Additional Data Struct */ 394 struct guc_ads { 395 u32 reg_state_addr; 396 u32 reg_state_buffer; 397 u32 scheduler_policies; 398 u32 gt_system_info; 399 u32 clients_info; 400 u32 control_data; 401 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; 402 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; 403 u32 reserved[16]; 404 } __packed; 405 406 /* GuC logging structures */ 407 408 enum guc_log_buffer_type { 409 GUC_ISR_LOG_BUFFER, 410 GUC_DPC_LOG_BUFFER, 411 GUC_CRASH_DUMP_LOG_BUFFER, 412 GUC_MAX_LOG_BUFFER 413 }; 414 415 /** 416 * struct guc_log_buffer_state - GuC log buffer state 417 * 418 * Below state structure is used for coordination of retrieval of GuC firmware 419 * logs. Separate state is maintained for each log buffer type. 420 * read_ptr points to the location where i915 read last in log buffer and 421 * is read only for GuC firmware. write_ptr is incremented by GuC with number 422 * of bytes written for each log entry and is read only for i915. 423 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 424 * GuC firmware expects that while it is writing to 2nd half of the buffer, 425 * first half would get consumed by Host and then get a flush completed 426 * acknowledgment from Host, so that it does not end up doing any overwrite 427 * causing loss of logs. So when buffer gets half filled & i915 has requested 428 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 429 * to the value of write_ptr and raise the interrupt. 430 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 431 * field and also update read_ptr with the value of sample_write_ptr, before 432 * sending an acknowledgment to GuC. marker & version fields are for internal 433 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 434 * time GuC detects the log buffer overflow. 435 */ 436 struct guc_log_buffer_state { 437 u32 marker[2]; 438 u32 read_ptr; 439 u32 write_ptr; 440 u32 size; 441 u32 sampled_write_ptr; 442 union { 443 struct { 444 u32 flush_to_file:1; 445 u32 buffer_full_cnt:4; 446 u32 reserved:27; 447 }; 448 u32 flags; 449 }; 450 u32 version; 451 } __packed; 452 453 struct guc_ctx_report { 454 u32 report_return_status; 455 u32 reserved1[64]; 456 u32 affected_count; 457 u32 reserved2[2]; 458 } __packed; 459 460 /* GuC Shared Context Data Struct */ 461 struct guc_shared_ctx_data { 462 u32 addr_of_last_preempted_data_low; 463 u32 addr_of_last_preempted_data_high; 464 u32 addr_of_last_preempted_data_high_tmp; 465 u32 padding; 466 u32 is_mapped_to_proxy; 467 u32 proxy_ctx_id; 468 u32 engine_reset_ctx_id; 469 u32 media_reset_count; 470 u32 reserved1[8]; 471 u32 uk_last_ctx_switch_reason; 472 u32 was_reset; 473 u32 lrca_gpu_addr; 474 u64 execlist_ctx; 475 u32 reserved2[66]; 476 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM]; 477 } __packed; 478 479 /** 480 * DOC: MMIO based communication 481 * 482 * The MMIO based communication between Host and GuC uses software scratch 483 * registers, where first register holds data treated as message header, 484 * and other registers are used to hold message payload. 485 * 486 * For Gen9+, GuC uses software scratch registers 0xC180-0xC1B8, 487 * but no H2G command takes more than 8 parameters and the GuC FW 488 * itself uses an 8-element array to store the H2G message. 489 * 490 * +-----------+---------+---------+---------+ 491 * | MMIO[0] | MMIO[1] | ... | MMIO[n] | 492 * +-----------+---------+---------+---------+ 493 * | header | optional payload | 494 * +======+====+=========+=========+=========+ 495 * | 31:28|type| | | | 496 * +------+----+ | | | 497 * | 27:16|data| | | | 498 * +------+----+ | | | 499 * | 15:0|code| | | | 500 * +------+----+---------+---------+---------+ 501 * 502 * The message header consists of: 503 * 504 * - **type**, indicates message type 505 * - **code**, indicates message code, is specific for **type** 506 * - **data**, indicates message data, optional, depends on **code** 507 * 508 * The following message **types** are supported: 509 * 510 * - **REQUEST**, indicates Host-to-GuC request, requested GuC action code 511 * must be priovided in **code** field. Optional action specific parameters 512 * can be provided in remaining payload registers or **data** field. 513 * 514 * - **RESPONSE**, indicates GuC-to-Host response from earlier GuC request, 515 * action response status will be provided in **code** field. Optional 516 * response data can be returned in remaining payload registers or **data** 517 * field. 518 */ 519 520 #define GUC_MAX_MMIO_MSG_LEN 8 521 522 #define INTEL_GUC_MSG_TYPE_SHIFT 28 523 #define INTEL_GUC_MSG_TYPE_MASK (0xF << INTEL_GUC_MSG_TYPE_SHIFT) 524 #define INTEL_GUC_MSG_DATA_SHIFT 16 525 #define INTEL_GUC_MSG_DATA_MASK (0xFFF << INTEL_GUC_MSG_DATA_SHIFT) 526 #define INTEL_GUC_MSG_CODE_SHIFT 0 527 #define INTEL_GUC_MSG_CODE_MASK (0xFFFF << INTEL_GUC_MSG_CODE_SHIFT) 528 529 #define __INTEL_GUC_MSG_GET(T, m) \ 530 (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT) 531 #define INTEL_GUC_MSG_TO_TYPE(m) __INTEL_GUC_MSG_GET(TYPE, m) 532 #define INTEL_GUC_MSG_TO_DATA(m) __INTEL_GUC_MSG_GET(DATA, m) 533 #define INTEL_GUC_MSG_TO_CODE(m) __INTEL_GUC_MSG_GET(CODE, m) 534 535 enum intel_guc_msg_type { 536 INTEL_GUC_MSG_TYPE_REQUEST = 0x0, 537 INTEL_GUC_MSG_TYPE_RESPONSE = 0xF, 538 }; 539 540 #define __INTEL_GUC_MSG_TYPE_IS(T, m) \ 541 (INTEL_GUC_MSG_TO_TYPE(m) == INTEL_GUC_MSG_TYPE_ ## T) 542 #define INTEL_GUC_MSG_IS_REQUEST(m) __INTEL_GUC_MSG_TYPE_IS(REQUEST, m) 543 #define INTEL_GUC_MSG_IS_RESPONSE(m) __INTEL_GUC_MSG_TYPE_IS(RESPONSE, m) 544 545 enum intel_guc_action { 546 INTEL_GUC_ACTION_DEFAULT = 0x0, 547 INTEL_GUC_ACTION_REQUEST_PREEMPTION = 0x2, 548 INTEL_GUC_ACTION_REQUEST_ENGINE_RESET = 0x3, 549 INTEL_GUC_ACTION_ALLOCATE_DOORBELL = 0x10, 550 INTEL_GUC_ACTION_DEALLOCATE_DOORBELL = 0x20, 551 INTEL_GUC_ACTION_LOG_BUFFER_FILE_FLUSH_COMPLETE = 0x30, 552 INTEL_GUC_ACTION_UK_LOG_ENABLE_LOGGING = 0x40, 553 INTEL_GUC_ACTION_FORCE_LOG_BUFFER_FLUSH = 0x302, 554 INTEL_GUC_ACTION_ENTER_S_STATE = 0x501, 555 INTEL_GUC_ACTION_EXIT_S_STATE = 0x502, 556 INTEL_GUC_ACTION_SLPC_REQUEST = 0x3003, 557 INTEL_GUC_ACTION_SAMPLE_FORCEWAKE = 0x3005, 558 INTEL_GUC_ACTION_AUTHENTICATE_HUC = 0x4000, 559 INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER = 0x4505, 560 INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER = 0x4506, 561 INTEL_GUC_ACTION_LIMIT 562 }; 563 564 enum intel_guc_preempt_options { 565 INTEL_GUC_PREEMPT_OPTION_DROP_WORK_Q = 0x4, 566 INTEL_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8, 567 }; 568 569 enum intel_guc_report_status { 570 INTEL_GUC_REPORT_STATUS_UNKNOWN = 0x0, 571 INTEL_GUC_REPORT_STATUS_ACKED = 0x1, 572 INTEL_GUC_REPORT_STATUS_ERROR = 0x2, 573 INTEL_GUC_REPORT_STATUS_COMPLETE = 0x4, 574 }; 575 576 enum intel_guc_sleep_state_status { 577 INTEL_GUC_SLEEP_STATE_SUCCESS = 0x1, 578 INTEL_GUC_SLEEP_STATE_PREEMPT_TO_IDLE_FAILED = 0x2, 579 INTEL_GUC_SLEEP_STATE_ENGINE_RESET_FAILED = 0x3 580 #define INTEL_GUC_SLEEP_STATE_INVALID_MASK 0x80000000 581 }; 582 583 #define GUC_LOG_CONTROL_LOGGING_ENABLED (1 << 0) 584 #define GUC_LOG_CONTROL_VERBOSITY_SHIFT 4 585 #define GUC_LOG_CONTROL_VERBOSITY_MASK (0xF << GUC_LOG_CONTROL_VERBOSITY_SHIFT) 586 #define GUC_LOG_CONTROL_DEFAULT_LOGGING (1 << 8) 587 588 enum intel_guc_response_status { 589 INTEL_GUC_RESPONSE_STATUS_SUCCESS = 0x0, 590 INTEL_GUC_RESPONSE_STATUS_GENERIC_FAIL = 0xF000, 591 }; 592 593 #define INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(m) \ 594 (typecheck(u32, (m)) && \ 595 ((m) & (INTEL_GUC_MSG_TYPE_MASK | INTEL_GUC_MSG_CODE_MASK)) == \ 596 ((INTEL_GUC_MSG_TYPE_RESPONSE << INTEL_GUC_MSG_TYPE_SHIFT) | \ 597 (INTEL_GUC_RESPONSE_STATUS_SUCCESS << INTEL_GUC_MSG_CODE_SHIFT))) 598 599 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 600 enum intel_guc_recv_message { 601 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 602 INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER = BIT(3) 603 }; 604 605 #endif 606
Indexes created Sat Sep 20 22:09:52 GMT 2025