1 /* $NetBSD: dc_types.h,v 1.2 2021/12/18 23:45:00 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 #ifndef DC_TYPES_H_ 28 #define DC_TYPES_H_ 29 30 /* AND EdidUtility only needs a portion 31 * of this file, including the rest only 32 * causes additional issues. 33 */ 34 #include "os_types.h" 35 #include "fixed31_32.h" 36 #include "irq_types.h" 37 #include "dc_dp_types.h" 38 #include "dc_hw_types.h" 39 #include "dal_types.h" 40 #include "grph_object_defs.h" 41 42 #ifdef CONFIG_DRM_AMD_DC_HDCP 43 #include "dm_cp_psp.h" 44 #endif 45 46 /* forward declarations */ 47 struct dc_plane_state; 48 struct dc_stream_state; 49 struct dc_link; 50 struct dc_sink; 51 struct dal; 52 struct dc_dmub_srv; 53 54 /******************************** 55 * Environment definitions 56 ********************************/ 57 enum dce_environment { 58 DCE_ENV_PRODUCTION_DRV = 0, 59 /* Emulation on FPGA, in "Maximus" System. 60 * This environment enforces that *only* DC registers accessed. 61 * (access to non-DC registers will hang FPGA) */ 62 DCE_ENV_FPGA_MAXIMUS, 63 /* Emulation on real HW or on FPGA. Used by Diagnostics, enforces 64 * requirements of Diagnostics team. */ 65 DCE_ENV_DIAG, 66 /* 67 * Guest VM system, DC HW may exist but is not virtualized and 68 * should not be used. SW support for VDI only. 69 */ 70 DCE_ENV_VIRTUAL_HW 71 }; 72 73 /* Note: use these macro definitions instead of direct comparison! */ 74 #define IS_FPGA_MAXIMUS_DC(dce_environment) \ 75 (dce_environment == DCE_ENV_FPGA_MAXIMUS) 76 77 #define IS_DIAG_DC(dce_environment) \ 78 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG)) 79 80 struct hw_asic_id { 81 uint32_t chip_id; 82 uint32_t chip_family; 83 uint32_t pci_revision_id; 84 uint32_t hw_internal_rev; 85 uint32_t vram_type; 86 uint32_t vram_width; 87 uint32_t feature_flags; 88 uint32_t fake_paths_num; 89 void *atombios_base_address; 90 }; 91 92 struct dc_perf_trace { 93 unsigned long read_count; 94 unsigned long write_count; 95 unsigned long last_entry_read; 96 unsigned long last_entry_write; 97 }; 98 99 struct dc_context { 100 struct dc *dc; 101 102 void *driver_context; /* e.g. amdgpu_device */ 103 struct dc_perf_trace *perf_trace; 104 void *cgs_device; 105 106 enum dce_environment dce_environment; 107 struct hw_asic_id asic_id; 108 109 /* todo: below should probably move to dc. to facilitate removal 110 * of AS we will store these here 111 */ 112 enum dce_version dce_version; 113 struct dc_bios *dc_bios; 114 bool created_bios; 115 struct gpio_service *gpio_service; 116 uint32_t dc_sink_id_count; 117 uint32_t dc_stream_id_count; 118 uint64_t fbc_gpu_addr; 119 struct dc_dmub_srv *dmub_srv; 120 121 #ifdef CONFIG_DRM_AMD_DC_HDCP 122 struct cp_psp cp_psp; 123 #endif 124 }; 125 126 127 #define DC_MAX_EDID_BUFFER_SIZE 1024 128 #define DC_EDID_BLOCK_SIZE 128 129 #define MAX_SURFACE_NUM 4 130 #define NUM_PIXEL_FORMATS 10 131 #define MAX_REPEATER_CNT 8 132 133 #include "dc_ddc_types.h" 134 135 enum tiling_mode { 136 TILING_MODE_INVALID, 137 TILING_MODE_LINEAR, 138 TILING_MODE_TILED, 139 TILING_MODE_COUNT 140 }; 141 142 enum view_3d_format { 143 VIEW_3D_FORMAT_NONE = 0, 144 VIEW_3D_FORMAT_FRAME_SEQUENTIAL, 145 VIEW_3D_FORMAT_SIDE_BY_SIDE, 146 VIEW_3D_FORMAT_TOP_AND_BOTTOM, 147 VIEW_3D_FORMAT_COUNT, 148 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL 149 }; 150 151 enum plane_stereo_format { 152 PLANE_STEREO_FORMAT_NONE = 0, 153 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1, 154 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2, 155 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3, 156 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5, 157 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6, 158 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7 159 }; 160 161 /* TODO: Find way to calculate number of bits 162 * Please increase if pixel_format enum increases 163 * num from PIXEL_FORMAT_INDEX8 to PIXEL_FORMAT_444BPP32 164 */ 165 166 enum dc_edid_connector_type { 167 DC_EDID_CONNECTOR_UNKNOWN = 0, 168 DC_EDID_CONNECTOR_ANALOG = 1, 169 DC_EDID_CONNECTOR_DIGITAL = 10, 170 DC_EDID_CONNECTOR_DVI = 11, 171 DC_EDID_CONNECTOR_HDMIA = 12, 172 DC_EDID_CONNECTOR_MDDI = 14, 173 DC_EDID_CONNECTOR_DISPLAYPORT = 15 174 }; 175 176 enum dc_edid_status { 177 EDID_OK, 178 EDID_BAD_INPUT, 179 EDID_NO_RESPONSE, 180 EDID_BAD_CHECKSUM, 181 EDID_THE_SAME, 182 }; 183 184 enum act_return_status { 185 ACT_SUCCESS, 186 ACT_LINK_LOST, 187 ACT_FAILED 188 }; 189 190 /* audio capability from EDID*/ 191 struct dc_cea_audio_mode { 192 uint8_t format_code; /* ucData[0] [6:3]*/ 193 uint8_t channel_count; /* ucData[0] [2:0]*/ 194 uint8_t sample_rate; /* ucData[1]*/ 195 union { 196 uint8_t sample_size; /* for LPCM*/ 197 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz)*/ 198 uint8_t max_bit_rate; 199 uint8_t audio_codec_vendor_specific; /* for Audio Formats 9-15*/ 200 }; 201 }; 202 203 struct dc_edid { 204 uint32_t length; 205 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE]; 206 }; 207 208 /* When speaker location data block is not available, DEFAULT_SPEAKER_LOCATION 209 * is used. In this case we assume speaker location are: front left, front 210 * right and front center. */ 211 #define DEFAULT_SPEAKER_LOCATION 5 212 213 #define DC_MAX_AUDIO_DESC_COUNT 16 214 215 #define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20 216 217 union display_content_support { 218 unsigned int raw; 219 struct { 220 unsigned int valid_content_type :1; 221 unsigned int game_content :1; 222 unsigned int cinema_content :1; 223 unsigned int photo_content :1; 224 unsigned int graphics_content :1; 225 unsigned int reserved :27; 226 } bits; 227 }; 228 229 struct dc_panel_patch { 230 unsigned int dppowerup_delay; 231 unsigned int extra_t12_ms; 232 unsigned int extra_delay_backlight_off; 233 unsigned int extra_t7_ms; 234 unsigned int manage_secondary_link; 235 }; 236 237 struct dc_edid_caps { 238 /* sink identification */ 239 uint16_t manufacturer_id; 240 uint16_t product_id; 241 uint32_t serial_number; 242 uint8_t manufacture_week; 243 uint8_t manufacture_year; 244 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 245 246 /* audio caps */ 247 uint8_t speaker_flags; 248 uint32_t audio_mode_count; 249 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT]; 250 uint32_t audio_latency; 251 uint32_t video_latency; 252 253 union display_content_support content_support; 254 255 uint8_t qs_bit; 256 uint8_t qy_bit; 257 258 /*HDMI 2.0 caps*/ 259 bool lte_340mcsc_scramble; 260 261 bool edid_hdmi; 262 bool hdr_supported; 263 264 struct dc_panel_patch panel_patch; 265 }; 266 267 struct view { 268 uint32_t width; 269 uint32_t height; 270 }; 271 272 struct dc_mode_flags { 273 /* note: part of refresh rate flag*/ 274 uint32_t INTERLACE :1; 275 /* native display timing*/ 276 uint32_t NATIVE :1; 277 /* preferred is the recommended mode, one per display */ 278 uint32_t PREFERRED :1; 279 /* true if this mode should use reduced blanking timings 280 *_not_ related to the Reduced Blanking adjustment*/ 281 uint32_t REDUCED_BLANKING :1; 282 /* note: part of refreshrate flag*/ 283 uint32_t VIDEO_OPTIMIZED_RATE :1; 284 /* should be reported to upper layers as mode_flags*/ 285 uint32_t PACKED_PIXEL_FORMAT :1; 286 /*< preferred view*/ 287 uint32_t PREFERRED_VIEW :1; 288 /* this timing should be used only in tiled mode*/ 289 uint32_t TILED_MODE :1; 290 uint32_t DSE_MODE :1; 291 /* Refresh rate divider when Miracast sink is using a 292 different rate than the output display device 293 Must be zero for wired displays and non-zero for 294 Miracast displays*/ 295 uint32_t MIRACAST_REFRESH_DIVIDER; 296 }; 297 298 299 enum dc_timing_source { 300 TIMING_SOURCE_UNDEFINED, 301 302 /* explicitly specifed by user, most important*/ 303 TIMING_SOURCE_USER_FORCED, 304 TIMING_SOURCE_USER_OVERRIDE, 305 TIMING_SOURCE_CUSTOM, 306 TIMING_SOURCE_EXPLICIT, 307 308 /* explicitly specified by the display device, more important*/ 309 TIMING_SOURCE_EDID_CEA_SVD_3D, 310 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED, 311 TIMING_SOURCE_EDID_CEA_SVD_420, 312 TIMING_SOURCE_EDID_DETAILED, 313 TIMING_SOURCE_EDID_ESTABLISHED, 314 TIMING_SOURCE_EDID_STANDARD, 315 TIMING_SOURCE_EDID_CEA_SVD, 316 TIMING_SOURCE_EDID_CVT_3BYTE, 317 TIMING_SOURCE_EDID_4BYTE, 318 TIMING_SOURCE_VBIOS, 319 TIMING_SOURCE_CV, 320 TIMING_SOURCE_TV, 321 TIMING_SOURCE_HDMI_VIC, 322 323 /* implicitly specified by display device, still safe but less important*/ 324 TIMING_SOURCE_DEFAULT, 325 326 /* only used for custom base modes */ 327 TIMING_SOURCE_CUSTOM_BASE, 328 329 /* these timing might not work, least important*/ 330 TIMING_SOURCE_RANGELIMIT, 331 TIMING_SOURCE_OS_FORCED, 332 TIMING_SOURCE_IMPLICIT, 333 334 /* only used by default mode list*/ 335 TIMING_SOURCE_BASICMODE, 336 337 TIMING_SOURCE_COUNT 338 }; 339 340 341 struct stereo_3d_features { 342 bool supported ; 343 bool allTimings ; 344 bool cloneMode ; 345 bool scaling ; 346 bool singleFrameSWPacked; 347 }; 348 349 enum dc_timing_support_method { 350 TIMING_SUPPORT_METHOD_UNDEFINED, 351 TIMING_SUPPORT_METHOD_EXPLICIT, 352 TIMING_SUPPORT_METHOD_IMPLICIT, 353 TIMING_SUPPORT_METHOD_NATIVE 354 }; 355 356 struct dc_mode_info { 357 uint32_t pixel_width; 358 uint32_t pixel_height; 359 uint32_t field_rate; 360 /* Vertical refresh rate for progressive modes. 361 * Field rate for interlaced modes.*/ 362 363 enum dc_timing_standard timing_standard; 364 enum dc_timing_source timing_source; 365 struct dc_mode_flags flags; 366 }; 367 368 enum dc_power_state { 369 DC_POWER_STATE_ON = 1, 370 DC_POWER_STATE_STANDBY, 371 DC_POWER_STATE_SUSPEND, 372 DC_POWER_STATE_OFF 373 }; 374 375 /* DC PowerStates */ 376 enum dc_video_power_state { 377 DC_VIDEO_POWER_UNSPECIFIED = 0, 378 DC_VIDEO_POWER_ON = 1, 379 DC_VIDEO_POWER_STANDBY, 380 DC_VIDEO_POWER_SUSPEND, 381 DC_VIDEO_POWER_OFF, 382 DC_VIDEO_POWER_HIBERNATE, 383 DC_VIDEO_POWER_SHUTDOWN, 384 DC_VIDEO_POWER_ULPS, /* BACO or Ultra-Light-Power-State */ 385 DC_VIDEO_POWER_AFTER_RESET, 386 DC_VIDEO_POWER_MAXIMUM 387 }; 388 389 enum dc_acpi_cm_power_state { 390 DC_ACPI_CM_POWER_STATE_D0 = 1, 391 DC_ACPI_CM_POWER_STATE_D1 = 2, 392 DC_ACPI_CM_POWER_STATE_D2 = 4, 393 DC_ACPI_CM_POWER_STATE_D3 = 8 394 }; 395 396 enum dc_connection_type { 397 dc_connection_none, 398 dc_connection_single, 399 dc_connection_mst_branch, 400 dc_connection_active_dongle 401 }; 402 403 struct dc_csc_adjustments { 404 struct fixed31_32 contrast; 405 struct fixed31_32 saturation; 406 struct fixed31_32 brightness; 407 struct fixed31_32 hue; 408 }; 409 410 enum dpcd_downstream_port_max_bpc { 411 DOWN_STREAM_MAX_8BPC = 0, 412 DOWN_STREAM_MAX_10BPC, 413 DOWN_STREAM_MAX_12BPC, 414 DOWN_STREAM_MAX_16BPC 415 }; 416 417 418 enum link_training_offset { 419 DPRX = 0, 420 LTTPR_PHY_REPEATER1 = 1, 421 LTTPR_PHY_REPEATER2 = 2, 422 LTTPR_PHY_REPEATER3 = 3, 423 LTTPR_PHY_REPEATER4 = 4, 424 LTTPR_PHY_REPEATER5 = 5, 425 LTTPR_PHY_REPEATER6 = 6, 426 LTTPR_PHY_REPEATER7 = 7, 427 LTTPR_PHY_REPEATER8 = 8 428 }; 429 430 struct dc_lttpr_caps { 431 union dpcd_rev revision; 432 uint8_t mode; 433 uint8_t max_lane_count; 434 uint8_t max_link_rate; 435 uint8_t phy_repeater_cnt; 436 uint8_t max_ext_timeout; 437 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1]; 438 }; 439 440 struct dc_dongle_caps { 441 /* dongle type (DP converter, CV smart dongle) */ 442 enum display_dongle_type dongle_type; 443 bool extendedCapValid; 444 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 445 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 446 bool is_dp_hdmi_s3d_converter; 447 bool is_dp_hdmi_ycbcr422_pass_through; 448 bool is_dp_hdmi_ycbcr420_pass_through; 449 bool is_dp_hdmi_ycbcr422_converter; 450 bool is_dp_hdmi_ycbcr420_converter; 451 uint32_t dp_hdmi_max_bpc; 452 uint32_t dp_hdmi_max_pixel_clk_in_khz; 453 }; 454 /* Scaling format */ 455 enum scaling_transformation { 456 SCALING_TRANSFORMATION_UNINITIALIZED, 457 SCALING_TRANSFORMATION_IDENTITY = 0x0001, 458 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002, 459 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004, 460 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008, 461 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010, 462 SCALING_TRANSFORMATION_INVALID = 0x80000000, 463 464 /* Flag the first and last */ 465 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY, 466 SCALING_TRANSFORMATION_END = 467 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE 468 }; 469 470 enum display_content_type { 471 DISPLAY_CONTENT_TYPE_NO_DATA = 0, 472 DISPLAY_CONTENT_TYPE_GRAPHICS = 1, 473 DISPLAY_CONTENT_TYPE_PHOTO = 2, 474 DISPLAY_CONTENT_TYPE_CINEMA = 4, 475 DISPLAY_CONTENT_TYPE_GAME = 8 476 }; 477 478 /* writeback */ 479 struct dwb_stereo_params { 480 bool stereo_enabled; /* false: normal mode, true: 3D stereo */ 481 enum dwb_stereo_type stereo_type; /* indicates stereo format */ 482 bool stereo_polarity; /* indicates left eye or right eye comes first in stereo mode */ 483 enum dwb_stereo_eye_select stereo_eye_select; /* indicate which eye should be captured */ 484 }; 485 486 struct dc_dwb_cnv_params { 487 unsigned int src_width; /* input active width */ 488 unsigned int src_height; /* input active height (half-active height in interlaced mode) */ 489 unsigned int crop_width; /* cropped window width at cnv output */ 490 bool crop_en; /* window cropping enable in cnv */ 491 unsigned int crop_height; /* cropped window height at cnv output */ 492 unsigned int crop_x; /* cropped window start x value at cnv output */ 493 unsigned int crop_y; /* cropped window start y value at cnv output */ 494 enum dwb_cnv_out_bpc cnv_out_bpc; /* cnv output pixel depth - 8bpc or 10bpc */ 495 }; 496 497 struct dc_dwb_params { 498 struct dc_dwb_cnv_params cnv_params; /* CNV source size and cropping window parameters */ 499 unsigned int dest_width; /* Destination width */ 500 unsigned int dest_height; /* Destination height */ 501 enum dwb_scaler_mode out_format; /* default = YUV420 - TODO: limit this to 0 and 1 on dcn3 */ 502 enum dwb_output_depth output_depth; /* output pixel depth - 8bpc or 10bpc */ 503 enum dwb_capture_rate capture_rate; /* controls the frame capture rate */ 504 struct scaling_taps scaler_taps; /* Scaling taps */ 505 enum dwb_subsample_position subsample_position; 506 struct dc_transfer_func *out_transfer_func; 507 }; 508 509 /* audio*/ 510 511 union audio_sample_rates { 512 struct sample_rates { 513 uint8_t RATE_32:1; 514 uint8_t RATE_44_1:1; 515 uint8_t RATE_48:1; 516 uint8_t RATE_88_2:1; 517 uint8_t RATE_96:1; 518 uint8_t RATE_176_4:1; 519 uint8_t RATE_192:1; 520 } rate; 521 522 uint8_t all; 523 }; 524 525 struct audio_speaker_flags { 526 uint32_t FL_FR:1; 527 uint32_t LFE:1; 528 uint32_t FC:1; 529 uint32_t RL_RR:1; 530 uint32_t RC:1; 531 uint32_t FLC_FRC:1; 532 uint32_t RLC_RRC:1; 533 uint32_t SUPPORT_AI:1; 534 }; 535 536 struct audio_speaker_info { 537 uint32_t ALLSPEAKERS:7; 538 uint32_t SUPPORT_AI:1; 539 }; 540 541 542 struct audio_info_flags { 543 544 union { 545 546 struct audio_speaker_flags speaker_flags; 547 struct audio_speaker_info info; 548 549 uint8_t all; 550 }; 551 }; 552 553 enum audio_format_code { 554 AUDIO_FORMAT_CODE_FIRST = 1, 555 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST, 556 557 AUDIO_FORMAT_CODE_AC3, 558 /*Layers 1 & 2 */ 559 AUDIO_FORMAT_CODE_MPEG1, 560 /*MPEG1 Layer 3 */ 561 AUDIO_FORMAT_CODE_MP3, 562 /*multichannel */ 563 AUDIO_FORMAT_CODE_MPEG2, 564 AUDIO_FORMAT_CODE_AAC, 565 AUDIO_FORMAT_CODE_DTS, 566 AUDIO_FORMAT_CODE_ATRAC, 567 AUDIO_FORMAT_CODE_1BITAUDIO, 568 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS, 569 AUDIO_FORMAT_CODE_DTS_HD, 570 AUDIO_FORMAT_CODE_MAT_MLP, 571 AUDIO_FORMAT_CODE_DST, 572 AUDIO_FORMAT_CODE_WMAPRO, 573 AUDIO_FORMAT_CODE_LAST, 574 AUDIO_FORMAT_CODE_COUNT = 575 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST 576 }; 577 578 struct audio_mode { 579 /* ucData[0] [6:3] */ 580 enum audio_format_code format_code; 581 /* ucData[0] [2:0] */ 582 uint8_t channel_count; 583 /* ucData[1] */ 584 union audio_sample_rates sample_rates; 585 union { 586 /* for LPCM */ 587 uint8_t sample_size; 588 /* for Audio Formats 2-8 (Max bit rate divided by 8 kHz) */ 589 uint8_t max_bit_rate; 590 /* for Audio Formats 9-15 */ 591 uint8_t vendor_specific; 592 }; 593 }; 594 595 struct audio_info { 596 struct audio_info_flags flags; 597 uint32_t video_latency; 598 uint32_t audio_latency; 599 uint32_t display_index; 600 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS]; 601 uint32_t manufacture_id; 602 uint32_t product_id; 603 /* PortID used for ContainerID when defined */ 604 uint32_t port_id[2]; 605 uint32_t mode_count; 606 /* this field must be last in this struct */ 607 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT]; 608 }; 609 struct audio_check { 610 unsigned int audio_packet_type; 611 unsigned int max_audiosample_rate; 612 unsigned int acat; 613 }; 614 enum dc_infoframe_type { 615 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81, 616 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, 617 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, 618 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, 619 DC_DP_INFOFRAME_TYPE_PPS = 0x10, 620 }; 621 622 struct dc_info_packet { 623 bool valid; 624 uint8_t hb0; 625 uint8_t hb1; 626 uint8_t hb2; 627 uint8_t hb3; 628 uint8_t sb[32]; 629 }; 630 631 struct dc_info_packet_128 { 632 bool valid; 633 uint8_t hb0; 634 uint8_t hb1; 635 uint8_t hb2; 636 uint8_t hb3; 637 uint8_t sb[128]; 638 }; 639 640 #define DC_PLANE_UPDATE_TIMES_MAX 10 641 642 struct dc_plane_flip_time { 643 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX]; 644 unsigned int index; 645 unsigned int prev_update_time_in_us; 646 }; 647 648 struct psr_config { 649 unsigned char psr_version; 650 unsigned int psr_rfb_setup_time; 651 bool psr_exit_link_training_required; 652 bool psr_frame_capture_indication_req; 653 unsigned int psr_sdp_transmit_line_num_deadline; 654 bool allow_smu_optimizations; 655 }; 656 657 union dmcu_psr_level { 658 struct { 659 unsigned int SKIP_CRC:1; 660 unsigned int SKIP_DP_VID_STREAM_DISABLE:1; 661 unsigned int SKIP_PHY_POWER_DOWN:1; 662 unsigned int SKIP_AUX_ACK_CHECK:1; 663 unsigned int SKIP_CRTC_DISABLE:1; 664 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1; 665 unsigned int SKIP_SMU_NOTIFICATION:1; 666 unsigned int SKIP_AUTO_STATE_ADVANCE:1; 667 unsigned int DISABLE_PSR_ENTRY_ABORT:1; 668 unsigned int SKIP_SINGLE_OTG_DISABLE:1; 669 unsigned int RESERVED:22; 670 } bits; 671 unsigned int u32all; 672 }; 673 674 enum physical_phy_id { 675 PHYLD_0, 676 PHYLD_1, 677 PHYLD_2, 678 PHYLD_3, 679 PHYLD_4, 680 PHYLD_5, 681 PHYLD_6, 682 PHYLD_7, 683 PHYLD_8, 684 PHYLD_9, 685 PHYLD_COUNT, 686 PHYLD_UNKNOWN = (-1L) 687 }; 688 689 enum phy_type { 690 PHY_TYPE_UNKNOWN = 1, 691 PHY_TYPE_PCIE_PHY = 2, 692 PHY_TYPE_UNIPHY = 3, 693 }; 694 695 struct psr_context { 696 /* ddc line */ 697 enum channel_id channel; 698 /* Transmitter id */ 699 enum transmitter transmitterId; 700 /* Engine Id is used for Dig Be source select */ 701 enum engine_id engineId; 702 /* Controller Id used for Dig Fe source select */ 703 enum controller_id controllerId; 704 /* Pcie or Uniphy */ 705 enum phy_type phyType; 706 /* Physical PHY Id used by SMU interpretation */ 707 enum physical_phy_id smuPhyId; 708 /* Vertical total pixels from crtc timing. 709 * This is used for static screen detection. 710 * ie. If we want to detect half a frame, 711 * we use this to determine the hyst lines. 712 */ 713 unsigned int crtcTimingVerticalTotal; 714 /* PSR supported from panel capabilities and 715 * current display configuration 716 */ 717 bool psrSupportedDisplayConfig; 718 /* Whether fast link training is supported by the panel */ 719 bool psrExitLinkTrainingRequired; 720 /* If RFB setup time is greater than the total VBLANK time, 721 * it is not possible for the sink to capture the video frame 722 * in the same frame the SDP is sent. In this case, 723 * the frame capture indication bit should be set and an extra 724 * static frame should be transmitted to the sink. 725 */ 726 bool psrFrameCaptureIndicationReq; 727 /* Set the last possible line SDP may be transmitted without violating 728 * the RFB setup time or entering the active video frame. 729 */ 730 unsigned int sdpTransmitLineNumDeadline; 731 /* The VSync rate in Hz used to calculate the 732 * step size for smooth brightness feature 733 */ 734 unsigned int vsync_rate_hz; 735 unsigned int skipPsrWaitForPllLock; 736 unsigned int numberOfControllers; 737 /* Unused, for future use. To indicate that first changed frame from 738 * state3 shouldn't result in psr_inactive, but rather to perform 739 * an automatic single frame rfb_update. 740 */ 741 bool rfb_update_auto_en; 742 /* Number of frame before entering static screen */ 743 unsigned int timehyst_frames; 744 /* Partial frames before entering static screen */ 745 unsigned int hyst_lines; 746 /* # of repeated AUX transaction attempts to make before 747 * indicating failure to the driver 748 */ 749 unsigned int aux_repeats; 750 /* Controls hw blocks to power down during PSR active state */ 751 union dmcu_psr_level psr_level; 752 /* Controls additional delay after remote frame capture before 753 * continuing powerd own 754 */ 755 unsigned int frame_delay; 756 bool allow_smu_optimizations; 757 }; 758 759 struct colorspace_transform { 760 struct fixed31_32 matrix[12]; 761 bool enable_remap; 762 }; 763 764 enum i2c_mot_mode { 765 I2C_MOT_UNDEF, 766 I2C_MOT_TRUE, 767 I2C_MOT_FALSE 768 }; 769 770 struct AsicStateEx { 771 unsigned int memoryClock; 772 unsigned int displayClock; 773 unsigned int engineClock; 774 unsigned int maxSupportedDppClock; 775 unsigned int dppClock; 776 unsigned int socClock; 777 unsigned int dcfClockDeepSleep; 778 unsigned int fClock; 779 unsigned int phyClock; 780 }; 781 782 783 enum dc_clock_type { 784 DC_CLOCK_TYPE_DISPCLK = 0, 785 DC_CLOCK_TYPE_DPPCLK = 1, 786 }; 787 788 struct dc_clock_config { 789 uint32_t max_clock_khz; 790 uint32_t min_clock_khz; 791 uint32_t bw_requirequired_clock_khz; 792 uint32_t current_clock_khz;/*current clock in use*/ 793 }; 794 795 /* DSC DPCD capabilities */ 796 union dsc_slice_caps1 { 797 struct { 798 uint8_t NUM_SLICES_1 : 1; 799 uint8_t NUM_SLICES_2 : 1; 800 uint8_t RESERVED : 1; 801 uint8_t NUM_SLICES_4 : 1; 802 uint8_t NUM_SLICES_6 : 1; 803 uint8_t NUM_SLICES_8 : 1; 804 uint8_t NUM_SLICES_10 : 1; 805 uint8_t NUM_SLICES_12 : 1; 806 } bits; 807 uint8_t raw; 808 }; 809 810 union dsc_slice_caps2 { 811 struct { 812 uint8_t NUM_SLICES_16 : 1; 813 uint8_t NUM_SLICES_20 : 1; 814 uint8_t NUM_SLICES_24 : 1; 815 uint8_t RESERVED : 5; 816 } bits; 817 uint8_t raw; 818 }; 819 820 union dsc_color_formats { 821 struct { 822 uint8_t RGB : 1; 823 uint8_t YCBCR_444 : 1; 824 uint8_t YCBCR_SIMPLE_422 : 1; 825 uint8_t YCBCR_NATIVE_422 : 1; 826 uint8_t YCBCR_NATIVE_420 : 1; 827 uint8_t RESERVED : 3; 828 } bits; 829 uint8_t raw; 830 }; 831 832 union dsc_color_depth { 833 struct { 834 uint8_t RESERVED1 : 1; 835 uint8_t COLOR_DEPTH_8_BPC : 1; 836 uint8_t COLOR_DEPTH_10_BPC : 1; 837 uint8_t COLOR_DEPTH_12_BPC : 1; 838 uint8_t RESERVED2 : 3; 839 } bits; 840 uint8_t raw; 841 }; 842 843 struct dsc_dec_dpcd_caps { 844 bool is_dsc_supported; 845 uint8_t dsc_version; 846 int32_t rc_buffer_size; /* DSC RC buffer block size in bytes */ 847 union dsc_slice_caps1 slice_caps1; 848 union dsc_slice_caps2 slice_caps2; 849 int32_t lb_bit_depth; 850 bool is_block_pred_supported; 851 int32_t edp_max_bits_per_pixel; /* Valid only in eDP */ 852 union dsc_color_formats color_formats; 853 union dsc_color_depth color_depth; 854 int32_t throughput_mode_0_mps; /* In MPs */ 855 int32_t throughput_mode_1_mps; /* In MPs */ 856 int32_t max_slice_width; 857 uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */ 858 859 /* Extended DSC caps */ 860 uint32_t branch_overall_throughput_0_mps; /* In MPs */ 861 uint32_t branch_overall_throughput_1_mps; /* In MPs */ 862 uint32_t branch_max_line_width; 863 }; 864 865 #endif /* DC_TYPES_H_ */ 866
Indexes created Sat Sep 20 22:09:52 GMT 2025