1 /* $NetBSD: dcareg.h,v 1.2 2005/12/11 12:17:19 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1982, 1986, 1990, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * @(#)dcareg.h 8.1 (Berkeley) 6/10/93 32 */ 33 34 #include <hp300/dev/iotypes.h> /* XXX */ 35 36 #ifdef hp700 37 struct dcadevice { 38 vu_char dca_reset; 39 vu_char dca_pad[0x800-1]; 40 vu_char dca_data; /* receive buf or xmit hold */ 41 vu_char dca_ier; /* interrupt enable */ 42 vu_char dca_iir; /* (RO) interrupt identify */ 43 #define dca_fifo dca_iir /* (WO) FIFO control */ 44 vu_char dca_cfcr; /* line control */ 45 vu_char dca_mcr; /* modem control */ 46 vu_char dca_lsr; /* line status */ 47 vu_char dca_msr; /* modem status */ 48 vu_char dca_scr; /* scratch pad */ 49 }; 50 #else 51 struct dcadevice { 52 /* card registers */ 53 u_char dca_pad0; 54 vu_char dca_id; /* 0x01 (read) */ 55 #define dca_reset dca_id /* 0x01 (write) */ 56 u_char dca_pad1; 57 vu_char dca_ic; /* 0x03 */ 58 u_char dca_pad2; 59 vu_char dca_ocbrc; /* 0x05 */ 60 u_char dca_pad3; 61 vu_char dca_lcsm; /* 0x07 */ 62 u_char dca_pad4[8]; 63 /* chip registers */ 64 u_char dca_pad5; 65 vu_char dca_data; /* 0x11 */ 66 u_char dca_pad6; 67 vu_char dca_ier; /* 0x13 */ 68 u_char dca_pad7; 69 vu_char dca_iir; /* 0x15 (read) */ 70 #define dca_fifo dca_iir /* 0x15 (write) */ 71 u_char dca_pad8; 72 vu_char dca_cfcr; /* 0x17 */ 73 u_char dca_pad9; 74 vu_char dca_mcr; /* 0x19 */ 75 u_char dca_padA; 76 vu_char dca_lsr; /* 0x1B */ 77 u_char dca_padB; 78 vu_char dca_msr; /* 0x1D */ 79 }; 80 #endif 81 82 /* interface reset/id (300 only) */ 83 #define DCAID0 0x02 84 #define DCAREMID0 0x82 85 #define DCAID1 0x42 86 #define DCAREMID1 0xC2 87 88 /* interrupt control (300 only) */ 89 #define DCAIPL(x) ((((x) >> 4) & 3) + 3) 90 #define IC_IR 0x40 91 #define IC_IE 0x80 92 93 /* 94 * 16 bit baud rate divisor (lower byte in dca_data, upper in dca_ier) 95 * NB: This constant is for a 7.3728 clock frequency. The 300 clock 96 * frequency is 2.4576, giving a constant of 153600. 97 */ 98 #ifdef hp300 99 #define DCABRD(x) (153600 / (x)) 100 #endif 101 #ifdef hp700 102 #define DCABRD(x) (460800 / (x)) 103 #endif 104 105 /* interrupt enable register */ 106 #define IER_ERXRDY 0x1 107 #define IER_ETXRDY 0x2 108 #define IER_ERLS 0x4 109 #define IER_EMSC 0x8 110 111 /* interrupt identification register */ 112 #define IIR_IMASK 0xf 113 #define IIR_RXTOUT 0xc 114 #define IIR_RLS 0x6 115 #define IIR_RXRDY 0x4 116 #define IIR_TXRDY 0x2 117 #define IIR_NOPEND 0x1 118 #define IIR_MLSC 0x0 119 #define IIR_FIFO_MASK 0xc0 /* set if FIFOs are enabled */ 120 121 /* fifo control register */ 122 #define FIFO_ENABLE 0x01 123 #define FIFO_RCV_RST 0x02 124 #define FIFO_XMT_RST 0x04 125 #define FIFO_DMA_MODE 0x08 126 #define FIFO_TRIGGER_1 0x00 127 #define FIFO_TRIGGER_4 0x40 128 #define FIFO_TRIGGER_8 0x80 129 #define FIFO_TRIGGER_14 0xc0 130 131 /* character format control register */ 132 #define CFCR_DLAB 0x80 133 #define CFCR_SBREAK 0x40 134 #define CFCR_PZERO 0x30 135 #define CFCR_PONE 0x20 136 #define CFCR_PEVEN 0x10 137 #define CFCR_PODD 0x00 138 #define CFCR_PENAB 0x08 139 #define CFCR_STOPB 0x04 140 #define CFCR_8BITS 0x03 141 #define CFCR_7BITS 0x02 142 #define CFCR_6BITS 0x01 143 #define CFCR_5BITS 0x00 144 145 /* modem control register */ 146 #define MCR_LOOPBACK 0x10 147 #define MCR_IEN 0x08 148 #define MCR_DRS 0x04 149 #define MCR_RTS 0x02 150 #define MCR_DTR 0x01 151 152 /* line status register */ 153 #define LSR_RCV_FIFO 0x80 154 #define LSR_TSRE 0x40 155 #define LSR_TXRDY 0x20 156 #define LSR_BI 0x10 157 #define LSR_FE 0x08 158 #define LSR_PE 0x04 159 #define LSR_OE 0x02 160 #define LSR_RXRDY 0x01 161 #define LSR_RCV_MASK 0x1f 162 163 /* modem status register */ 164 #define MSR_DCD 0x80 165 #define MSR_RI 0x40 166 #define MSR_DSR 0x20 167 #define MSR_CTS 0x10 168 #define MSR_DDCD 0x08 169 #define MSR_TERI 0x04 170 #define MSR_DDSR 0x02 171 #define MSR_DCTS 0x01 172
Indexes created Sat Sep 20 22:09:52 GMT 2025