1 /* $NetBSD: cache.h,v 1.31 2022/05/16 21:28:05 mrg Exp $ */ 2 3 /* 4 * Copyright (c) 2011 Matthew R. Green 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * Copyright (C) 1996-1999 Eduardo Horvath. 31 * All rights reserved. 32 * 33 * Redistribution and use in source and binary forms, with or without 34 * modification, are permitted provided that the following conditions 35 * are met: 36 * 1. Redistributions of source code must retain the above copyright 37 * notice, this list of conditions and the following disclaimer. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 40 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 41 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 42 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 43 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 44 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 45 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 46 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 47 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 48 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 49 * SUCH DAMAGE. 50 * 51 */ 52 53 /* 54 * The spitfire has a 16K two-way set-associative L1 I$ and a separate 55 * 16K L2 D$. The I$ can be invalidated using the FLUSH instructions, 56 * so we don't really need to worry about it much. The D$ is a 16K 57 * write-through, direct mapped virtually-addressed cache with two 16-byte 58 * sub-blocks per line. The E$ is a 512KB to 4MB direct mapped 59 * physically-indexed physically-tagged cache. Since the L1 caches 60 * are write-through, they don't need flushing and can be invalidated directly. 61 * 62 * The spitfire sees virtual addresses as: 63 * 64 * struct cache_va { 65 * uint64_t :22, (unused; VAs are only 40 bits) 66 * cva_tag:28, (tag ID) 67 * cva_line:9, (cache line number) 68 * cva_byte:5; (byte within line) 69 * }; 70 * 71 * Since there is one bit of overlap between the page offset and the line index, 72 * all we need to do is make sure that bit 14 of the va remains constant 73 * and we have no aliasing problems. 74 * 75 * Let me try again... 76 * Page size is 8K, cache size is 16K so if (va1 & 0x3fff != va2 & 0x3fff) 77 * then we have a problem. Bit 14 *must* be the same for all mappings 78 * of a page to be cacheable in the D$. (The I$ is 16K 2-way 79 * set-associative -- each bank is 8K. No conflict there.) 80 */ 81 82 #include <machine/psl.h> 83 #include <machine/hypervisor.h> 84 85 /* Various cache size/line sizes */ 86 extern int ecache_min_line_size; 87 extern int dcache_line_size; 88 extern int dcache_size; 89 extern int icache_line_size; 90 extern int icache_size; 91 92 /* The following are for I$ and D$ flushes and are in locore.s */ 93 void dcache_flush_page_us(paddr_t); /* flush page from D$ */ 94 void dcache_flush_page_usiii(paddr_t); /* flush page from D$ */ 95 void sp_blast_dcache(int, int); /* Clear entire D$ */ 96 void sp_blast_dcache_disabled(int, int); /* Above with D$ disable. */ 97 void blast_icache_us(void); /* Clear entire I$ */ 98 void blast_icache_usiii(void); /* Clear entire I$ */ 99 100 /* The following flush a range from the D$ and I$ but not E$. */ 101 void cache_flush_phys_us(paddr_t, psize_t, int); 102 void cache_flush_phys_usiii(paddr_t, psize_t, int); 103 extern void (*cache_flush_phys)(paddr_t, psize_t, int); 104 105 /* SPARC64 specific */ 106 /* Assembly routines to flush TLB mappings */ 107 void sp_tlb_flush_pte_us(vaddr_t, int); 108 void sp_tlb_flush_pte_usiii(vaddr_t, int); 109 void sp_tlb_flush_all_us(void); 110 void sp_tlb_flush_all_usiii(void); 111 112 113 extern void (*dcache_flush_page)(paddr_t); 114 extern void (*dcache_flush_page_cpuset)(paddr_t, sparc64_cpuset_t); 115 extern void (*blast_dcache)(void); 116 extern void (*blast_icache)(void); 117 extern void (*sp_tlb_flush_pte)(vaddr_t, int); 118 extern void (*sp_tlb_flush_all)(void); 119 120 void cache_setup_funcs(void); 121 122 #ifdef MULTIPROCESSOR 123 extern void (*sp_dcache_flush_page)(paddr_t); 124 125 void smp_tlb_flush_pte(vaddr_t, struct pmap *); 126 void smp_dcache_flush_page_cpuset(paddr_t, sparc64_cpuset_t); 127 void smp_dcache_flush_page_allcpu(paddr_t); 128 void smp_blast_dcache(void); 129 #define tlb_flush_pte(va,pm) smp_tlb_flush_pte(va, pm) 130 #define dcache_flush_page_all(pa) smp_dcache_flush_page_cpuset(pa, cpus_active) 131 #define dcache_flush_page_cpuset(pa,cs) smp_dcache_flush_page_cpuset(pa, cs) 132 #else 133 #define tlb_flush_pte(va,pm) sp_tlb_flush_pte(va, (pm)->pm_ctx[0]) 134 #define dcache_flush_page_all(pa) dcache_flush_page(pa) 135 #define dcache_flush_page_cpuset(pa,cs) dcache_flush_page(pa) 136 #endif 137
Indexes created Tue Sep 23 14:10:03 GMT 2025