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      1 /*	$NetBSD: amdgpu_dce100_hw_sequencer.c,v 1.2 2021/12/18 23:45:02 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2015 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: AMD
     25  *
     26  */
     27 #include <sys/cdefs.h>
     28 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce100_hw_sequencer.c,v 1.2 2021/12/18 23:45:02 riastradh Exp $");
     29 
     30 #include "dm_services.h"
     31 #include "dc.h"
     32 #include "core_types.h"
     33 #include "clk_mgr.h"
     34 #include "dce100_hw_sequencer.h"
     35 #include "resource.h"
     36 
     37 #include "dce110/dce110_hw_sequencer.h"
     38 
     39 /* include DCE10 register header files */
     40 #include "dce/dce_10_0_d.h"
     41 #include "dce/dce_10_0_sh_mask.h"
     42 
     43 struct dce100_hw_seq_reg_offsets {
     44 	uint32_t blnd;
     45 	uint32_t crtc;
     46 };
     47 
     48 static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
     49 {
     50 	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     51 },
     52 {
     53 	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     54 },
     55 {
     56 	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     57 },
     58 {
     59 	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     60 },
     61 {
     62 	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     63 },
     64 {
     65 	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     66 }
     67 };
     68 
     69 #define HW_REG_CRTC(reg, id)\
     70 	(reg + reg_offsets[id].crtc)
     71 
     72 /*******************************************************************************
     73  * Private definitions
     74  ******************************************************************************/
     75 /***************************PIPE_CONTROL***********************************/
     76 
     77 bool dce100_enable_display_power_gating(
     78 	struct dc *dc,
     79 	uint8_t controller_id,
     80 	struct dc_bios *dcb,
     81 	enum pipe_gating_control power_gating)
     82 {
     83 	enum bp_result bp_result = BP_RESULT_OK;
     84 	enum bp_pipe_control_action cntl;
     85 	struct dc_context *ctx = dc->ctx;
     86 
     87 	if (power_gating == PIPE_GATING_CONTROL_INIT)
     88 		cntl = ASIC_PIPE_INIT;
     89 	else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
     90 		cntl = ASIC_PIPE_ENABLE;
     91 	else
     92 		cntl = ASIC_PIPE_DISABLE;
     93 
     94 	if (!(power_gating == PIPE_GATING_CONTROL_INIT && controller_id != 0)){
     95 
     96 		bp_result = dcb->funcs->enable_disp_power_gating(
     97 						dcb, controller_id + 1, cntl);
     98 
     99 		/* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
    100 		 * by default when command table is called
    101 		 */
    102 		dm_write_reg(ctx,
    103 			HW_REG_CRTC(mmMASTER_UPDATE_MODE, controller_id),
    104 			0);
    105 	}
    106 
    107 	if (bp_result == BP_RESULT_OK)
    108 		return true;
    109 	else
    110 		return false;
    111 }
    112 
    113 void dce100_prepare_bandwidth(
    114 		struct dc *dc,
    115 		struct dc_state *context)
    116 {
    117 	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
    118 
    119 	dc->clk_mgr->funcs->update_clocks(
    120 			dc->clk_mgr,
    121 			context,
    122 			false);
    123 }
    124 
    125 void dce100_optimize_bandwidth(
    126 		struct dc *dc,
    127 		struct dc_state *context)
    128 {
    129 	dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
    130 
    131 	dc->clk_mgr->funcs->update_clocks(
    132 			dc->clk_mgr,
    133 			context,
    134 			true);
    135 }
    136 
    137 /**************************************************************************/
    138 
    139 void dce100_hw_sequencer_construct(struct dc *dc)
    140 {
    141 	dce110_hw_sequencer_construct(dc);
    142 
    143 	dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
    144 	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
    145 	dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
    146 }
    147 
    148