1 /* $NetBSD: amdgpu_dce110_clk_mgr.c,v 1.2 2021/12/18 23:45:01 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-16 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce110_clk_mgr.c,v 1.2 2021/12/18 23:45:01 riastradh Exp $"); 30 31 #include "core_types.h" 32 #include "clk_mgr_internal.h" 33 34 #include "dce/dce_11_0_d.h" 35 #include "dce/dce_11_0_sh_mask.h" 36 #include "dce110_clk_mgr.h" 37 #include "../clk_mgr/dce100/dce_clk_mgr.h" 38 39 /* set register offset */ 40 #define SR(reg_name)\ 41 .reg_name = mm ## reg_name 42 43 /* set register offset with instance */ 44 #define SRI(reg_name, block, id)\ 45 .reg_name = mm ## block ## id ## _ ## reg_name 46 47 static const struct clk_mgr_registers disp_clk_regs = { 48 CLK_COMMON_REG_LIST_DCE_BASE() 49 }; 50 51 static const struct clk_mgr_shift disp_clk_shift = { 52 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 53 }; 54 55 static const struct clk_mgr_mask disp_clk_mask = { 56 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 57 }; 58 59 static const struct state_dependent_clocks dce110_max_clks_by_state[] = { 60 /*ClocksStateInvalid - should not be used*/ 61 { .display_clk_khz = 0, .pixel_clk_khz = 0 }, 62 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/ 63 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, 64 /*ClocksStateLow*/ 65 { .display_clk_khz = 352000, .pixel_clk_khz = 330000 }, 66 /*ClocksStateNominal*/ 67 { .display_clk_khz = 467000, .pixel_clk_khz = 400000 }, 68 /*ClocksStatePerformance*/ 69 { .display_clk_khz = 643000, .pixel_clk_khz = 400000 } }; 70 71 static int determine_sclk_from_bounding_box( 72 const struct dc *dc, 73 int required_sclk) 74 { 75 int i; 76 77 /* 78 * Some asics do not give us sclk levels, so we just report the actual 79 * required sclk 80 */ 81 if (dc->sclk_lvls.num_levels == 0) 82 return required_sclk; 83 84 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { 85 if (dc->sclk_lvls.clocks_in_khz[i] >= required_sclk) 86 return dc->sclk_lvls.clocks_in_khz[i]; 87 } 88 /* 89 * even maximum level could not satisfy requirement, this 90 * is unexpected at this stage, should have been caught at 91 * validation time 92 */ 93 ASSERT(0); 94 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1]; 95 } 96 97 uint32_t dce110_get_min_vblank_time_us(const struct dc_state *context) 98 { 99 uint8_t j; 100 uint32_t min_vertical_blank_time = -1; 101 102 for (j = 0; j < context->stream_count; j++) { 103 struct dc_stream_state *stream = context->streams[j]; 104 uint32_t vertical_blank_in_pixels = 0; 105 uint32_t vertical_blank_time = 0; 106 uint32_t vertical_total_min = stream->timing.v_total; 107 struct dc_crtc_timing_adjust adjust = stream->adjust; 108 if (adjust.v_total_max != adjust.v_total_min) 109 vertical_total_min = adjust.v_total_min; 110 111 vertical_blank_in_pixels = stream->timing.h_total * 112 (vertical_total_min 113 - stream->timing.v_addressable); 114 vertical_blank_time = vertical_blank_in_pixels 115 * 10000 / stream->timing.pix_clk_100hz; 116 117 if (min_vertical_blank_time > vertical_blank_time) 118 min_vertical_blank_time = vertical_blank_time; 119 } 120 121 return min_vertical_blank_time; 122 } 123 124 void dce110_fill_display_configs( 125 const struct dc_state *context, 126 struct dm_pp_display_configuration *pp_display_cfg) 127 { 128 int j; 129 int num_cfgs = 0; 130 131 for (j = 0; j < context->stream_count; j++) { 132 int k; 133 134 const struct dc_stream_state *stream = context->streams[j]; 135 struct dm_pp_single_disp_config *cfg = 136 &pp_display_cfg->disp_configs[num_cfgs]; 137 const struct pipe_ctx *pipe_ctx = NULL; 138 139 for (k = 0; k < MAX_PIPES; k++) 140 if (stream == context->res_ctx.pipe_ctx[k].stream) { 141 pipe_ctx = &context->res_ctx.pipe_ctx[k]; 142 break; 143 } 144 145 ASSERT(pipe_ctx != NULL); 146 147 /* only notify active stream */ 148 if (stream->dpms_off) 149 continue; 150 151 num_cfgs++; 152 cfg->signal = pipe_ctx->stream->signal; 153 cfg->pipe_idx = pipe_ctx->stream_res.tg->inst; 154 cfg->src_height = stream->src.height; 155 cfg->src_width = stream->src.width; 156 cfg->ddi_channel_mapping = 157 stream->link->ddi_channel_mapping.raw; 158 cfg->transmitter = 159 stream->link->link_enc->transmitter; 160 cfg->link_settings.lane_count = 161 stream->link->cur_link_settings.lane_count; 162 cfg->link_settings.link_rate = 163 stream->link->cur_link_settings.link_rate; 164 cfg->link_settings.link_spread = 165 stream->link->cur_link_settings.link_spread; 166 cfg->sym_clock = stream->phy_pix_clk; 167 /* Round v_refresh*/ 168 cfg->v_refresh = stream->timing.pix_clk_100hz * 100; 169 cfg->v_refresh /= stream->timing.h_total; 170 cfg->v_refresh = (cfg->v_refresh + stream->timing.v_total / 2) 171 / stream->timing.v_total; 172 } 173 174 pp_display_cfg->display_count = num_cfgs; 175 } 176 177 void dce11_pplib_apply_display_requirements( 178 struct dc *dc, 179 struct dc_state *context) 180 { 181 struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg; 182 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; 183 184 if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm) 185 memory_type_multiplier = MEMORY_TYPE_HBM; 186 187 pp_display_cfg->all_displays_in_sync = 188 context->bw_ctx.bw.dce.all_displays_in_sync; 189 pp_display_cfg->nb_pstate_switch_disable = 190 context->bw_ctx.bw.dce.nbp_state_change_enable == false; 191 pp_display_cfg->cpu_cc6_disable = 192 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; 193 pp_display_cfg->cpu_pstate_disable = 194 context->bw_ctx.bw.dce.cpup_state_change_enable == false; 195 pp_display_cfg->cpu_pstate_separation_time = 196 context->bw_ctx.bw.dce.blackout_recovery_time_us; 197 198 /* 199 * TODO: determine whether the bandwidth has reached memory's limitation 200 * , then change minimum memory clock based on real-time bandwidth 201 * limitation. 202 */ 203 if (ASICREV_IS_VEGA20_P(dc->ctx->asic_id.hw_internal_rev) && (context->stream_count >= 2)) { 204 pp_display_cfg->min_memory_clock_khz = max(pp_display_cfg->min_memory_clock_khz, 205 (uint32_t) div64_s64( 206 div64_s64(dc->bw_vbios->high_yclk.value, 207 memory_type_multiplier), 10000)); 208 } else { 209 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz 210 / memory_type_multiplier; 211 } 212 213 pp_display_cfg->min_engine_clock_khz = determine_sclk_from_bounding_box( 214 dc, 215 context->bw_ctx.bw.dce.sclk_khz); 216 217 /* 218 * As workaround for >4x4K lightup set dcfclock to min_engine_clock value. 219 * This is not required for less than 5 displays, 220 * thus don't request decfclk in dc to avoid impact 221 * on power saving. 222 * 223 */ 224 pp_display_cfg->min_dcfclock_khz = (context->stream_count > 4) ? 225 pp_display_cfg->min_engine_clock_khz : 0; 226 227 pp_display_cfg->min_engine_clock_deep_sleep_khz 228 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; 229 230 pp_display_cfg->avail_mclk_switch_time_us = 231 dce110_get_min_vblank_time_us(context); 232 /* TODO: dce11.2*/ 233 pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0; 234 235 pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz; 236 237 dce110_fill_display_configs(context, pp_display_cfg); 238 239 /* TODO: is this still applicable?*/ 240 if (pp_display_cfg->display_count == 1) { 241 const struct dc_crtc_timing *timing = 242 &context->streams[0]->timing; 243 244 pp_display_cfg->crtc_index = 245 pp_display_cfg->disp_configs[0].pipe_idx; 246 pp_display_cfg->line_time_in_us = timing->h_total * 10000 / timing->pix_clk_100hz; 247 } 248 249 if (memcmp(&dc->current_state->pp_display_cfg, pp_display_cfg, sizeof(*pp_display_cfg)) != 0) 250 dm_pp_apply_display_requirements(dc->ctx, pp_display_cfg); 251 } 252 253 static void dce11_update_clocks(struct clk_mgr *clk_mgr_base, 254 struct dc_state *context, 255 bool safe_to_lower) 256 { 257 struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base); 258 struct dm_pp_power_level_change_request level_change_req; 259 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; 260 261 /*TODO: W/A for dal3 linux, investigate why this works */ 262 if (!clk_mgr_dce->dfs_bypass_active) 263 patched_disp_clk = patched_disp_clk * 115 / 100; 264 265 level_change_req.power_level = dce_get_required_clocks_state(clk_mgr_base, context); 266 /* get max clock state from PPLIB */ 267 if ((level_change_req.power_level < clk_mgr_dce->cur_min_clks_state && safe_to_lower) 268 || level_change_req.power_level > clk_mgr_dce->cur_min_clks_state) { 269 if (dm_pp_apply_power_level_change_request(clk_mgr_base->ctx, &level_change_req)) 270 clk_mgr_dce->cur_min_clks_state = level_change_req.power_level; 271 } 272 273 if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) { 274 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); 275 clk_mgr_base->clks.dispclk_khz = patched_disp_clk; 276 } 277 dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context); 278 } 279 280 static struct clk_mgr_funcs dce110_funcs = { 281 .get_dp_ref_clk_frequency = dce_get_dp_ref_freq_khz, 282 .update_clocks = dce11_update_clocks 283 }; 284 285 void dce110_clk_mgr_construct( 286 struct dc_context *ctx, 287 struct clk_mgr_internal *clk_mgr) 288 { 289 dce_clk_mgr_construct(ctx, clk_mgr); 290 291 memcpy(clk_mgr->max_clks_by_state, 292 dce110_max_clks_by_state, 293 sizeof(dce110_max_clks_by_state)); 294 295 clk_mgr->regs = &disp_clk_regs; 296 clk_mgr->clk_mgr_shift = &disp_clk_shift; 297 clk_mgr->clk_mgr_mask = &disp_clk_mask; 298 clk_mgr->base.funcs = &dce110_funcs; 299 300 } 301
Indexes created Sun Sep 21 18:09:52 GMT 2025