1 /* $NetBSD: dce_link_encoder.h,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DC_LINK_ENCODER__DCE110_H__ 29 #define __DC_LINK_ENCODER__DCE110_H__ 30 31 #include "link_encoder.h" 32 33 #define TO_DCE110_LINK_ENC(link_encoder)\ 34 container_of(link_encoder, struct dce110_link_encoder, base) 35 36 /* Not found regs in dce120 spec 37 * BIOS_SCRATCH_2 38 * DP_DPHY_INTERNAL_CTRL 39 */ 40 41 #define AUX_REG_LIST(id)\ 42 SRI(AUX_CONTROL, DP_AUX, id), \ 43 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id) 44 45 #define HPD_REG_LIST(id)\ 46 SRI(DC_HPD_CONTROL, HPD, id) 47 48 #define LE_COMMON_REG_LIST_BASE(id) \ 49 SR(DMCU_RAM_ACCESS_CTRL), \ 50 SR(DMCU_IRAM_RD_CTRL), \ 51 SR(DMCU_IRAM_RD_DATA), \ 52 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 53 SRI(DIG_BE_CNTL, DIG, id), \ 54 SRI(DIG_BE_EN_CNTL, DIG, id), \ 55 SRI(DP_CONFIG, DP, id), \ 56 SRI(DP_DPHY_CNTL, DP, id), \ 57 SRI(DP_DPHY_PRBS_CNTL, DP, id), \ 58 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\ 59 SRI(DP_DPHY_SYM0, DP, id), \ 60 SRI(DP_DPHY_SYM1, DP, id), \ 61 SRI(DP_DPHY_SYM2, DP, id), \ 62 SRI(DP_DPHY_TRAINING_PATTERN_SEL, DP, id), \ 63 SRI(DP_LINK_CNTL, DP, id), \ 64 SRI(DP_LINK_FRAMING_CNTL, DP, id), \ 65 SRI(DP_MSE_SAT0, DP, id), \ 66 SRI(DP_MSE_SAT1, DP, id), \ 67 SRI(DP_MSE_SAT2, DP, id), \ 68 SRI(DP_MSE_SAT_UPDATE, DP, id), \ 69 SRI(DP_SEC_CNTL, DP, id), \ 70 SRI(DP_VID_STREAM_CNTL, DP, id), \ 71 SRI(DP_DPHY_FAST_TRAINING, DP, id), \ 72 SRI(DP_SEC_CNTL1, DP, id) 73 74 #define LE_COMMON_REG_LIST(id)\ 75 LE_COMMON_REG_LIST_BASE(id), \ 76 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 77 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 78 SR(DCI_MEM_PWR_STATUS) 79 80 #define LE_DCE80_REG_LIST(id)\ 81 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 82 LE_COMMON_REG_LIST_BASE(id) 83 84 #define LE_DCE100_REG_LIST(id)\ 85 LE_COMMON_REG_LIST_BASE(id), \ 86 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 87 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 88 SR(DCI_MEM_PWR_STATUS) 89 90 #define LE_DCE110_REG_LIST(id)\ 91 LE_COMMON_REG_LIST_BASE(id), \ 92 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 93 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 94 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ 95 SR(DCI_MEM_PWR_STATUS) 96 97 #define LE_DCE120_REG_LIST(id)\ 98 LE_COMMON_REG_LIST_BASE(id), \ 99 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 100 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id), \ 101 SR(DCI_MEM_PWR_STATUS) 102 103 #define LE_DCN10_REG_LIST(id)\ 104 LE_COMMON_REG_LIST_BASE(id), \ 105 SRI(DP_DPHY_BS_SR_SWAP_CNTL, DP, id), \ 106 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \ 107 SRI(DP_DPHY_HBR2_PATTERN_CONTROL, DP, id) 108 109 struct dce110_link_enc_aux_registers { 110 uint32_t AUX_CONTROL; 111 uint32_t AUX_DPHY_RX_CONTROL0; 112 }; 113 114 struct dce110_link_enc_hpd_registers { 115 uint32_t DC_HPD_CONTROL; 116 }; 117 118 struct dce110_link_enc_registers { 119 /* DMCU registers */ 120 uint32_t MASTER_COMM_DATA_REG1; 121 uint32_t MASTER_COMM_DATA_REG2; 122 uint32_t MASTER_COMM_DATA_REG3; 123 uint32_t MASTER_COMM_CMD_REG; 124 uint32_t MASTER_COMM_CNTL_REG; 125 uint32_t DMCU_RAM_ACCESS_CTRL; 126 uint32_t DCI_MEM_PWR_STATUS; 127 uint32_t DMU_MEM_PWR_CNTL; 128 uint32_t DMCU_IRAM_RD_CTRL; 129 uint32_t DMCU_IRAM_RD_DATA; 130 uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; 131 132 /* Common DP registers */ 133 uint32_t DIG_BE_CNTL; 134 uint32_t DIG_BE_EN_CNTL; 135 uint32_t DP_CONFIG; 136 uint32_t DP_DPHY_CNTL; 137 uint32_t DP_DPHY_INTERNAL_CTRL; 138 uint32_t DP_DPHY_PRBS_CNTL; 139 uint32_t DP_DPHY_SCRAM_CNTL; 140 uint32_t DP_DPHY_SYM0; 141 uint32_t DP_DPHY_SYM1; 142 uint32_t DP_DPHY_SYM2; 143 uint32_t DP_DPHY_TRAINING_PATTERN_SEL; 144 uint32_t DP_LINK_CNTL; 145 uint32_t DP_LINK_FRAMING_CNTL; 146 uint32_t DP_MSE_SAT0; 147 uint32_t DP_MSE_SAT1; 148 uint32_t DP_MSE_SAT2; 149 uint32_t DP_MSE_SAT_UPDATE; 150 uint32_t DP_SEC_CNTL; 151 uint32_t DP_VID_STREAM_CNTL; 152 uint32_t DP_DPHY_FAST_TRAINING; 153 uint32_t DP_DPHY_BS_SR_SWAP_CNTL; 154 uint32_t DP_DPHY_HBR2_PATTERN_CONTROL; 155 uint32_t DP_SEC_CNTL1; 156 }; 157 158 struct dce110_link_encoder { 159 struct link_encoder base; 160 const struct dce110_link_enc_registers *link_regs; 161 const struct dce110_link_enc_aux_registers *aux_regs; 162 const struct dce110_link_enc_hpd_registers *hpd_regs; 163 }; 164 165 166 void dce110_link_encoder_construct( 167 struct dce110_link_encoder *enc110, 168 const struct encoder_init_data *init_data, 169 const struct encoder_feature_support *enc_features, 170 const struct dce110_link_enc_registers *link_regs, 171 const struct dce110_link_enc_aux_registers *aux_regs, 172 const struct dce110_link_enc_hpd_registers *hpd_regs); 173 174 bool dce110_link_encoder_validate_dvi_output( 175 const struct dce110_link_encoder *enc110, 176 enum signal_type connector_signal, 177 enum signal_type signal, 178 const struct dc_crtc_timing *crtc_timing); 179 180 bool dce110_link_encoder_validate_rgb_output( 181 const struct dce110_link_encoder *enc110, 182 const struct dc_crtc_timing *crtc_timing); 183 184 bool dce110_link_encoder_validate_dp_output( 185 const struct dce110_link_encoder *enc110, 186 const struct dc_crtc_timing *crtc_timing); 187 188 bool dce110_link_encoder_validate_wireless_output( 189 const struct dce110_link_encoder *enc110, 190 const struct dc_crtc_timing *crtc_timing); 191 192 bool dce110_link_encoder_validate_output_with_stream( 193 struct link_encoder *enc, 194 const struct dc_stream_state *stream); 195 196 /****************** HW programming ************************/ 197 198 /* initialize HW */ /* why do we initialze aux in here? */ 199 void dce110_link_encoder_hw_init(struct link_encoder *enc); 200 201 void dce110_link_encoder_destroy(struct link_encoder **enc); 202 203 /* program DIG_MODE in DIG_BE */ 204 /* TODO can this be combined with enable_output? */ 205 void dce110_link_encoder_setup( 206 struct link_encoder *enc, 207 enum signal_type signal); 208 209 /* enables TMDS PHY output */ 210 /* TODO: still need depth or just pass in adjusted pixel clock? */ 211 void dce110_link_encoder_enable_tmds_output( 212 struct link_encoder *enc, 213 enum clock_source_id clock_source, 214 enum dc_color_depth color_depth, 215 enum signal_type signal, 216 uint32_t pixel_clock); 217 218 /* enables DP PHY output */ 219 void dce110_link_encoder_enable_dp_output( 220 struct link_encoder *enc, 221 const struct dc_link_settings *link_settings, 222 enum clock_source_id clock_source); 223 224 /* enables DP PHY output in MST mode */ 225 void dce110_link_encoder_enable_dp_mst_output( 226 struct link_encoder *enc, 227 const struct dc_link_settings *link_settings, 228 enum clock_source_id clock_source); 229 230 /* enables LVDS PHY output */ 231 void dce110_link_encoder_enable_lvds_output( 232 struct link_encoder *enc, 233 enum clock_source_id clock_source, 234 uint32_t pixel_clock); 235 236 /* disable PHY output */ 237 void dce110_link_encoder_disable_output( 238 struct link_encoder *enc, 239 enum signal_type signal); 240 241 /* set DP lane settings */ 242 void dce110_link_encoder_dp_set_lane_settings( 243 struct link_encoder *enc, 244 const struct link_training_settings *link_settings); 245 246 void dce110_link_encoder_dp_set_phy_pattern( 247 struct link_encoder *enc, 248 const struct encoder_set_dp_phy_pattern_param *param); 249 250 /* programs DP MST VC payload allocation */ 251 void dce110_link_encoder_update_mst_stream_allocation_table( 252 struct link_encoder *enc, 253 const struct link_mst_stream_allocation_table *table); 254 255 void dce110_link_encoder_connect_dig_be_to_fe( 256 struct link_encoder *enc, 257 enum engine_id engine, 258 bool connect); 259 260 void dce110_link_encoder_set_dp_phy_pattern_training_pattern( 261 struct link_encoder *enc, 262 uint32_t index); 263 264 void dce110_link_encoder_enable_hpd(struct link_encoder *enc); 265 266 void dce110_link_encoder_disable_hpd(struct link_encoder *enc); 267 268 void dce110_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 269 bool exit_link_training_required); 270 271 void dce110_psr_program_secondary_packet(struct link_encoder *enc, 272 unsigned int sdp_transmit_line_num_deadline); 273 274 bool dce110_is_dig_enabled(struct link_encoder *enc); 275 276 #endif /* __DC_LINK_ENCODER__DCE110_H__ */ 277
Indexes created Mon Sep 22 05:09:51 GMT 2025