1 /* $NetBSD: amdgpu_dce_stream_encoder.c,v 1.3 2021/12/19 11:23:26 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce_stream_encoder.c,v 1.3 2021/12/19 11:23:26 riastradh Exp $"); 30 31 #include <linux/delay.h> 32 33 #include "dc_bios_types.h" 34 #include "dce_stream_encoder.h" 35 #include "reg_helper.h" 36 #include "hw_shared.h" 37 38 #define DC_LOGGER \ 39 enc110->base.ctx->logger 40 41 42 #define REG(reg)\ 43 (enc110->regs->reg) 44 45 #undef FN 46 #define FN(reg_name, field_name) \ 47 enc110->se_shift->field_name, enc110->se_mask->field_name 48 49 #define VBI_LINE_0 0 50 #define DP_BLANK_MAX_RETRY 20 51 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000 52 53 #ifndef TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 54 #define TMDS_CNTL__TMDS_PIXEL_ENCODING_MASK 0x00000010L 55 #define TMDS_CNTL__TMDS_COLOR_FORMAT_MASK 0x00000300L 56 #define TMDS_CNTL__TMDS_PIXEL_ENCODING__SHIFT 0x00000004 57 #define TMDS_CNTL__TMDS_COLOR_FORMAT__SHIFT 0x00000008 58 #endif 59 60 enum { 61 DP_MST_UPDATE_MAX_RETRY = 50 62 }; 63 64 #define DCE110_SE(audio)\ 65 container_of(audio, struct dce110_stream_encoder, base) 66 67 #define CTX \ 68 enc110->base.ctx 69 70 static void dce110_update_generic_info_packet( 71 struct dce110_stream_encoder *enc110, 72 uint32_t packet_index, 73 const struct dc_info_packet *info_packet) 74 { 75 uint32_t regval __unused; 76 /* TODOFPGA Figure out a proper number for max_retries polling for lock 77 * use 50 for now. 78 */ 79 uint32_t max_retries = 50; 80 81 /*we need turn on clock before programming AFMT block*/ 82 if (REG(AFMT_CNTL)) 83 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 84 85 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 86 if (packet_index >= 8) 87 ASSERT(0); 88 89 /* poll dig_update_lock is not locked -> asic internal signal 90 * assume otg master lock will unlock it 91 */ 92 /* REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_LOCK_STATUS, 93 0, 10, max_retries);*/ 94 95 /* check if HW reading GSP memory */ 96 REG_WAIT(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT, 97 0, 10, max_retries); 98 99 /* HW does is not reading GSP memory not reading too long -> 100 * something wrong. clear GPS memory access and notify? 101 * hw SW is writing to GSP memory 102 */ 103 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, AFMT_GENERIC_CONFLICT_CLR, 1); 104 } 105 /* choose which generic packet to use */ 106 { 107 regval = REG_READ(AFMT_VBI_PACKET_CONTROL); 108 REG_UPDATE(AFMT_VBI_PACKET_CONTROL, 109 AFMT_GENERIC_INDEX, packet_index); 110 } 111 112 /* write generic packet header 113 * (4th byte is for GENERIC0 only) */ 114 { 115 REG_SET_4(AFMT_GENERIC_HDR, 0, 116 AFMT_GENERIC_HB0, info_packet->hb0, 117 AFMT_GENERIC_HB1, info_packet->hb1, 118 AFMT_GENERIC_HB2, info_packet->hb2, 119 AFMT_GENERIC_HB3, info_packet->hb3); 120 } 121 122 /* write generic packet contents 123 * (we never use last 4 bytes) 124 * there are 8 (0-7) mmDIG0_AFMT_GENERIC0_x registers */ 125 { 126 const uint32_t *content = 127 (const uint32_t *) &info_packet->sb[0]; 128 129 REG_WRITE(AFMT_GENERIC_0, *content++); 130 REG_WRITE(AFMT_GENERIC_1, *content++); 131 REG_WRITE(AFMT_GENERIC_2, *content++); 132 REG_WRITE(AFMT_GENERIC_3, *content++); 133 REG_WRITE(AFMT_GENERIC_4, *content++); 134 REG_WRITE(AFMT_GENERIC_5, *content++); 135 REG_WRITE(AFMT_GENERIC_6, *content++); 136 REG_WRITE(AFMT_GENERIC_7, *content); 137 } 138 139 if (!REG(AFMT_VBI_PACKET_CONTROL1)) { 140 /* force double-buffered packet update */ 141 REG_UPDATE_2(AFMT_VBI_PACKET_CONTROL, 142 AFMT_GENERIC0_UPDATE, (packet_index == 0), 143 AFMT_GENERIC2_UPDATE, (packet_index == 2)); 144 } 145 #if defined(CONFIG_DRM_AMD_DC_DCN) 146 if (REG(AFMT_VBI_PACKET_CONTROL1)) { 147 switch (packet_index) { 148 case 0: 149 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 150 AFMT_GENERIC0_FRAME_UPDATE, 1); 151 break; 152 case 1: 153 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 154 AFMT_GENERIC1_FRAME_UPDATE, 1); 155 break; 156 case 2: 157 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 158 AFMT_GENERIC2_FRAME_UPDATE, 1); 159 break; 160 case 3: 161 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 162 AFMT_GENERIC3_FRAME_UPDATE, 1); 163 break; 164 case 4: 165 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 166 AFMT_GENERIC4_FRAME_UPDATE, 1); 167 break; 168 case 5: 169 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 170 AFMT_GENERIC5_FRAME_UPDATE, 1); 171 break; 172 case 6: 173 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 174 AFMT_GENERIC6_FRAME_UPDATE, 1); 175 break; 176 case 7: 177 REG_UPDATE(AFMT_VBI_PACKET_CONTROL1, 178 AFMT_GENERIC7_FRAME_UPDATE, 1); 179 break; 180 default: 181 break; 182 } 183 } 184 #endif 185 } 186 187 static void dce110_update_hdmi_info_packet( 188 struct dce110_stream_encoder *enc110, 189 uint32_t packet_index, 190 const struct dc_info_packet *info_packet) 191 { 192 uint32_t cont, send, line; 193 194 if (info_packet->valid) { 195 dce110_update_generic_info_packet( 196 enc110, 197 packet_index, 198 info_packet); 199 200 /* enable transmission of packet(s) - 201 * packet transmission begins on the next frame */ 202 cont = 1; 203 /* send packet(s) every frame */ 204 send = 1; 205 /* select line number to send packets on */ 206 line = 2; 207 } else { 208 cont = 0; 209 send = 0; 210 line = 0; 211 } 212 213 /* choose which generic packet control to use */ 214 switch (packet_index) { 215 case 0: 216 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 217 HDMI_GENERIC0_CONT, cont, 218 HDMI_GENERIC0_SEND, send, 219 HDMI_GENERIC0_LINE, line); 220 break; 221 case 1: 222 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL0, 223 HDMI_GENERIC1_CONT, cont, 224 HDMI_GENERIC1_SEND, send, 225 HDMI_GENERIC1_LINE, line); 226 break; 227 case 2: 228 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 229 HDMI_GENERIC0_CONT, cont, 230 HDMI_GENERIC0_SEND, send, 231 HDMI_GENERIC0_LINE, line); 232 break; 233 case 3: 234 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL1, 235 HDMI_GENERIC1_CONT, cont, 236 HDMI_GENERIC1_SEND, send, 237 HDMI_GENERIC1_LINE, line); 238 break; 239 #if defined(CONFIG_DRM_AMD_DC_DCN) 240 case 4: 241 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 242 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 243 HDMI_GENERIC0_CONT, cont, 244 HDMI_GENERIC0_SEND, send, 245 HDMI_GENERIC0_LINE, line); 246 break; 247 case 5: 248 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 249 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL2, 250 HDMI_GENERIC1_CONT, cont, 251 HDMI_GENERIC1_SEND, send, 252 HDMI_GENERIC1_LINE, line); 253 break; 254 case 6: 255 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 256 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 257 HDMI_GENERIC0_CONT, cont, 258 HDMI_GENERIC0_SEND, send, 259 HDMI_GENERIC0_LINE, line); 260 break; 261 case 7: 262 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 263 REG_UPDATE_3(HDMI_GENERIC_PACKET_CONTROL3, 264 HDMI_GENERIC1_CONT, cont, 265 HDMI_GENERIC1_SEND, send, 266 HDMI_GENERIC1_LINE, line); 267 break; 268 #endif 269 default: 270 /* invalid HW packet index */ 271 DC_LOG_WARNING( 272 "Invalid HW packet index: %s()\n", 273 __func__); 274 return; 275 } 276 } 277 278 /* setup stream encoder in dp mode */ 279 static void dce110_stream_encoder_dp_set_stream_attribute( 280 struct stream_encoder *enc, 281 struct dc_crtc_timing *crtc_timing, 282 enum dc_color_space output_color_space, 283 bool use_vsc_sdp_for_colorimetry, 284 uint32_t enable_sdp_splitting) 285 { 286 #if defined(CONFIG_DRM_AMD_DC_DCN) 287 uint32_t h_active_start; 288 uint32_t v_active_start; 289 uint32_t misc0 = 0; 290 uint32_t misc1 = 0; 291 uint32_t h_blank; 292 uint32_t h_back_porch; 293 uint8_t synchronous_clock = 0; /* asynchronous mode */ 294 uint8_t colorimetry_bpc; 295 uint8_t dynamic_range_rgb = 0; /*full range*/ 296 uint8_t dynamic_range_ycbcr = 1; /*bt709*/ 297 #endif 298 299 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 300 struct dc_crtc_timing hw_crtc_timing = *crtc_timing; 301 if (hw_crtc_timing.flags.INTERLACE) { 302 /*the input timing is in VESA spec format with Interlace flag =1*/ 303 hw_crtc_timing.v_total /= 2; 304 hw_crtc_timing.v_border_top /= 2; 305 hw_crtc_timing.v_addressable /= 2; 306 hw_crtc_timing.v_border_bottom /= 2; 307 hw_crtc_timing.v_front_porch /= 2; 308 hw_crtc_timing.v_sync_width /= 2; 309 } 310 /* set pixel encoding */ 311 switch (hw_crtc_timing.pixel_encoding) { 312 case PIXEL_ENCODING_YCBCR422: 313 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 314 DP_PIXEL_ENCODING_TYPE_YCBCR422); 315 break; 316 case PIXEL_ENCODING_YCBCR444: 317 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 318 DP_PIXEL_ENCODING_TYPE_YCBCR444); 319 320 if (hw_crtc_timing.flags.Y_ONLY) 321 if (hw_crtc_timing.display_color_depth != COLOR_DEPTH_666) 322 /* HW testing only, no use case yet. 323 * Color depth of Y-only could be 324 * 8, 10, 12, 16 bits */ 325 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 326 DP_PIXEL_ENCODING_TYPE_Y_ONLY); 327 /* Note: DP_MSA_MISC1 bit 7 is the indicator 328 * of Y-only mode. 329 * This bit is set in HW if register 330 * DP_PIXEL_ENCODING is programmed to 0x4 */ 331 break; 332 case PIXEL_ENCODING_YCBCR420: 333 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 334 DP_PIXEL_ENCODING_TYPE_YCBCR420); 335 if (enc110->se_mask->DP_VID_M_DOUBLE_VALUE_EN) 336 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1); 337 338 #if defined(CONFIG_DRM_AMD_DC_DCN) 339 if (enc110->se_mask->DP_VID_N_MUL) 340 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1); 341 #endif 342 break; 343 default: 344 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_ENCODING, 345 DP_PIXEL_ENCODING_TYPE_RGB444); 346 break; 347 } 348 349 #if defined(CONFIG_DRM_AMD_DC_DCN) 350 if (REG(DP_MSA_MISC)) 351 misc1 = REG_READ(DP_MSA_MISC); 352 #endif 353 354 /* set color depth */ 355 356 switch (hw_crtc_timing.display_color_depth) { 357 case COLOR_DEPTH_666: 358 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 359 0); 360 break; 361 case COLOR_DEPTH_888: 362 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 363 DP_COMPONENT_PIXEL_DEPTH_8BPC); 364 break; 365 case COLOR_DEPTH_101010: 366 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 367 DP_COMPONENT_PIXEL_DEPTH_10BPC); 368 369 break; 370 case COLOR_DEPTH_121212: 371 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 372 DP_COMPONENT_PIXEL_DEPTH_12BPC); 373 break; 374 default: 375 REG_UPDATE(DP_PIXEL_FORMAT, DP_COMPONENT_DEPTH, 376 DP_COMPONENT_PIXEL_DEPTH_6BPC); 377 break; 378 } 379 380 /* set dynamic range and YCbCr range */ 381 382 383 #if defined(CONFIG_DRM_AMD_DC_DCN) 384 switch (hw_crtc_timing.display_color_depth) { 385 case COLOR_DEPTH_666: 386 colorimetry_bpc = 0; 387 break; 388 case COLOR_DEPTH_888: 389 colorimetry_bpc = 1; 390 break; 391 case COLOR_DEPTH_101010: 392 colorimetry_bpc = 2; 393 break; 394 case COLOR_DEPTH_121212: 395 colorimetry_bpc = 3; 396 break; 397 default: 398 colorimetry_bpc = 0; 399 break; 400 } 401 402 misc0 = misc0 | synchronous_clock; 403 misc0 = colorimetry_bpc << 5; 404 405 if (REG(DP_MSA_TIMING_PARAM1)) { 406 switch (output_color_space) { 407 case COLOR_SPACE_SRGB: 408 misc0 = misc0 | 0x0; 409 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 410 dynamic_range_rgb = 0; /*full range*/ 411 break; 412 case COLOR_SPACE_SRGB_LIMITED: 413 misc0 = misc0 | 0x8; /* bit3=1 */ 414 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 415 dynamic_range_rgb = 1; /*limited range*/ 416 break; 417 case COLOR_SPACE_YCBCR601: 418 case COLOR_SPACE_YCBCR601_LIMITED: 419 misc0 = misc0 | 0x8; /* bit3=1, bit4=0 */ 420 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 421 dynamic_range_ycbcr = 0; /*bt601*/ 422 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 423 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 424 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 425 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 426 break; 427 case COLOR_SPACE_YCBCR709: 428 case COLOR_SPACE_YCBCR709_LIMITED: 429 case COLOR_SPACE_YCBCR709_BLACK: 430 misc0 = misc0 | 0x18; /* bit3=1, bit4=1 */ 431 misc1 = misc1 & ~0x80; /* bit7 = 0*/ 432 dynamic_range_ycbcr = 1; /*bt709*/ 433 if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) 434 misc0 = misc0 | 0x2; /* bit2=0, bit1=1 */ 435 else if (hw_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR444) 436 misc0 = misc0 | 0x4; /* bit2=1, bit1=0 */ 437 break; 438 case COLOR_SPACE_2020_RGB_LIMITEDRANGE: 439 dynamic_range_rgb = 1; /*limited range*/ 440 break; 441 case COLOR_SPACE_2020_RGB_FULLRANGE: 442 case COLOR_SPACE_2020_YCBCR: 443 case COLOR_SPACE_XR_RGB: 444 case COLOR_SPACE_MSREF_SCRGB: 445 case COLOR_SPACE_ADOBERGB: 446 case COLOR_SPACE_DCIP3: 447 case COLOR_SPACE_XV_YCC_709: 448 case COLOR_SPACE_XV_YCC_601: 449 case COLOR_SPACE_DISPLAYNATIVE: 450 case COLOR_SPACE_DOLBYVISION: 451 case COLOR_SPACE_APPCTRL: 452 case COLOR_SPACE_CUSTOMPOINTS: 453 case COLOR_SPACE_UNKNOWN: 454 /* do nothing */ 455 break; 456 } 457 if (enc110->se_mask->DP_DYN_RANGE && enc110->se_mask->DP_YCBCR_RANGE) 458 REG_UPDATE_2( 459 DP_PIXEL_FORMAT, 460 DP_DYN_RANGE, dynamic_range_rgb, 461 DP_YCBCR_RANGE, dynamic_range_ycbcr); 462 463 #if defined(CONFIG_DRM_AMD_DC_DCN) 464 if (REG(DP_MSA_COLORIMETRY)) 465 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); 466 467 if (REG(DP_MSA_MISC)) 468 REG_WRITE(DP_MSA_MISC, misc1); /* MSA_MISC1 */ 469 470 /* dcn new register 471 * dc_crtc_timing is vesa dmt struct. data from edid 472 */ 473 if (REG(DP_MSA_TIMING_PARAM1)) 474 REG_SET_2(DP_MSA_TIMING_PARAM1, 0, 475 DP_MSA_HTOTAL, hw_crtc_timing.h_total, 476 DP_MSA_VTOTAL, hw_crtc_timing.v_total); 477 #endif 478 479 /* calcuate from vesa timing parameters 480 * h_active_start related to leading edge of sync 481 */ 482 483 h_blank = hw_crtc_timing.h_total - hw_crtc_timing.h_border_left - 484 hw_crtc_timing.h_addressable - hw_crtc_timing.h_border_right; 485 486 h_back_porch = h_blank - hw_crtc_timing.h_front_porch - 487 hw_crtc_timing.h_sync_width; 488 489 /* start at begining of left border */ 490 h_active_start = hw_crtc_timing.h_sync_width + h_back_porch; 491 492 493 v_active_start = hw_crtc_timing.v_total - hw_crtc_timing.v_border_top - 494 hw_crtc_timing.v_addressable - hw_crtc_timing.v_border_bottom - 495 hw_crtc_timing.v_front_porch; 496 497 498 #if defined(CONFIG_DRM_AMD_DC_DCN) 499 /* start at begining of left border */ 500 if (REG(DP_MSA_TIMING_PARAM2)) 501 REG_SET_2(DP_MSA_TIMING_PARAM2, 0, 502 DP_MSA_HSTART, h_active_start, 503 DP_MSA_VSTART, v_active_start); 504 505 if (REG(DP_MSA_TIMING_PARAM3)) 506 REG_SET_4(DP_MSA_TIMING_PARAM3, 0, 507 DP_MSA_HSYNCWIDTH, 508 hw_crtc_timing.h_sync_width, 509 DP_MSA_HSYNCPOLARITY, 510 !hw_crtc_timing.flags.HSYNC_POSITIVE_POLARITY, 511 DP_MSA_VSYNCWIDTH, 512 hw_crtc_timing.v_sync_width, 513 DP_MSA_VSYNCPOLARITY, 514 !hw_crtc_timing.flags.VSYNC_POSITIVE_POLARITY); 515 516 /* HWDITH include border or overscan */ 517 if (REG(DP_MSA_TIMING_PARAM4)) 518 REG_SET_2(DP_MSA_TIMING_PARAM4, 0, 519 DP_MSA_HWIDTH, hw_crtc_timing.h_border_left + 520 hw_crtc_timing.h_addressable + hw_crtc_timing.h_border_right, 521 DP_MSA_VHEIGHT, hw_crtc_timing.v_border_top + 522 hw_crtc_timing.v_addressable + hw_crtc_timing.v_border_bottom); 523 #endif 524 } 525 #endif 526 } 527 528 static void dce110_stream_encoder_set_stream_attribute_helper( 529 struct dce110_stream_encoder *enc110, 530 struct dc_crtc_timing *crtc_timing) 531 { 532 if (enc110->regs->TMDS_CNTL) { 533 switch (crtc_timing->pixel_encoding) { 534 case PIXEL_ENCODING_YCBCR422: 535 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 1); 536 break; 537 default: 538 REG_UPDATE(TMDS_CNTL, TMDS_PIXEL_ENCODING, 0); 539 break; 540 } 541 REG_UPDATE(TMDS_CNTL, TMDS_COLOR_FORMAT, 0); 542 } else if (enc110->regs->DIG_FE_CNTL) { 543 switch (crtc_timing->pixel_encoding) { 544 case PIXEL_ENCODING_YCBCR422: 545 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 1); 546 break; 547 default: 548 REG_UPDATE(DIG_FE_CNTL, TMDS_PIXEL_ENCODING, 0); 549 break; 550 } 551 REG_UPDATE(DIG_FE_CNTL, TMDS_COLOR_FORMAT, 0); 552 } 553 554 } 555 556 /* setup stream encoder in hdmi mode */ 557 static void dce110_stream_encoder_hdmi_set_stream_attribute( 558 struct stream_encoder *enc, 559 struct dc_crtc_timing *crtc_timing, 560 int actual_pix_clk_khz, 561 bool enable_audio) 562 { 563 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 564 struct bp_encoder_control cntl = {0}; 565 566 cntl.action = ENCODER_CONTROL_SETUP; 567 cntl.engine_id = enc110->base.id; 568 cntl.signal = SIGNAL_TYPE_HDMI_TYPE_A; 569 cntl.enable_dp_audio = enable_audio; 570 cntl.pixel_clock = actual_pix_clk_khz; 571 cntl.lanes_number = LANE_COUNT_FOUR; 572 573 if (enc110->base.bp->funcs->encoder_control( 574 enc110->base.bp, &cntl) != BP_RESULT_OK) 575 return; 576 577 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 578 579 /* setup HDMI engine */ 580 if (!enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 581 REG_UPDATE_3(HDMI_CONTROL, 582 HDMI_PACKET_GEN_VERSION, 1, 583 HDMI_KEEPOUT_MODE, 1, 584 HDMI_DEEP_COLOR_ENABLE, 0); 585 } else if (enc110->regs->DIG_FE_CNTL) { 586 REG_UPDATE_5(HDMI_CONTROL, 587 HDMI_PACKET_GEN_VERSION, 1, 588 HDMI_KEEPOUT_MODE, 1, 589 HDMI_DEEP_COLOR_ENABLE, 0, 590 HDMI_DATA_SCRAMBLE_EN, 0, 591 HDMI_CLOCK_CHANNEL_RATE, 0); 592 } 593 594 switch (crtc_timing->display_color_depth) { 595 case COLOR_DEPTH_888: 596 REG_UPDATE(HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0); 597 break; 598 case COLOR_DEPTH_101010: 599 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 600 REG_UPDATE_2(HDMI_CONTROL, 601 HDMI_DEEP_COLOR_DEPTH, 1, 602 HDMI_DEEP_COLOR_ENABLE, 0); 603 } else { 604 REG_UPDATE_2(HDMI_CONTROL, 605 HDMI_DEEP_COLOR_DEPTH, 1, 606 HDMI_DEEP_COLOR_ENABLE, 1); 607 } 608 break; 609 case COLOR_DEPTH_121212: 610 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR422) { 611 REG_UPDATE_2(HDMI_CONTROL, 612 HDMI_DEEP_COLOR_DEPTH, 2, 613 HDMI_DEEP_COLOR_ENABLE, 0); 614 } else { 615 REG_UPDATE_2(HDMI_CONTROL, 616 HDMI_DEEP_COLOR_DEPTH, 2, 617 HDMI_DEEP_COLOR_ENABLE, 1); 618 } 619 break; 620 case COLOR_DEPTH_161616: 621 REG_UPDATE_2(HDMI_CONTROL, 622 HDMI_DEEP_COLOR_DEPTH, 3, 623 HDMI_DEEP_COLOR_ENABLE, 1); 624 break; 625 default: 626 break; 627 } 628 629 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) { 630 if (actual_pix_clk_khz >= HDMI_CLOCK_CHANNEL_RATE_MORE_340M) { 631 /* enable HDMI data scrambler 632 * HDMI_CLOCK_CHANNEL_RATE_MORE_340M 633 * Clock channel frequency is 1/4 of character rate. 634 */ 635 REG_UPDATE_2(HDMI_CONTROL, 636 HDMI_DATA_SCRAMBLE_EN, 1, 637 HDMI_CLOCK_CHANNEL_RATE, 1); 638 } else if (crtc_timing->flags.LTE_340MCSC_SCRAMBLE) { 639 640 /* TODO: New feature for DCE11, still need to implement */ 641 642 /* enable HDMI data scrambler 643 * HDMI_CLOCK_CHANNEL_FREQ_EQUAL_TO_CHAR_RATE 644 * Clock channel frequency is the same 645 * as character rate 646 */ 647 REG_UPDATE_2(HDMI_CONTROL, 648 HDMI_DATA_SCRAMBLE_EN, 1, 649 HDMI_CLOCK_CHANNEL_RATE, 0); 650 } 651 } 652 653 REG_UPDATE_3(HDMI_VBI_PACKET_CONTROL, 654 HDMI_GC_CONT, 1, 655 HDMI_GC_SEND, 1, 656 HDMI_NULL_SEND, 1); 657 658 /* following belongs to audio */ 659 REG_UPDATE(HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1); 660 661 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 662 663 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 664 VBI_LINE_0 + 2); 665 666 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, 0); 667 668 } 669 670 /* setup stream encoder in dvi mode */ 671 static void dce110_stream_encoder_dvi_set_stream_attribute( 672 struct stream_encoder *enc, 673 struct dc_crtc_timing *crtc_timing, 674 bool is_dual_link) 675 { 676 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 677 struct bp_encoder_control cntl = {0}; 678 679 cntl.action = ENCODER_CONTROL_SETUP; 680 cntl.engine_id = enc110->base.id; 681 cntl.signal = is_dual_link ? 682 SIGNAL_TYPE_DVI_DUAL_LINK : SIGNAL_TYPE_DVI_SINGLE_LINK; 683 cntl.enable_dp_audio = false; 684 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 685 cntl.lanes_number = (is_dual_link) ? LANE_COUNT_EIGHT : LANE_COUNT_FOUR; 686 687 if (enc110->base.bp->funcs->encoder_control( 688 enc110->base.bp, &cntl) != BP_RESULT_OK) 689 return; 690 691 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 692 ASSERT(crtc_timing->display_color_depth == COLOR_DEPTH_888); 693 dce110_stream_encoder_set_stream_attribute_helper(enc110, crtc_timing); 694 } 695 696 /* setup stream encoder in LVDS mode */ 697 static void dce110_stream_encoder_lvds_set_stream_attribute( 698 struct stream_encoder *enc, 699 struct dc_crtc_timing *crtc_timing) 700 { 701 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 702 struct bp_encoder_control cntl = {0}; 703 704 cntl.action = ENCODER_CONTROL_SETUP; 705 cntl.engine_id = enc110->base.id; 706 cntl.signal = SIGNAL_TYPE_LVDS; 707 cntl.enable_dp_audio = false; 708 cntl.pixel_clock = crtc_timing->pix_clk_100hz / 10; 709 cntl.lanes_number = LANE_COUNT_FOUR; 710 711 if (enc110->base.bp->funcs->encoder_control( 712 enc110->base.bp, &cntl) != BP_RESULT_OK) 713 return; 714 715 ASSERT(crtc_timing->pixel_encoding == PIXEL_ENCODING_RGB); 716 } 717 718 static void dce110_stream_encoder_set_mst_bandwidth( 719 struct stream_encoder *enc, 720 struct fixed31_32 avg_time_slots_per_mtp) 721 { 722 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 723 uint32_t x = dc_fixpt_floor( 724 avg_time_slots_per_mtp); 725 uint32_t y = dc_fixpt_ceil( 726 dc_fixpt_shl( 727 dc_fixpt_sub_int( 728 avg_time_slots_per_mtp, 729 x), 730 26)); 731 732 { 733 REG_SET_2(DP_MSE_RATE_CNTL, 0, 734 DP_MSE_RATE_X, x, 735 DP_MSE_RATE_Y, y); 736 } 737 738 /* wait for update to be completed on the link */ 739 /* i.e. DP_MSE_RATE_UPDATE_PENDING field (read only) */ 740 /* is reset to 0 (not pending) */ 741 REG_WAIT(DP_MSE_RATE_UPDATE, DP_MSE_RATE_UPDATE_PENDING, 742 0, 743 10, DP_MST_UPDATE_MAX_RETRY); 744 } 745 746 static void dce110_stream_encoder_update_hdmi_info_packets( 747 struct stream_encoder *enc, 748 const struct encoder_info_frame *info_frame) 749 { 750 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 751 752 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 753 enc110->se_mask->HDMI_AVI_INFO_SEND) { 754 755 if (info_frame->avi.valid) { 756 const uint32_t *content = 757 (const uint32_t *) &info_frame->avi.sb[0]; 758 /*we need turn on clock before programming AFMT block*/ 759 if (REG(AFMT_CNTL)) 760 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, 1); 761 762 REG_WRITE(AFMT_AVI_INFO0, content[0]); 763 764 REG_WRITE(AFMT_AVI_INFO1, content[1]); 765 766 REG_WRITE(AFMT_AVI_INFO2, content[2]); 767 768 REG_WRITE(AFMT_AVI_INFO3, content[3]); 769 770 REG_UPDATE(AFMT_AVI_INFO3, AFMT_AVI_INFO_VERSION, 771 info_frame->avi.hb1); 772 773 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 774 HDMI_AVI_INFO_SEND, 1, 775 HDMI_AVI_INFO_CONT, 1); 776 777 REG_UPDATE(HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 778 VBI_LINE_0 + 2); 779 780 } else { 781 REG_UPDATE_2(HDMI_INFOFRAME_CONTROL0, 782 HDMI_AVI_INFO_SEND, 0, 783 HDMI_AVI_INFO_CONT, 0); 784 } 785 } 786 787 if (enc110->se_mask->HDMI_AVI_INFO_CONT && 788 enc110->se_mask->HDMI_AVI_INFO_SEND) { 789 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->vendor); 790 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->gamut); 791 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->spd); 792 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->hdrsmd); 793 } 794 795 #if defined(CONFIG_DRM_AMD_DC_DCN) 796 if (enc110->se_mask->HDMI_DB_DISABLE) { 797 /* for bring up, disable dp double TODO */ 798 if (REG(HDMI_DB_CONTROL)) 799 REG_UPDATE(HDMI_DB_CONTROL, HDMI_DB_DISABLE, 1); 800 801 dce110_update_hdmi_info_packet(enc110, 0, &info_frame->avi); 802 dce110_update_hdmi_info_packet(enc110, 1, &info_frame->vendor); 803 dce110_update_hdmi_info_packet(enc110, 2, &info_frame->gamut); 804 dce110_update_hdmi_info_packet(enc110, 3, &info_frame->spd); 805 dce110_update_hdmi_info_packet(enc110, 4, &info_frame->hdrsmd); 806 } 807 #endif 808 } 809 810 static void dce110_stream_encoder_stop_hdmi_info_packets( 811 struct stream_encoder *enc) 812 { 813 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 814 815 /* stop generic packets 0 & 1 on HDMI */ 816 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL0, 0, 817 HDMI_GENERIC1_CONT, 0, 818 HDMI_GENERIC1_LINE, 0, 819 HDMI_GENERIC1_SEND, 0, 820 HDMI_GENERIC0_CONT, 0, 821 HDMI_GENERIC0_LINE, 0, 822 HDMI_GENERIC0_SEND, 0); 823 824 /* stop generic packets 2 & 3 on HDMI */ 825 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL1, 0, 826 HDMI_GENERIC0_CONT, 0, 827 HDMI_GENERIC0_LINE, 0, 828 HDMI_GENERIC0_SEND, 0, 829 HDMI_GENERIC1_CONT, 0, 830 HDMI_GENERIC1_LINE, 0, 831 HDMI_GENERIC1_SEND, 0); 832 833 #if defined(CONFIG_DRM_AMD_DC_DCN) 834 /* stop generic packets 2 & 3 on HDMI */ 835 if (REG(HDMI_GENERIC_PACKET_CONTROL2)) 836 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL2, 0, 837 HDMI_GENERIC0_CONT, 0, 838 HDMI_GENERIC0_LINE, 0, 839 HDMI_GENERIC0_SEND, 0, 840 HDMI_GENERIC1_CONT, 0, 841 HDMI_GENERIC1_LINE, 0, 842 HDMI_GENERIC1_SEND, 0); 843 844 if (REG(HDMI_GENERIC_PACKET_CONTROL3)) 845 REG_SET_6(HDMI_GENERIC_PACKET_CONTROL3, 0, 846 HDMI_GENERIC0_CONT, 0, 847 HDMI_GENERIC0_LINE, 0, 848 HDMI_GENERIC0_SEND, 0, 849 HDMI_GENERIC1_CONT, 0, 850 HDMI_GENERIC1_LINE, 0, 851 HDMI_GENERIC1_SEND, 0); 852 #endif 853 } 854 855 static void dce110_stream_encoder_update_dp_info_packets( 856 struct stream_encoder *enc, 857 const struct encoder_info_frame *info_frame) 858 { 859 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 860 uint32_t value = 0; 861 862 if (info_frame->vsc.valid) 863 dce110_update_generic_info_packet( 864 enc110, 865 0, /* packetIndex */ 866 &info_frame->vsc); 867 868 if (info_frame->spd.valid) 869 dce110_update_generic_info_packet( 870 enc110, 871 2, /* packetIndex */ 872 &info_frame->spd); 873 874 if (info_frame->hdrsmd.valid) 875 dce110_update_generic_info_packet( 876 enc110, 877 3, /* packetIndex */ 878 &info_frame->hdrsmd); 879 880 /* enable/disable transmission of packet(s). 881 * If enabled, packet transmission begins on the next frame 882 */ 883 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); 884 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP2_ENABLE, info_frame->spd.valid); 885 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP3_ENABLE, info_frame->hdrsmd.valid); 886 887 /* This bit is the master enable bit. 888 * When enabling secondary stream engine, 889 * this master bit must also be set. 890 * This register shared with audio info frame. 891 * Therefore we need to enable master bit 892 * if at least on of the fields is not 0 893 */ 894 value = REG_READ(DP_SEC_CNTL); 895 if (value) 896 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 897 } 898 899 static void dce110_stream_encoder_stop_dp_info_packets( 900 struct stream_encoder *enc) 901 { 902 /* stop generic packets on DP */ 903 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 904 uint32_t value = 0; 905 906 if (enc110->se_mask->DP_SEC_AVI_ENABLE) { 907 REG_SET_7(DP_SEC_CNTL, 0, 908 DP_SEC_GSP0_ENABLE, 0, 909 DP_SEC_GSP1_ENABLE, 0, 910 DP_SEC_GSP2_ENABLE, 0, 911 DP_SEC_GSP3_ENABLE, 0, 912 DP_SEC_AVI_ENABLE, 0, 913 DP_SEC_MPG_ENABLE, 0, 914 DP_SEC_STREAM_ENABLE, 0); 915 } 916 917 /* this register shared with audio info frame. 918 * therefore we need to keep master enabled 919 * if at least one of the fields is not 0 */ 920 value = REG_READ(DP_SEC_CNTL); 921 if (value) 922 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 923 924 } 925 926 static void dce110_stream_encoder_dp_blank( 927 struct stream_encoder *enc) 928 { 929 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 930 uint32_t reg1 = 0; 931 uint32_t max_retries = DP_BLANK_MAX_RETRY * 10; 932 933 /* Note: For CZ, we are changing driver default to disable 934 * stream deferred to next VBLANK. If results are positive, we 935 * will make the same change to all DCE versions. There are a 936 * handful of panels that cannot handle disable stream at 937 * HBLANK and will result in a white line flash across the 938 * screen on stream disable. */ 939 REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); 940 if ((reg1 & 0x1) == 0) 941 /*stream not enabled*/ 942 return; 943 /* Specify the video stream disable point 944 * (2 = start of the next vertical blank) */ 945 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_DIS_DEFER, 2); 946 /* Larger delay to wait until VBLANK - use max retry of 947 * 10us*3000=30ms. This covers 16.6ms of typical 60 Hz mode + 948 * a little more because we may not trust delay accuracy. 949 */ 950 max_retries = DP_BLANK_MAX_RETRY * 150; 951 952 /* disable DP stream */ 953 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 954 955 /* the encoder stops sending the video stream 956 * at the start of the vertical blanking. 957 * Poll for DP_VID_STREAM_STATUS == 0 958 */ 959 960 REG_WAIT(DP_VID_STREAM_CNTL, DP_VID_STREAM_STATUS, 961 0, 962 10, max_retries); 963 964 /* Tell the DP encoder to ignore timing from CRTC, must be done after 965 * the polling. If we set DP_STEER_FIFO_RESET before DP stream blank is 966 * complete, stream status will be stuck in video stream enabled state, 967 * i.e. DP_VID_STREAM_STATUS stuck at 1. 968 */ 969 970 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, true); 971 } 972 973 /* output video stream to link encoder */ 974 static void dce110_stream_encoder_dp_unblank( 975 struct stream_encoder *enc, 976 const struct encoder_unblank_param *param) 977 { 978 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 979 980 if (param->link_settings.link_rate != LINK_RATE_UNKNOWN) { 981 uint32_t n_vid = 0x8000; 982 uint32_t m_vid; 983 984 /* M / N = Fstream / Flink 985 * m_vid / n_vid = pixel rate / link rate 986 */ 987 988 uint64_t m_vid_l = n_vid; 989 990 m_vid_l *= param->timing.pix_clk_100hz / 10; 991 m_vid_l = div_u64(m_vid_l, 992 param->link_settings.link_rate 993 * LINK_RATE_REF_FREQ_IN_KHZ); 994 995 m_vid = (uint32_t) m_vid_l; 996 997 /* enable auto measurement */ 998 999 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0); 1000 1001 /* auto measurement need 1 full 0x8000 symbol cycle to kick in, 1002 * therefore program initial value for Mvid and Nvid 1003 */ 1004 1005 REG_UPDATE(DP_VID_N, DP_VID_N, n_vid); 1006 1007 REG_UPDATE(DP_VID_M, DP_VID_M, m_vid); 1008 1009 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1); 1010 } 1011 1012 /* set DIG_START to 0x1 to resync FIFO */ 1013 1014 REG_UPDATE(DIG_FE_CNTL, DIG_START, 1); 1015 1016 /* switch DP encoder to CRTC data */ 1017 1018 REG_UPDATE(DP_STEER_FIFO, DP_STEER_FIFO_RESET, 0); 1019 1020 /* wait 100us for DIG/DP logic to prime 1021 * (i.e. a few video lines) 1022 */ 1023 udelay(100); 1024 1025 /* the hardware would start sending video at the start of the next DP 1026 * frame (i.e. rising edge of the vblank). 1027 * NOTE: We used to program DP_VID_STREAM_DIS_DEFER = 2 here, but this 1028 * register has no effect on enable transition! HW always guarantees 1029 * VID_STREAM enable at start of next frame, and this is not 1030 * programmable 1031 */ 1032 1033 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, true); 1034 } 1035 1036 static void dce110_stream_encoder_set_avmute( 1037 struct stream_encoder *enc, 1038 bool enable) 1039 { 1040 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1041 unsigned int value = enable ? 1 : 0; 1042 1043 REG_UPDATE(HDMI_GC, HDMI_GC_AVMUTE, value); 1044 } 1045 1046 1047 static void dce110_reset_hdmi_stream_attribute( 1048 struct stream_encoder *enc) 1049 { 1050 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1051 if (enc110->se_mask->HDMI_DATA_SCRAMBLE_EN) 1052 REG_UPDATE_5(HDMI_CONTROL, 1053 HDMI_PACKET_GEN_VERSION, 1, 1054 HDMI_KEEPOUT_MODE, 1, 1055 HDMI_DEEP_COLOR_ENABLE, 0, 1056 HDMI_DATA_SCRAMBLE_EN, 0, 1057 HDMI_CLOCK_CHANNEL_RATE, 0); 1058 else 1059 REG_UPDATE_3(HDMI_CONTROL, 1060 HDMI_PACKET_GEN_VERSION, 1, 1061 HDMI_KEEPOUT_MODE, 1, 1062 HDMI_DEEP_COLOR_ENABLE, 0); 1063 } 1064 1065 #define DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT 0x8000 1066 #define DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC 1 1067 1068 #include "include/audio_types.h" 1069 1070 /** 1071 * speakersToChannels 1072 * 1073 * @brief 1074 * translate speakers to channels 1075 * 1076 * FL - Front Left 1077 * FR - Front Right 1078 * RL - Rear Left 1079 * RR - Rear Right 1080 * RC - Rear Center 1081 * FC - Front Center 1082 * FLC - Front Left Center 1083 * FRC - Front Right Center 1084 * RLC - Rear Left Center 1085 * RRC - Rear Right Center 1086 * LFE - Low Freq Effect 1087 * 1088 * FC 1089 * FLC FRC 1090 * FL FR 1091 * 1092 * LFE 1093 * () 1094 * 1095 * 1096 * RL RR 1097 * RLC RRC 1098 * RC 1099 * 1100 * ch 8 7 6 5 4 3 2 1 1101 * 0b00000011 - - - - - - FR FL 1102 * 0b00000111 - - - - - LFE FR FL 1103 * 0b00001011 - - - - FC - FR FL 1104 * 0b00001111 - - - - FC LFE FR FL 1105 * 0b00010011 - - - RC - - FR FL 1106 * 0b00010111 - - - RC - LFE FR FL 1107 * 0b00011011 - - - RC FC - FR FL 1108 * 0b00011111 - - - RC FC LFE FR FL 1109 * 0b00110011 - - RR RL - - FR FL 1110 * 0b00110111 - - RR RL - LFE FR FL 1111 * 0b00111011 - - RR RL FC - FR FL 1112 * 0b00111111 - - RR RL FC LFE FR FL 1113 * 0b01110011 - RC RR RL - - FR FL 1114 * 0b01110111 - RC RR RL - LFE FR FL 1115 * 0b01111011 - RC RR RL FC - FR FL 1116 * 0b01111111 - RC RR RL FC LFE FR FL 1117 * 0b11110011 RRC RLC RR RL - - FR FL 1118 * 0b11110111 RRC RLC RR RL - LFE FR FL 1119 * 0b11111011 RRC RLC RR RL FC - FR FL 1120 * 0b11111111 RRC RLC RR RL FC LFE FR FL 1121 * 0b11000011 FRC FLC - - - - FR FL 1122 * 0b11000111 FRC FLC - - - LFE FR FL 1123 * 0b11001011 FRC FLC - - FC - FR FL 1124 * 0b11001111 FRC FLC - - FC LFE FR FL 1125 * 0b11010011 FRC FLC - RC - - FR FL 1126 * 0b11010111 FRC FLC - RC - LFE FR FL 1127 * 0b11011011 FRC FLC - RC FC - FR FL 1128 * 0b11011111 FRC FLC - RC FC LFE FR FL 1129 * 0b11110011 FRC FLC RR RL - - FR FL 1130 * 0b11110111 FRC FLC RR RL - LFE FR FL 1131 * 0b11111011 FRC FLC RR RL FC - FR FL 1132 * 0b11111111 FRC FLC RR RL FC LFE FR FL 1133 * 1134 * @param 1135 * speakers - speaker information as it comes from CEA audio block 1136 */ 1137 /* translate speakers to channels */ 1138 1139 union audio_cea_channels { 1140 uint8_t all; 1141 struct audio_cea_channels_bits { 1142 uint32_t FL:1; 1143 uint32_t FR:1; 1144 uint32_t LFE:1; 1145 uint32_t FC:1; 1146 uint32_t RL_RC:1; 1147 uint32_t RR:1; 1148 uint32_t RC_RLC_FLC:1; 1149 uint32_t RRC_FRC:1; 1150 } channels; 1151 }; 1152 1153 /* 25.2MHz/1.001*/ 1154 /* 25.2MHz/1.001*/ 1155 /* 25.2MHz*/ 1156 /* 27MHz */ 1157 /* 27MHz*1.001*/ 1158 /* 27MHz*1.001*/ 1159 /* 54MHz*/ 1160 /* 54MHz*1.001*/ 1161 /* 74.25MHz/1.001*/ 1162 /* 74.25MHz*/ 1163 /* 148.5MHz/1.001*/ 1164 /* 148.5MHz*/ 1165 1166 static const struct audio_clock_info audio_clock_info_table[16] = { 1167 {2517, 4576, 28125, 7007, 31250, 6864, 28125}, 1168 {2518, 4576, 28125, 7007, 31250, 6864, 28125}, 1169 {2520, 4096, 25200, 6272, 28000, 6144, 25200}, 1170 {2700, 4096, 27000, 6272, 30000, 6144, 27000}, 1171 {2702, 4096, 27027, 6272, 30030, 6144, 27027}, 1172 {2703, 4096, 27027, 6272, 30030, 6144, 27027}, 1173 {5400, 4096, 54000, 6272, 60000, 6144, 54000}, 1174 {5405, 4096, 54054, 6272, 60060, 6144, 54054}, 1175 {7417, 11648, 210937, 17836, 234375, 11648, 140625}, 1176 {7425, 4096, 74250, 6272, 82500, 6144, 74250}, 1177 {14835, 11648, 421875, 8918, 234375, 5824, 140625}, 1178 {14850, 4096, 148500, 6272, 165000, 6144, 148500}, 1179 {29670, 5824, 421875, 4459, 234375, 5824, 281250}, 1180 {29700, 3072, 222750, 4704, 247500, 5120, 247500}, 1181 {59340, 5824, 843750, 8918, 937500, 5824, 562500}, 1182 {59400, 3072, 445500, 9408, 990000, 6144, 594000} 1183 }; 1184 1185 static const struct audio_clock_info audio_clock_info_table_36bpc[14] = { 1186 {2517, 9152, 84375, 7007, 48875, 9152, 56250}, 1187 {2518, 9152, 84375, 7007, 48875, 9152, 56250}, 1188 {2520, 4096, 37800, 6272, 42000, 6144, 37800}, 1189 {2700, 4096, 40500, 6272, 45000, 6144, 40500}, 1190 {2702, 8192, 81081, 6272, 45045, 8192, 54054}, 1191 {2703, 8192, 81081, 6272, 45045, 8192, 54054}, 1192 {5400, 4096, 81000, 6272, 90000, 6144, 81000}, 1193 {5405, 4096, 81081, 6272, 90090, 6144, 81081}, 1194 {7417, 11648, 316406, 17836, 351562, 11648, 210937}, 1195 {7425, 4096, 111375, 6272, 123750, 6144, 111375}, 1196 {14835, 11648, 632812, 17836, 703125, 11648, 421875}, 1197 {14850, 4096, 222750, 6272, 247500, 6144, 222750}, 1198 {29670, 5824, 632812, 8918, 703125, 5824, 421875}, 1199 {29700, 4096, 445500, 4704, 371250, 5120, 371250} 1200 }; 1201 1202 static const struct audio_clock_info audio_clock_info_table_48bpc[14] = { 1203 {2517, 4576, 56250, 7007, 62500, 6864, 56250}, 1204 {2518, 4576, 56250, 7007, 62500, 6864, 56250}, 1205 {2520, 4096, 50400, 6272, 56000, 6144, 50400}, 1206 {2700, 4096, 54000, 6272, 60000, 6144, 54000}, 1207 {2702, 4096, 54054, 6267, 60060, 8192, 54054}, 1208 {2703, 4096, 54054, 6272, 60060, 8192, 54054}, 1209 {5400, 4096, 108000, 6272, 120000, 6144, 108000}, 1210 {5405, 4096, 108108, 6272, 120120, 6144, 108108}, 1211 {7417, 11648, 421875, 17836, 468750, 11648, 281250}, 1212 {7425, 4096, 148500, 6272, 165000, 6144, 148500}, 1213 {14835, 11648, 843750, 8918, 468750, 11648, 281250}, 1214 {14850, 4096, 297000, 6272, 330000, 6144, 297000}, 1215 {29670, 5824, 843750, 4459, 468750, 5824, 562500}, 1216 {29700, 3072, 445500, 4704, 495000, 5120, 495000} 1217 1218 1219 }; 1220 1221 static union audio_cea_channels speakers_to_channels( 1222 struct audio_speaker_flags speaker_flags) 1223 { 1224 union audio_cea_channels cea_channels = {0}; 1225 1226 /* these are one to one */ 1227 cea_channels.channels.FL = speaker_flags.FL_FR; 1228 cea_channels.channels.FR = speaker_flags.FL_FR; 1229 cea_channels.channels.LFE = speaker_flags.LFE; 1230 cea_channels.channels.FC = speaker_flags.FC; 1231 1232 /* if Rear Left and Right exist move RC speaker to channel 7 1233 * otherwise to channel 5 1234 */ 1235 if (speaker_flags.RL_RR) { 1236 cea_channels.channels.RL_RC = speaker_flags.RL_RR; 1237 cea_channels.channels.RR = speaker_flags.RL_RR; 1238 cea_channels.channels.RC_RLC_FLC = speaker_flags.RC; 1239 } else { 1240 cea_channels.channels.RL_RC = speaker_flags.RC; 1241 } 1242 1243 /* FRONT Left Right Center and REAR Left Right Center are exclusive */ 1244 if (speaker_flags.FLC_FRC) { 1245 cea_channels.channels.RC_RLC_FLC = speaker_flags.FLC_FRC; 1246 cea_channels.channels.RRC_FRC = speaker_flags.FLC_FRC; 1247 } else { 1248 cea_channels.channels.RC_RLC_FLC = speaker_flags.RLC_RRC; 1249 cea_channels.channels.RRC_FRC = speaker_flags.RLC_RRC; 1250 } 1251 1252 return cea_channels; 1253 } 1254 1255 static uint32_t calc_max_audio_packets_per_line( 1256 const struct audio_crtc_info *crtc_info) 1257 { 1258 uint32_t max_packets_per_line; 1259 1260 max_packets_per_line = 1261 crtc_info->h_total - crtc_info->h_active; 1262 1263 if (crtc_info->pixel_repetition) 1264 max_packets_per_line *= crtc_info->pixel_repetition; 1265 1266 /* for other hdmi features */ 1267 max_packets_per_line -= 58; 1268 /* for Control Period */ 1269 max_packets_per_line -= 16; 1270 /* Number of Audio Packets per Line */ 1271 max_packets_per_line /= 32; 1272 1273 return max_packets_per_line; 1274 } 1275 1276 static void get_audio_clock_info( 1277 enum dc_color_depth color_depth, 1278 uint32_t crtc_pixel_clock_100Hz, 1279 uint32_t actual_pixel_clock_100Hz, 1280 struct audio_clock_info *audio_clock_info) 1281 { 1282 const struct audio_clock_info *clock_info; 1283 uint32_t index; 1284 uint32_t crtc_pixel_clock_in_10khz = crtc_pixel_clock_100Hz / 100; 1285 uint32_t audio_array_size; 1286 1287 switch (color_depth) { 1288 case COLOR_DEPTH_161616: 1289 clock_info = audio_clock_info_table_48bpc; 1290 audio_array_size = ARRAY_SIZE( 1291 audio_clock_info_table_48bpc); 1292 break; 1293 case COLOR_DEPTH_121212: 1294 clock_info = audio_clock_info_table_36bpc; 1295 audio_array_size = ARRAY_SIZE( 1296 audio_clock_info_table_36bpc); 1297 break; 1298 default: 1299 clock_info = audio_clock_info_table; 1300 audio_array_size = ARRAY_SIZE( 1301 audio_clock_info_table); 1302 break; 1303 } 1304 1305 if (clock_info != NULL) { 1306 /* search for exact pixel clock in table */ 1307 for (index = 0; index < audio_array_size; index++) { 1308 if (clock_info[index].pixel_clock_in_10khz > 1309 crtc_pixel_clock_in_10khz) 1310 break; /* not match */ 1311 else if (clock_info[index].pixel_clock_in_10khz == 1312 crtc_pixel_clock_in_10khz) { 1313 /* match found */ 1314 *audio_clock_info = clock_info[index]; 1315 return; 1316 } 1317 } 1318 } 1319 1320 /* not found */ 1321 if (actual_pixel_clock_100Hz == 0) 1322 actual_pixel_clock_100Hz = crtc_pixel_clock_100Hz; 1323 1324 /* See HDMI spec the table entry under 1325 * pixel clock of "Other". */ 1326 audio_clock_info->pixel_clock_in_10khz = 1327 actual_pixel_clock_100Hz / 100; 1328 audio_clock_info->cts_32khz = actual_pixel_clock_100Hz / 10; 1329 audio_clock_info->cts_44khz = actual_pixel_clock_100Hz / 10; 1330 audio_clock_info->cts_48khz = actual_pixel_clock_100Hz / 10; 1331 1332 audio_clock_info->n_32khz = 4096; 1333 audio_clock_info->n_44khz = 6272; 1334 audio_clock_info->n_48khz = 6144; 1335 } 1336 1337 static void dce110_se_audio_setup( 1338 struct stream_encoder *enc, 1339 unsigned int az_inst, 1340 struct audio_info *audio_info) 1341 { 1342 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1343 1344 uint32_t speakers __unused = 0; 1345 uint32_t channels = 0; 1346 1347 ASSERT(audio_info); 1348 if (audio_info == NULL) 1349 /* This should not happen.it does so we don't get BSOD*/ 1350 return; 1351 1352 speakers = audio_info->flags.info.ALLSPEAKERS; 1353 channels = speakers_to_channels(audio_info->flags.speaker_flags).all; 1354 1355 /* setup the audio stream source select (audio -> dig mapping) */ 1356 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); 1357 1358 /* Channel allocation */ 1359 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_CHANNEL_ENABLE, channels); 1360 } 1361 1362 static void dce110_se_setup_hdmi_audio( 1363 struct stream_encoder *enc, 1364 const struct audio_crtc_info *crtc_info) 1365 { 1366 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1367 1368 struct audio_clock_info audio_clock_info = {0}; 1369 uint32_t max_packets_per_line; 1370 1371 /* For now still do calculation, although this field is ignored when 1372 above HDMI_PACKET_GEN_VERSION set to 1 */ 1373 max_packets_per_line = calc_max_audio_packets_per_line(crtc_info); 1374 1375 /* HDMI_AUDIO_PACKET_CONTROL */ 1376 REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL, 1377 HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line, 1378 HDMI_AUDIO_DELAY_EN, 1); 1379 1380 /* AFMT_AUDIO_PACKET_CONTROL */ 1381 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1382 1383 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1384 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1385 AFMT_AUDIO_LAYOUT_OVRD, 0, 1386 AFMT_60958_OSF_OVRD, 0); 1387 1388 /* HDMI_ACR_PACKET_CONTROL */ 1389 REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, 1390 HDMI_ACR_AUTO_SEND, 1, 1391 HDMI_ACR_SOURCE, 0, 1392 HDMI_ACR_AUDIO_PRIORITY, 0); 1393 1394 /* Program audio clock sample/regeneration parameters */ 1395 get_audio_clock_info(crtc_info->color_depth, 1396 crtc_info->requested_pixel_clock_100Hz, 1397 crtc_info->calculated_pixel_clock_100Hz, 1398 &audio_clock_info); 1399 DC_LOG_HW_AUDIO( 1400 "\n%s:Input::requested_pixel_clock_100Hz = %d" \ 1401 "calculated_pixel_clock_100Hz = %d \n", __func__, \ 1402 crtc_info->requested_pixel_clock_100Hz, \ 1403 crtc_info->calculated_pixel_clock_100Hz); 1404 1405 /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */ 1406 REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz); 1407 1408 /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */ 1409 REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz); 1410 1411 /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */ 1412 REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz); 1413 1414 /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */ 1415 REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz); 1416 1417 /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */ 1418 REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz); 1419 1420 /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */ 1421 REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz); 1422 1423 /* Video driver cannot know in advance which sample rate will 1424 be used by HD Audio driver 1425 HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is 1426 programmed below in interruppt callback */ 1427 1428 /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK & 1429 AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1430 REG_UPDATE_2(AFMT_60958_0, 1431 AFMT_60958_CS_CHANNEL_NUMBER_L, 1, 1432 AFMT_60958_CS_CLOCK_ACCURACY, 0); 1433 1434 /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */ 1435 REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2); 1436 1437 /*AFMT_60958_2 now keep this settings until 1438 * Programming guide comes out*/ 1439 REG_UPDATE_6(AFMT_60958_2, 1440 AFMT_60958_CS_CHANNEL_NUMBER_2, 3, 1441 AFMT_60958_CS_CHANNEL_NUMBER_3, 4, 1442 AFMT_60958_CS_CHANNEL_NUMBER_4, 5, 1443 AFMT_60958_CS_CHANNEL_NUMBER_5, 6, 1444 AFMT_60958_CS_CHANNEL_NUMBER_6, 7, 1445 AFMT_60958_CS_CHANNEL_NUMBER_7, 8); 1446 } 1447 1448 static void dce110_se_setup_dp_audio( 1449 struct stream_encoder *enc) 1450 { 1451 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1452 1453 /* --- DP Audio packet configurations --- */ 1454 1455 /* ATP Configuration */ 1456 REG_SET(DP_SEC_AUD_N, 0, 1457 DP_SEC_AUD_N, DP_SEC_AUD_N__DP_SEC_AUD_N__DEFAULT); 1458 1459 /* Async/auto-calc timestamp mode */ 1460 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, 1461 DP_SEC_TIMESTAMP__DP_SEC_TIMESTAMP_MODE__AUTO_CALC); 1462 1463 /* --- The following are the registers 1464 * copied from the SetupHDMI --- */ 1465 1466 /* AFMT_AUDIO_PACKET_CONTROL */ 1467 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1); 1468 1469 /* AFMT_AUDIO_PACKET_CONTROL2 */ 1470 /* Program the ATP and AIP next */ 1471 REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, 1472 AFMT_AUDIO_LAYOUT_OVRD, 0, 1473 AFMT_60958_OSF_OVRD, 0); 1474 1475 /* AFMT_INFOFRAME_CONTROL0 */ 1476 REG_UPDATE(AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1); 1477 1478 /* AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */ 1479 REG_UPDATE(AFMT_60958_0, AFMT_60958_CS_CLOCK_ACCURACY, 0); 1480 } 1481 1482 static void dce110_se_enable_audio_clock( 1483 struct stream_encoder *enc, 1484 bool enable) 1485 { 1486 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1487 1488 if (REG(AFMT_CNTL) == 0) 1489 return; /* DCE8/10 does not have this register */ 1490 1491 REG_UPDATE(AFMT_CNTL, AFMT_AUDIO_CLOCK_EN, !!enable); 1492 1493 /* wait for AFMT clock to turn on, 1494 * expectation: this should complete in 1-2 reads 1495 * 1496 * REG_WAIT(AFMT_CNTL, AFMT_AUDIO_CLOCK_ON, !!enable, 1, 10); 1497 * 1498 * TODO: wait for clock_on does not work well. May need HW 1499 * program sequence. But audio seems work normally even without wait 1500 * for clock_on status change 1501 */ 1502 } 1503 1504 static void dce110_se_enable_dp_audio( 1505 struct stream_encoder *enc) 1506 { 1507 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1508 1509 /* Enable Audio packets */ 1510 REG_UPDATE(DP_SEC_CNTL, DP_SEC_ASP_ENABLE, 1); 1511 1512 /* Program the ATP and AIP next */ 1513 REG_UPDATE_2(DP_SEC_CNTL, 1514 DP_SEC_ATP_ENABLE, 1, 1515 DP_SEC_AIP_ENABLE, 1); 1516 1517 /* Program STREAM_ENABLE after all the other enables. */ 1518 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1519 } 1520 1521 static void dce110_se_disable_dp_audio( 1522 struct stream_encoder *enc) 1523 { 1524 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1525 uint32_t value = 0; 1526 1527 /* Disable Audio packets */ 1528 REG_UPDATE_5(DP_SEC_CNTL, 1529 DP_SEC_ASP_ENABLE, 0, 1530 DP_SEC_ATP_ENABLE, 0, 1531 DP_SEC_AIP_ENABLE, 0, 1532 DP_SEC_ACM_ENABLE, 0, 1533 DP_SEC_STREAM_ENABLE, 0); 1534 1535 /* This register shared with encoder info frame. Therefore we need to 1536 keep master enabled if at least on of the fields is not 0 */ 1537 value = REG_READ(DP_SEC_CNTL); 1538 if (value != 0) 1539 REG_UPDATE(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, 1); 1540 1541 } 1542 1543 void dce110_se_audio_mute_control( 1544 struct stream_encoder *enc, 1545 bool mute) 1546 { 1547 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1548 1549 REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, !mute); 1550 } 1551 1552 void dce110_se_dp_audio_setup( 1553 struct stream_encoder *enc, 1554 unsigned int az_inst, 1555 struct audio_info *info) 1556 { 1557 dce110_se_audio_setup(enc, az_inst, info); 1558 } 1559 1560 void dce110_se_dp_audio_enable( 1561 struct stream_encoder *enc) 1562 { 1563 dce110_se_enable_audio_clock(enc, true); 1564 dce110_se_setup_dp_audio(enc); 1565 dce110_se_enable_dp_audio(enc); 1566 } 1567 1568 void dce110_se_dp_audio_disable( 1569 struct stream_encoder *enc) 1570 { 1571 dce110_se_disable_dp_audio(enc); 1572 dce110_se_enable_audio_clock(enc, false); 1573 } 1574 1575 void dce110_se_hdmi_audio_setup( 1576 struct stream_encoder *enc, 1577 unsigned int az_inst, 1578 struct audio_info *info, 1579 struct audio_crtc_info *audio_crtc_info) 1580 { 1581 dce110_se_enable_audio_clock(enc, true); 1582 dce110_se_setup_hdmi_audio(enc, audio_crtc_info); 1583 dce110_se_audio_setup(enc, az_inst, info); 1584 } 1585 1586 void dce110_se_hdmi_audio_disable( 1587 struct stream_encoder *enc) 1588 { 1589 dce110_se_enable_audio_clock(enc, false); 1590 } 1591 1592 1593 static void setup_stereo_sync( 1594 struct stream_encoder *enc, 1595 int tg_inst, bool enable) 1596 { 1597 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1598 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_SELECT, tg_inst); 1599 REG_UPDATE(DIG_FE_CNTL, DIG_STEREOSYNC_GATE_EN, !enable); 1600 } 1601 1602 static void dig_connect_to_otg( 1603 struct stream_encoder *enc, 1604 int tg_inst) 1605 { 1606 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1607 1608 REG_UPDATE(DIG_FE_CNTL, DIG_SOURCE_SELECT, tg_inst); 1609 } 1610 1611 static unsigned int dig_source_otg( 1612 struct stream_encoder *enc) 1613 { 1614 uint32_t tg_inst = 0; 1615 struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc); 1616 1617 REG_GET(DIG_FE_CNTL, DIG_SOURCE_SELECT, &tg_inst); 1618 1619 return tg_inst; 1620 } 1621 1622 static const struct stream_encoder_funcs dce110_str_enc_funcs = { 1623 .dp_set_stream_attribute = 1624 dce110_stream_encoder_dp_set_stream_attribute, 1625 .hdmi_set_stream_attribute = 1626 dce110_stream_encoder_hdmi_set_stream_attribute, 1627 .dvi_set_stream_attribute = 1628 dce110_stream_encoder_dvi_set_stream_attribute, 1629 .lvds_set_stream_attribute = 1630 dce110_stream_encoder_lvds_set_stream_attribute, 1631 .set_mst_bandwidth = 1632 dce110_stream_encoder_set_mst_bandwidth, 1633 .update_hdmi_info_packets = 1634 dce110_stream_encoder_update_hdmi_info_packets, 1635 .stop_hdmi_info_packets = 1636 dce110_stream_encoder_stop_hdmi_info_packets, 1637 .update_dp_info_packets = 1638 dce110_stream_encoder_update_dp_info_packets, 1639 .stop_dp_info_packets = 1640 dce110_stream_encoder_stop_dp_info_packets, 1641 .dp_blank = 1642 dce110_stream_encoder_dp_blank, 1643 .dp_unblank = 1644 dce110_stream_encoder_dp_unblank, 1645 .audio_mute_control = dce110_se_audio_mute_control, 1646 1647 .dp_audio_setup = dce110_se_dp_audio_setup, 1648 .dp_audio_enable = dce110_se_dp_audio_enable, 1649 .dp_audio_disable = dce110_se_dp_audio_disable, 1650 1651 .hdmi_audio_setup = dce110_se_hdmi_audio_setup, 1652 .hdmi_audio_disable = dce110_se_hdmi_audio_disable, 1653 .setup_stereo_sync = setup_stereo_sync, 1654 .set_avmute = dce110_stream_encoder_set_avmute, 1655 .dig_connect_to_otg = dig_connect_to_otg, 1656 .hdmi_reset_stream_attribute = dce110_reset_hdmi_stream_attribute, 1657 .dig_source_otg = dig_source_otg, 1658 }; 1659 1660 void dce110_stream_encoder_construct( 1661 struct dce110_stream_encoder *enc110, 1662 struct dc_context *ctx, 1663 struct dc_bios *bp, 1664 enum engine_id eng_id, 1665 const struct dce110_stream_enc_registers *regs, 1666 const struct dce_stream_encoder_shift *se_shift, 1667 const struct dce_stream_encoder_mask *se_mask) 1668 { 1669 enc110->base.funcs = &dce110_str_enc_funcs; 1670 enc110->base.ctx = ctx; 1671 enc110->base.id = eng_id; 1672 enc110->base.bp = bp; 1673 enc110->regs = regs; 1674 enc110->se_shift = se_shift; 1675 enc110->se_mask = se_mask; 1676 } 1677
Indexes created Sun Sep 21 20:09:37 GMT 2025