1 /* $NetBSD: amdgpu_dce112_resource.c,v 1.4 2021/12/19 11:59:30 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce112_resource.c,v 1.4 2021/12/19 11:59:30 riastradh Exp $"); 30 31 #include <linux/slab.h> 32 33 #include "dm_services.h" 34 35 #include "link_encoder.h" 36 #include "stream_encoder.h" 37 38 #include "resource.h" 39 #include "include/irq_service_interface.h" 40 #include "dce110/dce110_resource.h" 41 #include "dce110/dce110_timing_generator.h" 42 43 #include "irq/dce110/irq_service_dce110.h" 44 #include "dce/dce_mem_input.h" 45 #include "dce/dce_transform.h" 46 #include "dce/dce_link_encoder.h" 47 #include "dce/dce_stream_encoder.h" 48 #include "dce/dce_audio.h" 49 #include "dce/dce_opp.h" 50 #include "dce/dce_ipp.h" 51 #include "dce/dce_clock_source.h" 52 53 #include "dce/dce_hwseq.h" 54 #include "dce112/dce112_hw_sequencer.h" 55 #include "dce/dce_abm.h" 56 #include "dce/dce_dmcu.h" 57 #include "dce/dce_aux.h" 58 #include "dce/dce_i2c.h" 59 60 #include "reg_helper.h" 61 62 #include "dce/dce_11_2_d.h" 63 #include "dce/dce_11_2_sh_mask.h" 64 65 #include "dce100/dce100_resource.h" 66 #define DC_LOGGER \ 67 dc->ctx->logger 68 69 #ifndef mmDP_DPHY_INTERNAL_CTRL 70 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7 71 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7 72 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7 73 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7 74 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7 75 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7 76 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7 77 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7 78 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7 79 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7 80 #endif 81 82 #ifndef mmBIOS_SCRATCH_2 83 #define mmBIOS_SCRATCH_2 0x05CB 84 #define mmBIOS_SCRATCH_3 0x05CC 85 #define mmBIOS_SCRATCH_6 0x05CF 86 #endif 87 88 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL 89 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 90 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC 91 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC 92 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC 93 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC 94 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC 95 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC 96 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC 97 #endif 98 99 #ifndef mmDP_DPHY_FAST_TRAINING 100 #define mmDP_DPHY_FAST_TRAINING 0x4ABC 101 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC 102 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC 103 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC 104 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC 105 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC 106 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC 107 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC 108 #endif 109 110 enum dce112_clk_src_array_id { 111 DCE112_CLK_SRC_PLL0, 112 DCE112_CLK_SRC_PLL1, 113 DCE112_CLK_SRC_PLL2, 114 DCE112_CLK_SRC_PLL3, 115 DCE112_CLK_SRC_PLL4, 116 DCE112_CLK_SRC_PLL5, 117 118 DCE112_CLK_SRC_TOTAL 119 }; 120 121 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = { 122 { 123 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL), 124 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL), 125 }, 126 { 127 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL), 128 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL), 129 }, 130 { 131 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL), 132 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL), 133 }, 134 { 135 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL), 136 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL), 137 }, 138 { 139 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL), 140 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL), 141 }, 142 { 143 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL), 144 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL), 145 } 146 }; 147 148 /* set register offset */ 149 #define SR(reg_name)\ 150 .reg_name = mm ## reg_name 151 152 /* set register offset with instance */ 153 #define SRI(reg_name, block, id)\ 154 .reg_name = mm ## block ## id ## _ ## reg_name 155 156 static const struct dce_dmcu_registers dmcu_regs = { 157 DMCU_DCE110_COMMON_REG_LIST() 158 }; 159 160 static const struct dce_dmcu_shift dmcu_shift = { 161 DMCU_MASK_SH_LIST_DCE110(__SHIFT) 162 }; 163 164 static const struct dce_dmcu_mask dmcu_mask = { 165 DMCU_MASK_SH_LIST_DCE110(_MASK) 166 }; 167 168 static const struct dce_abm_registers abm_regs = { 169 ABM_DCE110_COMMON_REG_LIST() 170 }; 171 172 static const struct dce_abm_shift abm_shift = { 173 ABM_MASK_SH_LIST_DCE110(__SHIFT) 174 }; 175 176 static const struct dce_abm_mask abm_mask = { 177 ABM_MASK_SH_LIST_DCE110(_MASK) 178 }; 179 180 static const struct dce110_aux_registers_shift aux_shift = { 181 DCE_AUX_MASK_SH_LIST(__SHIFT) 182 }; 183 184 static const struct dce110_aux_registers_mask aux_mask = { 185 DCE_AUX_MASK_SH_LIST(_MASK) 186 }; 187 188 #define ipp_regs(id)\ 189 [id] = {\ 190 IPP_DCE110_REG_LIST_DCE_BASE(id)\ 191 } 192 193 static const struct dce_ipp_registers ipp_regs[] = { 194 ipp_regs(0), 195 ipp_regs(1), 196 ipp_regs(2), 197 ipp_regs(3), 198 ipp_regs(4), 199 ipp_regs(5) 200 }; 201 202 static const struct dce_ipp_shift ipp_shift = { 203 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) 204 }; 205 206 static const struct dce_ipp_mask ipp_mask = { 207 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) 208 }; 209 210 #define transform_regs(id)\ 211 [id] = {\ 212 XFM_COMMON_REG_LIST_DCE110(id)\ 213 } 214 215 static const struct dce_transform_registers xfm_regs[] = { 216 transform_regs(0), 217 transform_regs(1), 218 transform_regs(2), 219 transform_regs(3), 220 transform_regs(4), 221 transform_regs(5) 222 }; 223 224 static const struct dce_transform_shift xfm_shift = { 225 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 226 }; 227 228 static const struct dce_transform_mask xfm_mask = { 229 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) 230 }; 231 232 #define aux_regs(id)\ 233 [id] = {\ 234 AUX_REG_LIST(id)\ 235 } 236 237 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = { 238 aux_regs(0), 239 aux_regs(1), 240 aux_regs(2), 241 aux_regs(3), 242 aux_regs(4), 243 aux_regs(5) 244 }; 245 246 #define hpd_regs(id)\ 247 [id] = {\ 248 HPD_REG_LIST(id)\ 249 } 250 251 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = { 252 hpd_regs(0), 253 hpd_regs(1), 254 hpd_regs(2), 255 hpd_regs(3), 256 hpd_regs(4), 257 hpd_regs(5) 258 }; 259 260 #define link_regs(id)\ 261 [id] = {\ 262 LE_DCE110_REG_LIST(id)\ 263 } 264 265 static const struct dce110_link_enc_registers link_enc_regs[] = { 266 link_regs(0), 267 link_regs(1), 268 link_regs(2), 269 link_regs(3), 270 link_regs(4), 271 link_regs(5), 272 link_regs(6), 273 }; 274 275 #define stream_enc_regs(id)\ 276 [id] = {\ 277 SE_COMMON_REG_LIST(id),\ 278 .TMDS_CNTL = 0,\ 279 } 280 281 static const struct dce110_stream_enc_registers stream_enc_regs[] = { 282 stream_enc_regs(0), 283 stream_enc_regs(1), 284 stream_enc_regs(2), 285 stream_enc_regs(3), 286 stream_enc_regs(4), 287 stream_enc_regs(5) 288 }; 289 290 static const struct dce_stream_encoder_shift se_shift = { 291 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) 292 }; 293 294 static const struct dce_stream_encoder_mask se_mask = { 295 SE_COMMON_MASK_SH_LIST_DCE112(_MASK) 296 }; 297 298 #define opp_regs(id)\ 299 [id] = {\ 300 OPP_DCE_112_REG_LIST(id),\ 301 } 302 303 static const struct dce_opp_registers opp_regs[] = { 304 opp_regs(0), 305 opp_regs(1), 306 opp_regs(2), 307 opp_regs(3), 308 opp_regs(4), 309 opp_regs(5) 310 }; 311 312 static const struct dce_opp_shift opp_shift = { 313 OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 314 }; 315 316 static const struct dce_opp_mask opp_mask = { 317 OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) 318 }; 319 320 #define aux_engine_regs(id)\ 321 [id] = {\ 322 AUX_COMMON_REG_LIST(id), \ 323 .AUX_RESET_MASK = 0 \ 324 } 325 326 static const struct dce110_aux_registers aux_engine_regs[] = { 327 aux_engine_regs(0), 328 aux_engine_regs(1), 329 aux_engine_regs(2), 330 aux_engine_regs(3), 331 aux_engine_regs(4), 332 aux_engine_regs(5) 333 }; 334 335 #define audio_regs(id)\ 336 [id] = {\ 337 AUD_COMMON_REG_LIST(id)\ 338 } 339 340 static const struct dce_audio_registers audio_regs[] = { 341 audio_regs(0), 342 audio_regs(1), 343 audio_regs(2), 344 audio_regs(3), 345 audio_regs(4), 346 audio_regs(5) 347 }; 348 349 static const struct dce_audio_shift audio_shift = { 350 AUD_COMMON_MASK_SH_LIST(__SHIFT) 351 }; 352 353 static const struct dce_audio_mask audio_mask = { 354 AUD_COMMON_MASK_SH_LIST(_MASK) 355 }; 356 357 #define clk_src_regs(index, id)\ 358 [index] = {\ 359 CS_COMMON_REG_LIST_DCE_112(id),\ 360 } 361 362 static const struct dce110_clk_src_regs clk_src_regs[] = { 363 clk_src_regs(0, A), 364 clk_src_regs(1, B), 365 clk_src_regs(2, C), 366 clk_src_regs(3, D), 367 clk_src_regs(4, E), 368 clk_src_regs(5, F) 369 }; 370 371 static const struct dce110_clk_src_shift cs_shift = { 372 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) 373 }; 374 375 static const struct dce110_clk_src_mask cs_mask = { 376 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) 377 }; 378 379 static const struct bios_registers bios_regs = { 380 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3, 381 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 382 }; 383 384 static const struct resource_caps polaris_10_resource_cap = { 385 .num_timing_generator = 6, 386 .num_audio = 6, 387 .num_stream_encoder = 6, 388 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 389 .num_ddc = 6, 390 }; 391 392 static const struct resource_caps polaris_11_resource_cap = { 393 .num_timing_generator = 5, 394 .num_audio = 5, 395 .num_stream_encoder = 5, 396 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */ 397 .num_ddc = 5, 398 }; 399 400 static const struct dc_plane_cap plane_cap = { 401 .type = DC_PLANE_TYPE_DCE_RGB, 402 403 .pixel_format_support = { 404 .argb8888 = true, 405 .nv12 = false, 406 .fp16 = false 407 }, 408 409 .max_upscale_factor = { 410 .argb8888 = 16000, 411 .nv12 = 1, 412 .fp16 = 1 413 }, 414 415 .max_downscale_factor = { 416 .argb8888 = 250, 417 .nv12 = 1, 418 .fp16 = 1 419 } 420 }; 421 422 #define CTX ctx 423 #define REG(reg) mm ## reg 424 425 #ifndef mmCC_DC_HDMI_STRAPS 426 #define mmCC_DC_HDMI_STRAPS 0x4819 427 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40 428 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6 429 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700 430 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8 431 #endif 432 433 static int map_transmitter_id_to_phy_instance( 434 enum transmitter transmitter) 435 { 436 switch (transmitter) { 437 case TRANSMITTER_UNIPHY_A: 438 return 0; 439 break; 440 case TRANSMITTER_UNIPHY_B: 441 return 1; 442 break; 443 case TRANSMITTER_UNIPHY_C: 444 return 2; 445 break; 446 case TRANSMITTER_UNIPHY_D: 447 return 3; 448 break; 449 case TRANSMITTER_UNIPHY_E: 450 return 4; 451 break; 452 case TRANSMITTER_UNIPHY_F: 453 return 5; 454 break; 455 case TRANSMITTER_UNIPHY_G: 456 return 6; 457 break; 458 default: 459 ASSERT(0); 460 return 0; 461 } 462 } 463 464 static void read_dce_straps( 465 struct dc_context *ctx, 466 struct resource_straps *straps) 467 { 468 REG_GET_2(CC_DC_HDMI_STRAPS, 469 HDMI_DISABLE, &straps->hdmi_disable, 470 AUDIO_STREAM_NUMBER, &straps->audio_stream_number); 471 472 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio); 473 } 474 475 static struct audio *create_audio( 476 struct dc_context *ctx, unsigned int inst) 477 { 478 return dce_audio_create(ctx, inst, 479 &audio_regs[inst], &audio_shift, &audio_mask); 480 } 481 482 static struct timing_generator *dce112_timing_generator_create( 483 struct dc_context *ctx, 484 uint32_t instance, 485 const struct dce110_timing_generator_offsets *offsets) 486 { 487 struct dce110_timing_generator *tg110 = 488 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL); 489 490 if (!tg110) 491 return NULL; 492 493 dce110_timing_generator_construct(tg110, ctx, instance, offsets); 494 return &tg110->base; 495 } 496 497 static struct stream_encoder *dce112_stream_encoder_create( 498 enum engine_id eng_id, 499 struct dc_context *ctx) 500 { 501 struct dce110_stream_encoder *enc110 = 502 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL); 503 504 if (!enc110) 505 return NULL; 506 507 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id, 508 &stream_enc_regs[eng_id], 509 &se_shift, &se_mask); 510 return &enc110->base; 511 } 512 513 #define SRII(reg_name, block, id)\ 514 .reg_name[id] = mm ## block ## id ## _ ## reg_name 515 516 static const struct dce_hwseq_registers hwseq_reg = { 517 HWSEQ_DCE112_REG_LIST() 518 }; 519 520 static const struct dce_hwseq_shift hwseq_shift = { 521 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) 522 }; 523 524 static const struct dce_hwseq_mask hwseq_mask = { 525 HWSEQ_DCE112_MASK_SH_LIST(_MASK) 526 }; 527 528 static struct dce_hwseq *dce112_hwseq_create( 529 struct dc_context *ctx) 530 { 531 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL); 532 533 if (hws) { 534 hws->ctx = ctx; 535 hws->regs = &hwseq_reg; 536 hws->shifts = &hwseq_shift; 537 hws->masks = &hwseq_mask; 538 } 539 return hws; 540 } 541 542 static const struct resource_create_funcs res_create_funcs = { 543 .read_dce_straps = read_dce_straps, 544 .create_audio = create_audio, 545 .create_stream_encoder = dce112_stream_encoder_create, 546 .create_hwseq = dce112_hwseq_create, 547 }; 548 549 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) } 550 static const struct dce_mem_input_registers mi_regs[] = { 551 mi_inst_regs(0), 552 mi_inst_regs(1), 553 mi_inst_regs(2), 554 mi_inst_regs(3), 555 mi_inst_regs(4), 556 mi_inst_regs(5), 557 }; 558 559 static const struct dce_mem_input_shift mi_shifts = { 560 MI_DCE11_2_MASK_SH_LIST(__SHIFT) 561 }; 562 563 static const struct dce_mem_input_mask mi_masks = { 564 MI_DCE11_2_MASK_SH_LIST(_MASK) 565 }; 566 567 static struct mem_input *dce112_mem_input_create( 568 struct dc_context *ctx, 569 uint32_t inst) 570 { 571 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input), 572 GFP_KERNEL); 573 574 if (!dce_mi) { 575 BREAK_TO_DEBUGGER(); 576 return NULL; 577 } 578 579 dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks); 580 return &dce_mi->base; 581 } 582 583 static void dce112_transform_destroy(struct transform **xfm) 584 { 585 kfree(TO_DCE_TRANSFORM(*xfm)); 586 *xfm = NULL; 587 } 588 589 static struct transform *dce112_transform_create( 590 struct dc_context *ctx, 591 uint32_t inst) 592 { 593 struct dce_transform *transform = 594 kzalloc(sizeof(struct dce_transform), GFP_KERNEL); 595 596 if (!transform) 597 return NULL; 598 599 dce_transform_construct(transform, ctx, inst, 600 &xfm_regs[inst], &xfm_shift, &xfm_mask); 601 transform->lb_memory_size = 0x1404; /*5124*/ 602 return &transform->base; 603 } 604 605 static const struct encoder_feature_support link_enc_feature = { 606 .max_hdmi_deep_color = COLOR_DEPTH_121212, 607 .max_hdmi_pixel_clock = 600000, 608 .hdmi_ycbcr420_supported = true, 609 .dp_ycbcr420_supported = false, 610 .flags.bits.IS_HBR2_CAPABLE = true, 611 .flags.bits.IS_HBR3_CAPABLE = true, 612 .flags.bits.IS_TPS3_CAPABLE = true, 613 .flags.bits.IS_TPS4_CAPABLE = true 614 }; 615 616 struct link_encoder *dce112_link_encoder_create( 617 const struct encoder_init_data *enc_init_data) 618 { 619 struct dce110_link_encoder *enc110 = 620 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL); 621 int link_regs_id; 622 623 if (!enc110) 624 return NULL; 625 626 link_regs_id = 627 map_transmitter_id_to_phy_instance(enc_init_data->transmitter); 628 629 dce110_link_encoder_construct(enc110, 630 enc_init_data, 631 &link_enc_feature, 632 &link_enc_regs[link_regs_id], 633 &link_enc_aux_regs[enc_init_data->channel - 1], 634 &link_enc_hpd_regs[enc_init_data->hpd_source]); 635 return &enc110->base; 636 } 637 638 static struct input_pixel_processor *dce112_ipp_create( 639 struct dc_context *ctx, uint32_t inst) 640 { 641 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL); 642 643 if (!ipp) { 644 BREAK_TO_DEBUGGER(); 645 return NULL; 646 } 647 648 dce_ipp_construct(ipp, ctx, inst, 649 &ipp_regs[inst], &ipp_shift, &ipp_mask); 650 return &ipp->base; 651 } 652 653 struct output_pixel_processor *dce112_opp_create( 654 struct dc_context *ctx, 655 uint32_t inst) 656 { 657 struct dce110_opp *opp = 658 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL); 659 660 if (!opp) 661 return NULL; 662 663 dce110_opp_construct(opp, 664 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask); 665 return &opp->base; 666 } 667 668 struct dce_aux *dce112_aux_engine_create( 669 struct dc_context *ctx, 670 uint32_t inst) 671 { 672 struct aux_engine_dce110 *aux_engine = 673 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL); 674 675 if (!aux_engine) 676 return NULL; 677 678 dce110_aux_engine_construct(aux_engine, ctx, inst, 679 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD, 680 &aux_engine_regs[inst], 681 &aux_mask, 682 &aux_shift, 683 ctx->dc->caps.extended_aux_timeout_support); 684 685 return &aux_engine->base; 686 } 687 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) } 688 689 static const struct dce_i2c_registers i2c_hw_regs[] = { 690 i2c_inst_regs(1), 691 i2c_inst_regs(2), 692 i2c_inst_regs(3), 693 i2c_inst_regs(4), 694 i2c_inst_regs(5), 695 i2c_inst_regs(6), 696 }; 697 698 static const struct dce_i2c_shift i2c_shifts = { 699 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) 700 }; 701 702 static const struct dce_i2c_mask i2c_masks = { 703 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) 704 }; 705 706 struct dce_i2c_hw *dce112_i2c_hw_create( 707 struct dc_context *ctx, 708 uint32_t inst) 709 { 710 struct dce_i2c_hw *dce_i2c_hw = 711 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL); 712 713 if (!dce_i2c_hw) 714 return NULL; 715 716 dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst, 717 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks); 718 719 return dce_i2c_hw; 720 } 721 struct clock_source *dce112_clock_source_create( 722 struct dc_context *ctx, 723 struct dc_bios *bios, 724 enum clock_source_id id, 725 const struct dce110_clk_src_regs *regs, 726 bool dp_clk_src) 727 { 728 struct dce110_clk_src *clk_src = 729 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL); 730 731 if (!clk_src) 732 return NULL; 733 734 if (dce112_clk_src_construct(clk_src, ctx, bios, id, 735 regs, &cs_shift, &cs_mask)) { 736 clk_src->base.dp_clk_src = dp_clk_src; 737 return &clk_src->base; 738 } 739 740 kfree(clk_src); 741 BREAK_TO_DEBUGGER(); 742 return NULL; 743 } 744 745 void dce112_clock_source_destroy(struct clock_source **clk_src) 746 { 747 kfree(TO_DCE110_CLK_SRC(*clk_src)); 748 *clk_src = NULL; 749 } 750 751 static void dce112_resource_destruct(struct dce110_resource_pool *pool) 752 { 753 unsigned int i; 754 755 for (i = 0; i < pool->base.pipe_count; i++) { 756 if (pool->base.opps[i] != NULL) 757 dce110_opp_destroy(&pool->base.opps[i]); 758 759 if (pool->base.transforms[i] != NULL) 760 dce112_transform_destroy(&pool->base.transforms[i]); 761 762 if (pool->base.ipps[i] != NULL) 763 dce_ipp_destroy(&pool->base.ipps[i]); 764 765 if (pool->base.mis[i] != NULL) { 766 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i])); 767 pool->base.mis[i] = NULL; 768 } 769 770 if (pool->base.timing_generators[i] != NULL) { 771 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i])); 772 pool->base.timing_generators[i] = NULL; 773 } 774 } 775 776 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 777 if (pool->base.engines[i] != NULL) 778 dce110_engine_destroy(&pool->base.engines[i]); 779 if (pool->base.hw_i2cs[i] != NULL) { 780 kfree(pool->base.hw_i2cs[i]); 781 pool->base.hw_i2cs[i] = NULL; 782 } 783 if (pool->base.sw_i2cs[i] != NULL) { 784 kfree(pool->base.sw_i2cs[i]); 785 pool->base.sw_i2cs[i] = NULL; 786 } 787 } 788 789 for (i = 0; i < pool->base.stream_enc_count; i++) { 790 if (pool->base.stream_enc[i] != NULL) 791 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i])); 792 } 793 794 for (i = 0; i < pool->base.clk_src_count; i++) { 795 if (pool->base.clock_sources[i] != NULL) { 796 dce112_clock_source_destroy(&pool->base.clock_sources[i]); 797 } 798 } 799 800 if (pool->base.dp_clock_source != NULL) 801 dce112_clock_source_destroy(&pool->base.dp_clock_source); 802 803 for (i = 0; i < pool->base.audio_count; i++) { 804 if (pool->base.audios[i] != NULL) { 805 dce_aud_destroy(&pool->base.audios[i]); 806 } 807 } 808 809 if (pool->base.abm != NULL) 810 dce_abm_destroy(&pool->base.abm); 811 812 if (pool->base.dmcu != NULL) 813 dce_dmcu_destroy(&pool->base.dmcu); 814 815 if (pool->base.irqs != NULL) { 816 dal_irq_service_destroy(&pool->base.irqs); 817 } 818 } 819 820 static struct clock_source *find_matching_pll( 821 struct resource_context *res_ctx, 822 const struct resource_pool *pool, 823 const struct dc_stream_state *const stream) 824 { 825 switch (stream->link->link_enc->transmitter) { 826 case TRANSMITTER_UNIPHY_A: 827 return pool->clock_sources[DCE112_CLK_SRC_PLL0]; 828 case TRANSMITTER_UNIPHY_B: 829 return pool->clock_sources[DCE112_CLK_SRC_PLL1]; 830 case TRANSMITTER_UNIPHY_C: 831 return pool->clock_sources[DCE112_CLK_SRC_PLL2]; 832 case TRANSMITTER_UNIPHY_D: 833 return pool->clock_sources[DCE112_CLK_SRC_PLL3]; 834 case TRANSMITTER_UNIPHY_E: 835 return pool->clock_sources[DCE112_CLK_SRC_PLL4]; 836 case TRANSMITTER_UNIPHY_F: 837 return pool->clock_sources[DCE112_CLK_SRC_PLL5]; 838 default: 839 return NULL; 840 }; 841 842 return 0; 843 } 844 845 static enum dc_status build_mapped_resource( 846 const struct dc *dc, 847 struct dc_state *context, 848 struct dc_stream_state *stream) 849 { 850 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream); 851 852 if (!pipe_ctx) 853 return DC_ERROR_UNEXPECTED; 854 855 dce110_resource_build_pipe_hw_param(pipe_ctx); 856 857 resource_build_info_frame(pipe_ctx); 858 859 return DC_OK; 860 } 861 862 bool dce112_validate_bandwidth( 863 struct dc *dc, 864 struct dc_state *context, 865 bool fast_validate) 866 { 867 bool result = false; 868 869 DC_LOG_BANDWIDTH_CALCS( 870 "%s: start", 871 __func__); 872 873 if (bw_calcs( 874 dc->ctx, 875 dc->bw_dceip, 876 dc->bw_vbios, 877 context->res_ctx.pipe_ctx, 878 dc->res_pool->pipe_count, 879 &context->bw_ctx.bw.dce)) 880 result = true; 881 882 if (!result) 883 DC_LOG_BANDWIDTH_VALIDATION( 884 "%s: Bandwidth validation failed!", 885 __func__); 886 887 if (memcmp(&dc->current_state->bw_ctx.bw.dce, 888 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { 889 890 DC_LOG_BANDWIDTH_CALCS( 891 "%s: finish,\n" 892 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 893 "stutMark_b: %d stutMark_a: %d\n" 894 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 895 "stutMark_b: %d stutMark_a: %d\n" 896 "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n" 897 "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n" 898 "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n" 899 "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n" 900 , 901 __func__, 902 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].b_mark, 903 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[0].a_mark, 904 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, 905 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, 906 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].b_mark, 907 context->bw_ctx.bw.dce.stutter_exit_wm_ns[0].a_mark, 908 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].b_mark, 909 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[1].a_mark, 910 context->bw_ctx.bw.dce.urgent_wm_ns[1].b_mark, 911 context->bw_ctx.bw.dce.urgent_wm_ns[1].a_mark, 912 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].b_mark, 913 context->bw_ctx.bw.dce.stutter_exit_wm_ns[1].a_mark, 914 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].b_mark, 915 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[2].a_mark, 916 context->bw_ctx.bw.dce.urgent_wm_ns[2].b_mark, 917 context->bw_ctx.bw.dce.urgent_wm_ns[2].a_mark, 918 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].b_mark, 919 context->bw_ctx.bw.dce.stutter_exit_wm_ns[2].a_mark, 920 context->bw_ctx.bw.dce.stutter_mode_enable, 921 context->bw_ctx.bw.dce.cpuc_state_change_enable, 922 context->bw_ctx.bw.dce.cpup_state_change_enable, 923 context->bw_ctx.bw.dce.nbp_state_change_enable, 924 context->bw_ctx.bw.dce.all_displays_in_sync, 925 context->bw_ctx.bw.dce.dispclk_khz, 926 context->bw_ctx.bw.dce.sclk_khz, 927 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, 928 context->bw_ctx.bw.dce.yclk_khz, 929 context->bw_ctx.bw.dce.blackout_recovery_time_us); 930 } 931 return result; 932 } 933 934 enum dc_status resource_map_phy_clock_resources( 935 const struct dc *dc, 936 struct dc_state *context, 937 struct dc_stream_state *stream) 938 { 939 940 /* acquire new resources */ 941 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream( 942 &context->res_ctx, stream); 943 944 if (!pipe_ctx) 945 return DC_ERROR_UNEXPECTED; 946 947 if (dc_is_dp_signal(pipe_ctx->stream->signal) 948 || dc_is_virtual_signal(pipe_ctx->stream->signal)) 949 pipe_ctx->clock_source = 950 dc->res_pool->dp_clock_source; 951 else 952 pipe_ctx->clock_source = find_matching_pll( 953 &context->res_ctx, dc->res_pool, 954 stream); 955 956 if (pipe_ctx->clock_source == NULL) 957 return DC_NO_CLOCK_SOURCE_RESOURCE; 958 959 resource_reference_clock_source( 960 &context->res_ctx, 961 dc->res_pool, 962 pipe_ctx->clock_source); 963 964 return DC_OK; 965 } 966 967 static bool dce112_validate_surface_sets( 968 struct dc_state *context) 969 { 970 int i; 971 972 for (i = 0; i < context->stream_count; i++) { 973 if (context->stream_status[i].plane_count == 0) 974 continue; 975 976 if (context->stream_status[i].plane_count > 1) 977 return false; 978 979 if (context->stream_status[i].plane_states[0]->format 980 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) 981 return false; 982 } 983 984 return true; 985 } 986 987 enum dc_status dce112_add_stream_to_ctx( 988 struct dc *dc, 989 struct dc_state *new_ctx, 990 struct dc_stream_state *dc_stream) 991 { 992 enum dc_status result = DC_ERROR_UNEXPECTED; 993 994 result = resource_map_pool_resources(dc, new_ctx, dc_stream); 995 996 if (result == DC_OK) 997 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); 998 999 1000 if (result == DC_OK) 1001 result = build_mapped_resource(dc, new_ctx, dc_stream); 1002 1003 return result; 1004 } 1005 1006 enum dc_status dce112_validate_global( 1007 struct dc *dc, 1008 struct dc_state *context) 1009 { 1010 if (!dce112_validate_surface_sets(context)) 1011 return DC_FAIL_SURFACE_VALIDATE; 1012 1013 return DC_OK; 1014 } 1015 1016 static void dce112_destroy_resource_pool(struct resource_pool **pool) 1017 { 1018 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool); 1019 1020 dce112_resource_destruct(dce110_pool); 1021 kfree(dce110_pool); 1022 *pool = NULL; 1023 } 1024 1025 static const struct resource_funcs dce112_res_pool_funcs = { 1026 .destroy = dce112_destroy_resource_pool, 1027 .link_enc_create = dce112_link_encoder_create, 1028 .validate_bandwidth = dce112_validate_bandwidth, 1029 .validate_plane = dce100_validate_plane, 1030 .add_stream_to_ctx = dce112_add_stream_to_ctx, 1031 .validate_global = dce112_validate_global, 1032 .find_first_free_match_stream_enc_for_link = dce110_find_first_free_match_stream_enc_for_link 1033 }; 1034 1035 static void bw_calcs_data_update_from_pplib(struct dc *dc) 1036 { 1037 struct dm_pp_clock_levels_with_latency eng_clks = {0}; 1038 struct dm_pp_clock_levels_with_latency mem_clks = {0}; 1039 struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0}; 1040 struct dm_pp_clock_levels clks = {0}; 1041 int memory_type_multiplier = MEMORY_TYPE_MULTIPLIER_CZ; 1042 1043 if (dc->bw_vbios && dc->bw_vbios->memory_type == bw_def_hbm) 1044 memory_type_multiplier = MEMORY_TYPE_HBM; 1045 1046 /*do system clock TODO PPLIB: after PPLIB implement, 1047 * then remove old way 1048 */ 1049 if (!dm_pp_get_clock_levels_by_type_with_latency( 1050 dc->ctx, 1051 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1052 &eng_clks)) { 1053 1054 /* This is only for temporary */ 1055 dm_pp_get_clock_levels_by_type( 1056 dc->ctx, 1057 DM_PP_CLOCK_TYPE_ENGINE_CLK, 1058 &clks); 1059 /* convert all the clock fro kHz to fix point mHz */ 1060 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1061 clks.clocks_in_khz[clks.num_levels-1], 1000); 1062 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1063 clks.clocks_in_khz[clks.num_levels/8], 1000); 1064 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1065 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1066 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1067 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1068 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1069 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1070 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1071 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1072 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1073 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1074 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1075 clks.clocks_in_khz[0], 1000); 1076 1077 /*do memory clock*/ 1078 dm_pp_get_clock_levels_by_type( 1079 dc->ctx, 1080 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1081 &clks); 1082 1083 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1084 clks.clocks_in_khz[0] * memory_type_multiplier, 1000); 1085 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1086 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, 1087 1000); 1088 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1089 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, 1090 1000); 1091 1092 return; 1093 } 1094 1095 /* convert all the clock fro kHz to fix point mHz TODO: wloop data */ 1096 dc->bw_vbios->high_sclk = bw_frc_to_fixed( 1097 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 1098 dc->bw_vbios->mid1_sclk = bw_frc_to_fixed( 1099 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 1100 dc->bw_vbios->mid2_sclk = bw_frc_to_fixed( 1101 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 1102 dc->bw_vbios->mid3_sclk = bw_frc_to_fixed( 1103 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 1104 dc->bw_vbios->mid4_sclk = bw_frc_to_fixed( 1105 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 1106 dc->bw_vbios->mid5_sclk = bw_frc_to_fixed( 1107 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 1108 dc->bw_vbios->mid6_sclk = bw_frc_to_fixed( 1109 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000); 1110 dc->bw_vbios->low_sclk = bw_frc_to_fixed( 1111 eng_clks.data[0].clocks_in_khz, 1000); 1112 1113 /*do memory clock*/ 1114 dm_pp_get_clock_levels_by_type_with_latency( 1115 dc->ctx, 1116 DM_PP_CLOCK_TYPE_MEMORY_CLK, 1117 &mem_clks); 1118 1119 /* we don't need to call PPLIB for validation clock since they 1120 * also give us the highest sclk and highest mclk (UMA clock). 1121 * ALSO always convert UMA clock (from PPLIB) to YCLK (HW formula): 1122 * YCLK = UMACLK*m_memoryTypeMultiplier 1123 */ 1124 dc->bw_vbios->low_yclk = bw_frc_to_fixed( 1125 mem_clks.data[0].clocks_in_khz * memory_type_multiplier, 1000); 1126 dc->bw_vbios->mid_yclk = bw_frc_to_fixed( 1127 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * memory_type_multiplier, 1128 1000); 1129 dc->bw_vbios->high_yclk = bw_frc_to_fixed( 1130 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * memory_type_multiplier, 1131 1000); 1132 1133 /* Now notify PPLib/SMU about which Watermarks sets they should select 1134 * depending on DPM state they are in. And update BW MGR GFX Engine and 1135 * Memory clock member variables for Watermarks calculations for each 1136 * Watermark Set 1137 */ 1138 clk_ranges.num_wm_sets = 4; 1139 clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A; 1140 clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz = 1141 eng_clks.data[0].clocks_in_khz; 1142 clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz = 1143 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1144 clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz = 1145 mem_clks.data[0].clocks_in_khz; 1146 clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz = 1147 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1148 1149 clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B; 1150 clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz = 1151 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1152 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1153 clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000; 1154 clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz = 1155 mem_clks.data[0].clocks_in_khz; 1156 clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz = 1157 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1; 1158 1159 clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C; 1160 clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz = 1161 eng_clks.data[0].clocks_in_khz; 1162 clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz = 1163 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1; 1164 clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz = 1165 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1166 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1167 clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000; 1168 1169 clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D; 1170 clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz = 1171 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz; 1172 /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */ 1173 clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000; 1174 clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz = 1175 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz; 1176 /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */ 1177 clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000; 1178 1179 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */ 1180 dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges); 1181 } 1182 1183 const struct resource_caps *dce112_resource_cap( 1184 struct hw_asic_id *asic_id) 1185 { 1186 if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) || 1187 ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev)) 1188 return &polaris_11_resource_cap; 1189 else 1190 return &polaris_10_resource_cap; 1191 } 1192 1193 static bool dce112_resource_construct( 1194 uint8_t num_virtual_links, 1195 struct dc *dc, 1196 struct dce110_resource_pool *pool) 1197 { 1198 unsigned int i; 1199 struct dc_context *ctx = dc->ctx; 1200 1201 ctx->dc_bios->regs = &bios_regs; 1202 1203 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); 1204 pool->base.funcs = &dce112_res_pool_funcs; 1205 1206 /************************************************* 1207 * Resource + asic cap harcoding * 1208 *************************************************/ 1209 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE; 1210 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; 1211 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; 1212 dc->caps.max_downscale_ratio = 200; 1213 dc->caps.i2c_speed_in_khz = 100; 1214 dc->caps.max_cursor_size = 128; 1215 dc->caps.dual_link_dvi = true; 1216 dc->caps.extended_aux_timeout_support = false; 1217 1218 /************************************************* 1219 * Create resources * 1220 *************************************************/ 1221 1222 pool->base.clock_sources[DCE112_CLK_SRC_PLL0] = 1223 dce112_clock_source_create( 1224 ctx, ctx->dc_bios, 1225 CLOCK_SOURCE_COMBO_PHY_PLL0, 1226 &clk_src_regs[0], false); 1227 pool->base.clock_sources[DCE112_CLK_SRC_PLL1] = 1228 dce112_clock_source_create( 1229 ctx, ctx->dc_bios, 1230 CLOCK_SOURCE_COMBO_PHY_PLL1, 1231 &clk_src_regs[1], false); 1232 pool->base.clock_sources[DCE112_CLK_SRC_PLL2] = 1233 dce112_clock_source_create( 1234 ctx, ctx->dc_bios, 1235 CLOCK_SOURCE_COMBO_PHY_PLL2, 1236 &clk_src_regs[2], false); 1237 pool->base.clock_sources[DCE112_CLK_SRC_PLL3] = 1238 dce112_clock_source_create( 1239 ctx, ctx->dc_bios, 1240 CLOCK_SOURCE_COMBO_PHY_PLL3, 1241 &clk_src_regs[3], false); 1242 pool->base.clock_sources[DCE112_CLK_SRC_PLL4] = 1243 dce112_clock_source_create( 1244 ctx, ctx->dc_bios, 1245 CLOCK_SOURCE_COMBO_PHY_PLL4, 1246 &clk_src_regs[4], false); 1247 pool->base.clock_sources[DCE112_CLK_SRC_PLL5] = 1248 dce112_clock_source_create( 1249 ctx, ctx->dc_bios, 1250 CLOCK_SOURCE_COMBO_PHY_PLL5, 1251 &clk_src_regs[5], false); 1252 pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL; 1253 1254 pool->base.dp_clock_source = dce112_clock_source_create( 1255 ctx, ctx->dc_bios, 1256 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true); 1257 1258 1259 for (i = 0; i < pool->base.clk_src_count; i++) { 1260 if (pool->base.clock_sources[i] == NULL) { 1261 dm_error("DC: failed to create clock sources!\n"); 1262 BREAK_TO_DEBUGGER(); 1263 goto res_create_fail; 1264 } 1265 } 1266 1267 pool->base.dmcu = dce_dmcu_create(ctx, 1268 &dmcu_regs, 1269 &dmcu_shift, 1270 &dmcu_mask); 1271 if (pool->base.dmcu == NULL) { 1272 dm_error("DC: failed to create dmcu!\n"); 1273 BREAK_TO_DEBUGGER(); 1274 goto res_create_fail; 1275 } 1276 1277 pool->base.abm = dce_abm_create(ctx, 1278 &abm_regs, 1279 &abm_shift, 1280 &abm_mask); 1281 if (pool->base.abm == NULL) { 1282 dm_error("DC: failed to create abm!\n"); 1283 BREAK_TO_DEBUGGER(); 1284 goto res_create_fail; 1285 } 1286 1287 { 1288 struct irq_service_init_data init_data; 1289 init_data.ctx = dc->ctx; 1290 pool->base.irqs = dal_irq_service_dce110_create(&init_data); 1291 if (!pool->base.irqs) 1292 goto res_create_fail; 1293 } 1294 1295 for (i = 0; i < pool->base.pipe_count; i++) { 1296 pool->base.timing_generators[i] = 1297 dce112_timing_generator_create( 1298 ctx, 1299 i, 1300 &dce112_tg_offsets[i]); 1301 if (pool->base.timing_generators[i] == NULL) { 1302 BREAK_TO_DEBUGGER(); 1303 dm_error("DC: failed to create tg!\n"); 1304 goto res_create_fail; 1305 } 1306 1307 pool->base.mis[i] = dce112_mem_input_create(ctx, i); 1308 if (pool->base.mis[i] == NULL) { 1309 BREAK_TO_DEBUGGER(); 1310 dm_error( 1311 "DC: failed to create memory input!\n"); 1312 goto res_create_fail; 1313 } 1314 1315 pool->base.ipps[i] = dce112_ipp_create(ctx, i); 1316 if (pool->base.ipps[i] == NULL) { 1317 BREAK_TO_DEBUGGER(); 1318 dm_error( 1319 "DC:failed to create input pixel processor!\n"); 1320 goto res_create_fail; 1321 } 1322 1323 pool->base.transforms[i] = dce112_transform_create(ctx, i); 1324 if (pool->base.transforms[i] == NULL) { 1325 BREAK_TO_DEBUGGER(); 1326 dm_error( 1327 "DC: failed to create transform!\n"); 1328 goto res_create_fail; 1329 } 1330 1331 pool->base.opps[i] = dce112_opp_create( 1332 ctx, 1333 i); 1334 if (pool->base.opps[i] == NULL) { 1335 BREAK_TO_DEBUGGER(); 1336 dm_error( 1337 "DC:failed to create output pixel processor!\n"); 1338 goto res_create_fail; 1339 } 1340 } 1341 1342 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { 1343 pool->base.engines[i] = dce112_aux_engine_create(ctx, i); 1344 if (pool->base.engines[i] == NULL) { 1345 BREAK_TO_DEBUGGER(); 1346 dm_error( 1347 "DC:failed to create aux engine!!\n"); 1348 goto res_create_fail; 1349 } 1350 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i); 1351 if (pool->base.hw_i2cs[i] == NULL) { 1352 BREAK_TO_DEBUGGER(); 1353 dm_error( 1354 "DC:failed to create i2c engine!!\n"); 1355 goto res_create_fail; 1356 } 1357 pool->base.sw_i2cs[i] = NULL; 1358 } 1359 1360 if (!resource_construct(num_virtual_links, dc, &pool->base, 1361 &res_create_funcs)) 1362 goto res_create_fail; 1363 1364 dc->caps.max_planes = pool->base.pipe_count; 1365 1366 for (i = 0; i < dc->caps.max_planes; ++i) 1367 dc->caps.planes[i] = plane_cap; 1368 1369 /* Create hardware sequencer */ 1370 dce112_hw_sequencer_construct(dc); 1371 1372 bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id); 1373 1374 bw_calcs_data_update_from_pplib(dc); 1375 1376 return true; 1377 1378 res_create_fail: 1379 dce112_resource_destruct(pool); 1380 return false; 1381 } 1382 1383 struct resource_pool *dce112_create_resource_pool( 1384 uint8_t num_virtual_links, 1385 struct dc *dc) 1386 { 1387 struct dce110_resource_pool *pool = 1388 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL); 1389 1390 if (!pool) 1391 return NULL; 1392 1393 if (dce112_resource_construct(num_virtual_links, dc, pool)) 1394 return &pool->base; 1395 1396 kfree(pool); 1397 BREAK_TO_DEBUGGER(); 1398 return NULL; 1399 } 1400
Indexes created Sat Sep 20 22:09:52 GMT 2025