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      1 /*	$NetBSD: amdgpu_dce120_clk_mgr.c,v 1.2 2021/12/18 23:45:01 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2012-16 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: AMD
     25  *
     26  */
     27 
     28 #include <sys/cdefs.h>
     29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce120_clk_mgr.c,v 1.2 2021/12/18 23:45:01 riastradh Exp $");
     30 
     31 #include "core_types.h"
     32 #include "clk_mgr_internal.h"
     33 
     34 #include "dce112/dce112_clk_mgr.h"
     35 #include "dce110/dce110_clk_mgr.h"
     36 #include "dce120_clk_mgr.h"
     37 #include "dce100/dce_clk_mgr.h"
     38 #include "dce120/dce120_hw_sequencer.h"
     39 
     40 static const struct state_dependent_clocks dce120_max_clks_by_state[] = {
     41 /*ClocksStateInvalid - should not be used*/
     42 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
     43 /*ClocksStateUltraLow - currently by HW design team not supposed to be used*/
     44 { .display_clk_khz = 0, .pixel_clk_khz = 0 },
     45 /*ClocksStateLow*/
     46 { .display_clk_khz = 460000, .pixel_clk_khz = 400000 },
     47 /*ClocksStateNominal*/
     48 { .display_clk_khz = 670000, .pixel_clk_khz = 600000 },
     49 /*ClocksStatePerformance*/
     50 { .display_clk_khz = 1133000, .pixel_clk_khz = 600000 } };
     51 
     52 /**
     53  * dce121_clock_patch_xgmi_ss_info() - Save XGMI spread spectrum info
     54  * @clk_mgr_dce: clock manager internal structure
     55  *
     56  * Reads from VBIOS the XGMI spread spectrum info and saves it within
     57  * the dce clock manager. This operation will overwrite the existing dprefclk
     58  * SS values if the vBIOS query succeeds. Otherwise, it does nothing. It also
     59  * sets the ->xgmi_enabled flag.
     60  */
     61 static void dce121_clock_patch_xgmi_ss_info(struct clk_mgr_internal *clk_mgr_dce)
     62 {
     63 	enum bp_result result;
     64 	struct spread_spectrum_info info = { { 0 } };
     65 	struct dc_bios *bp = clk_mgr_dce->base.ctx->dc_bios;
     66 
     67 	clk_mgr_dce->xgmi_enabled = false;
     68 
     69 	result = bp->funcs->get_spread_spectrum_info(bp, AS_SIGNAL_TYPE_XGMI,
     70 						     0, &info);
     71 	if (result == BP_RESULT_OK && info.spread_spectrum_percentage != 0) {
     72 		clk_mgr_dce->xgmi_enabled = true;
     73 		clk_mgr_dce->ss_on_dprefclk = true;
     74 		clk_mgr_dce->dprefclk_ss_divider =
     75 				info.spread_percentage_divider;
     76 
     77 		if (info.type.CENTER_MODE == 0) {
     78 			/*
     79 			 * Currently for DP Reference clock we
     80 			 * need only SS percentage for
     81 			 * downspread
     82 			 */
     83 			clk_mgr_dce->dprefclk_ss_percentage =
     84 					info.spread_spectrum_percentage;
     85 		}
     86 	}
     87 }
     88 
     89 static void dce12_update_clocks(struct clk_mgr *clk_mgr_base,
     90 			struct dc_state *context,
     91 			bool safe_to_lower)
     92 {
     93 	struct clk_mgr_internal *clk_mgr_dce = TO_CLK_MGR_INTERNAL(clk_mgr_base);
     94 	struct dm_pp_clock_for_voltage_req clock_voltage_req = {0};
     95 	int max_pix_clk = dce_get_max_pixel_clock_for_all_paths(context);
     96 	int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
     97 
     98 	/*TODO: W/A for dal3 linux, investigate why this works */
     99 	if (!clk_mgr_dce->dfs_bypass_active)
    100 		patched_disp_clk = patched_disp_clk * 115 / 100;
    101 
    102 	if (should_set_clock(safe_to_lower, patched_disp_clk, clk_mgr_base->clks.dispclk_khz)) {
    103 		clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAY_CLK;
    104 		/*
    105 		 * When xGMI is enabled, the display clk needs to be adjusted
    106 		 * with the WAFL link's SS percentage.
    107 		 */
    108 		if (clk_mgr_dce->xgmi_enabled)
    109 			patched_disp_clk = dce_adjust_dp_ref_freq_for_ss(
    110 					clk_mgr_dce, patched_disp_clk);
    111 		clock_voltage_req.clocks_in_khz = patched_disp_clk;
    112 		clk_mgr_base->clks.dispclk_khz = dce112_set_clock(clk_mgr_base, patched_disp_clk);
    113 
    114 		dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req);
    115 	}
    116 
    117 	if (should_set_clock(safe_to_lower, max_pix_clk, clk_mgr_base->clks.phyclk_khz)) {
    118 		clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DISPLAYPHYCLK;
    119 		clock_voltage_req.clocks_in_khz = max_pix_clk;
    120 		clk_mgr_base->clks.phyclk_khz = max_pix_clk;
    121 
    122 		dm_pp_apply_clock_for_voltage_request(clk_mgr_base->ctx, &clock_voltage_req);
    123 	}
    124 	dce11_pplib_apply_display_requirements(clk_mgr_base->ctx->dc, context);
    125 }
    126 
    127 
    128 static struct clk_mgr_funcs dce120_funcs = {
    129 	.get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
    130 	.update_clocks = dce12_update_clocks
    131 };
    132 
    133 void dce120_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr)
    134 {
    135 	dce_clk_mgr_construct(ctx, clk_mgr);
    136 
    137 	memcpy(clk_mgr->max_clks_by_state,
    138 		dce120_max_clks_by_state,
    139 		sizeof(dce120_max_clks_by_state));
    140 
    141 	clk_mgr->base.dprefclk_khz = 600000;
    142 	clk_mgr->base.funcs = &dce120_funcs;
    143 }
    144 
    145 void dce121_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr)
    146 {
    147 	dce120_clk_mgr_construct(ctx, clk_mgr);
    148 	clk_mgr->base.dprefclk_khz = 625000;
    149 
    150 	/*
    151 	 * The xGMI enabled info is used to determine if audio and display
    152 	 * clocks need to be adjusted with the WAFL link's SS info.
    153 	 */
    154 	if (dce121_xgmi_enabled(ctx->dc->hwseq))
    155 		dce121_clock_patch_xgmi_ss_info(clk_mgr);
    156 
    157 }
    158 
    159