1 /* $NetBSD: radeon_dce6_afmt.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 #include <sys/cdefs.h> 26 __KERNEL_RCSID(0, "$NetBSD: radeon_dce6_afmt.c,v 1.2 2021/12/18 23:45:43 riastradh Exp $"); 27 28 #include <linux/hdmi.h> 29 30 #include "radeon.h" 31 #include "radeon_audio.h" 32 #include "sid.h" 33 34 #define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8 35 #define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc 36 37 u32 dce6_endpoint_rreg(struct radeon_device *rdev, 38 u32 block_offset, u32 reg) 39 { 40 unsigned long flags; 41 u32 r; 42 43 spin_lock_irqsave(&rdev->end_idx_lock, flags); 44 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 45 r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); 46 spin_unlock_irqrestore(&rdev->end_idx_lock, flags); 47 48 return r; 49 } 50 51 void dce6_endpoint_wreg(struct radeon_device *rdev, 52 u32 block_offset, u32 reg, u32 v) 53 { 54 unsigned long flags; 55 56 spin_lock_irqsave(&rdev->end_idx_lock, flags); 57 if (ASIC_IS_DCE8(rdev)) 58 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); 59 else 60 WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, 61 AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); 62 WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); 63 spin_unlock_irqrestore(&rdev->end_idx_lock, flags); 64 } 65 66 static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) 67 { 68 int i; 69 u32 offset, tmp; 70 71 for (i = 0; i < rdev->audio.num_pins; i++) { 72 offset = rdev->audio.pin[i].offset; 73 tmp = RREG32_ENDPOINT(offset, 74 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 75 if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) 76 rdev->audio.pin[i].connected = false; 77 else 78 rdev->audio.pin[i].connected = true; 79 } 80 } 81 82 struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) 83 { 84 struct drm_encoder *encoder; 85 struct radeon_encoder *radeon_encoder; 86 struct radeon_encoder_atom_dig *dig; 87 struct r600_audio_pin *pin = NULL; 88 int i, pin_count; 89 90 dce6_afmt_get_connected_pins(rdev); 91 92 for (i = 0; i < rdev->audio.num_pins; i++) { 93 if (rdev->audio.pin[i].connected) { 94 pin = &rdev->audio.pin[i]; 95 pin_count = 0; 96 97 list_for_each_entry(encoder, &rdev->ddev->mode_config.encoder_list, head) { 98 if (radeon_encoder_is_digital(encoder)) { 99 radeon_encoder = to_radeon_encoder(encoder); 100 dig = radeon_encoder->enc_priv; 101 if (dig->pin == pin) 102 pin_count++; 103 } 104 } 105 106 if (pin_count == 0) 107 return pin; 108 } 109 } 110 if (!pin) 111 DRM_ERROR("No connected audio pins found!\n"); 112 return pin; 113 } 114 115 void dce6_afmt_select_pin(struct drm_encoder *encoder) 116 { 117 struct radeon_device *rdev = encoder->dev->dev_private; 118 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 119 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 120 121 if (!dig || !dig->afmt || !dig->pin) 122 return; 123 124 WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, 125 AFMT_AUDIO_SRC_SELECT(dig->pin->id)); 126 } 127 128 void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, 129 struct drm_connector *connector, 130 struct drm_display_mode *mode) 131 { 132 struct radeon_device *rdev = encoder->dev->dev_private; 133 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 134 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 135 u32 tmp = 0; 136 137 if (!dig || !dig->afmt || !dig->pin) 138 return; 139 140 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 141 if (connector->latency_present[1]) 142 tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | 143 AUDIO_LIPSYNC(connector->audio_latency[1]); 144 else 145 tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); 146 } else { 147 if (connector->latency_present[0]) 148 tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | 149 AUDIO_LIPSYNC(connector->audio_latency[0]); 150 else 151 tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); 152 } 153 WREG32_ENDPOINT(dig->pin->offset, 154 AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); 155 } 156 157 void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, 158 u8 *sadb, int sad_count) 159 { 160 struct radeon_device *rdev = encoder->dev->dev_private; 161 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 162 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 163 u32 tmp; 164 165 if (!dig || !dig->afmt || !dig->pin) 166 return; 167 168 /* program the speaker allocation */ 169 tmp = RREG32_ENDPOINT(dig->pin->offset, 170 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 171 tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); 172 /* set HDMI mode */ 173 tmp |= HDMI_CONNECTION; 174 if (sad_count) 175 tmp |= SPEAKER_ALLOCATION(sadb[0]); 176 else 177 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 178 WREG32_ENDPOINT(dig->pin->offset, 179 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 180 } 181 182 void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, 183 u8 *sadb, int sad_count) 184 { 185 struct radeon_device *rdev = encoder->dev->dev_private; 186 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 187 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 188 u32 tmp; 189 190 if (!dig || !dig->afmt || !dig->pin) 191 return; 192 193 /* program the speaker allocation */ 194 tmp = RREG32_ENDPOINT(dig->pin->offset, 195 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 196 tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); 197 /* set DP mode */ 198 tmp |= DP_CONNECTION; 199 if (sad_count) 200 tmp |= SPEAKER_ALLOCATION(sadb[0]); 201 else 202 tmp |= SPEAKER_ALLOCATION(5); /* stereo */ 203 WREG32_ENDPOINT(dig->pin->offset, 204 AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); 205 } 206 207 void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, 208 struct cea_sad *sads, int sad_count) 209 { 210 int i; 211 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 212 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 213 struct radeon_device *rdev = encoder->dev->dev_private; 214 static const u16 eld_reg_to_type[][2] = { 215 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, 216 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, 217 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, 218 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, 219 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, 220 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, 221 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, 222 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, 223 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, 224 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, 225 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, 226 { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, 227 }; 228 229 if (!dig || !dig->afmt || !dig->pin) 230 return; 231 232 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { 233 u32 value = 0; 234 u8 stereo_freqs = 0; 235 int max_channels = -1; 236 int j; 237 238 for (j = 0; j < sad_count; j++) { 239 struct cea_sad *sad = &sads[j]; 240 241 if (sad->format == eld_reg_to_type[i][1]) { 242 if (sad->channels > max_channels) { 243 value = MAX_CHANNELS(sad->channels) | 244 DESCRIPTOR_BYTE_2(sad->byte2) | 245 SUPPORTED_FREQUENCIES(sad->freq); 246 max_channels = sad->channels; 247 } 248 249 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) 250 stereo_freqs |= sad->freq; 251 else 252 break; 253 } 254 } 255 256 value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); 257 258 WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value); 259 } 260 } 261 262 void dce6_audio_enable(struct radeon_device *rdev, 263 struct r600_audio_pin *pin, 264 u8 enable_mask) 265 { 266 if (!pin) 267 return; 268 269 WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 270 enable_mask ? AUDIO_ENABLED : 0); 271 } 272 273 void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, 274 struct radeon_crtc *crtc, unsigned int clock) 275 { 276 /* Two dtos; generally use dto0 for HDMI */ 277 u32 value = 0; 278 279 if (crtc) 280 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); 281 282 WREG32(DCCG_AUDIO_DTO_SOURCE, value); 283 284 /* Express [24MHz / target pixel clock] as an exact rational 285 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 286 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 287 */ 288 WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); 289 WREG32(DCCG_AUDIO_DTO0_MODULE, clock); 290 } 291 292 void dce6_dp_audio_set_dto(struct radeon_device *rdev, 293 struct radeon_crtc *crtc, unsigned int clock) 294 { 295 /* Two dtos; generally use dto1 for DP */ 296 u32 value = 0; 297 value |= DCCG_AUDIO_DTO_SEL; 298 299 if (crtc) 300 value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); 301 302 WREG32(DCCG_AUDIO_DTO_SOURCE, value); 303 304 /* Express [24MHz / target pixel clock] as an exact rational 305 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE 306 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator 307 */ 308 if (ASIC_IS_DCE8(rdev)) { 309 unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) & 310 DENTIST_DPREFCLK_WDIVIDER_MASK) >> 311 DENTIST_DPREFCLK_WDIVIDER_SHIFT; 312 div = radeon_audio_decode_dfs_div(div); 313 314 if (div) 315 clock = clock * 100 / div; 316 317 WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); 318 WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); 319 } else { 320 WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); 321 WREG32(DCCG_AUDIO_DTO1_MODULE, clock); 322 } 323 } 324
Indexes created Sun Sep 21 19:09:51 GMT 2025