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      1 /*	$NetBSD: amdgpu_dce80_hw_sequencer.c,v 1.3 2021/12/19 11:23:00 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2015 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: AMD
     25  *
     26  */
     27 
     28 #include <sys/cdefs.h>
     29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce80_hw_sequencer.c,v 1.3 2021/12/19 11:23:00 riastradh Exp $");
     30 
     31 #include "dm_services.h"
     32 #include "dc.h"
     33 #include "core_types.h"
     34 #include "dce80_hw_sequencer.h"
     35 
     36 #include "dce/dce_hwseq.h"
     37 #include "dce110/dce110_hw_sequencer.h"
     38 #include "dce100/dce100_hw_sequencer.h"
     39 
     40 /* include DCE8 register header files */
     41 #include "dce/dce_8_0_d.h"
     42 #include "dce/dce_8_0_sh_mask.h"
     43 
     44 struct dce80_hw_seq_reg_offsets {
     45 	uint32_t crtc;
     46 };
     47 
     48 static const struct dce80_hw_seq_reg_offsets reg_offsets[] __unused = {
     49 {
     50 	.crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     51 },
     52 {
     53 	.crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     54 },
     55 {
     56 	.crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     57 },
     58 {
     59 	.crtc = (mmCRTC3_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     60 },
     61 {
     62 	.crtc = (mmCRTC4_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     63 },
     64 {
     65 	.crtc = (mmCRTC5_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
     66 }
     67 };
     68 
     69 #define HW_REG_CRTC(reg, id)\
     70 	(reg + reg_offsets[id].crtc)
     71 
     72 /*******************************************************************************
     73  * Private definitions
     74  ******************************************************************************/
     75 
     76 /***************************PIPE_CONTROL***********************************/
     77 
     78 void dce80_hw_sequencer_construct(struct dc *dc)
     79 {
     80 	dce110_hw_sequencer_construct(dc);
     81 
     82 	dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
     83 	dc->hwss.pipe_control_lock = dce_pipe_control_lock;
     84 	dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
     85 	dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
     86 }
     87 
     88