1 /* $NetBSD: dce_abm.h,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-16 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 29 #ifndef _DCE_ABM_H_ 30 #define _DCE_ABM_H_ 31 32 #include "abm.h" 33 34 #define ABM_COMMON_REG_LIST_DCE_BASE() \ 35 SR(BL_PWM_PERIOD_CNTL), \ 36 SR(BL_PWM_CNTL), \ 37 SR(BL_PWM_CNTL2), \ 38 SR(BL_PWM_GRP1_REG_LOCK), \ 39 SR(LVTMA_PWRSEQ_REF_DIV), \ 40 SR(MASTER_COMM_CNTL_REG), \ 41 SR(MASTER_COMM_CMD_REG), \ 42 SR(MASTER_COMM_DATA_REG1) 43 44 #define ABM_DCE110_COMMON_REG_LIST() \ 45 ABM_COMMON_REG_LIST_DCE_BASE(), \ 46 SR(DC_ABM1_HG_SAMPLE_RATE), \ 47 SR(DC_ABM1_LS_SAMPLE_RATE), \ 48 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 49 SR(DC_ABM1_HG_MISC_CTRL), \ 50 SR(DC_ABM1_IPCSC_COEFF_SEL), \ 51 SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 52 SR(BL1_PWM_TARGET_ABM_LEVEL), \ 53 SR(BL1_PWM_USER_LEVEL), \ 54 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ 55 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ 56 SR(BIOS_SCRATCH_2) 57 58 #define ABM_DCN10_REG_LIST(id)\ 59 ABM_COMMON_REG_LIST_DCE_BASE(), \ 60 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \ 61 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \ 62 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \ 63 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \ 64 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \ 65 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \ 66 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \ 67 SRI(BL1_PWM_USER_LEVEL, ABM, id), \ 68 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \ 69 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \ 70 NBIO_SR(BIOS_SCRATCH_2) 71 72 #define ABM_DCN20_REG_LIST() \ 73 ABM_COMMON_REG_LIST_DCE_BASE(), \ 74 SR(DC_ABM1_HG_SAMPLE_RATE), \ 75 SR(DC_ABM1_LS_SAMPLE_RATE), \ 76 SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \ 77 SR(DC_ABM1_HG_MISC_CTRL), \ 78 SR(DC_ABM1_IPCSC_COEFF_SEL), \ 79 SR(BL1_PWM_CURRENT_ABM_LEVEL), \ 80 SR(BL1_PWM_TARGET_ABM_LEVEL), \ 81 SR(BL1_PWM_USER_LEVEL), \ 82 SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \ 83 SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \ 84 NBIO_SR(BIOS_SCRATCH_2) 85 86 #define ABM_SF(reg_name, field_name, post_fix)\ 87 .field_name = reg_name ## __ ## field_name ## post_fix 88 89 #define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 90 ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD, mask_sh), \ 91 ABM_SF(BL_PWM_PERIOD_CNTL, BL_PWM_PERIOD_BITCNT, mask_sh), \ 92 ABM_SF(BL_PWM_CNTL, BL_ACTIVE_INT_FRAC_CNT, mask_sh), \ 93 ABM_SF(BL_PWM_CNTL, BL_PWM_FRACTIONAL_EN, mask_sh), \ 94 ABM_SF(BL_PWM_CNTL, BL_PWM_EN, mask_sh), \ 95 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN, mask_sh), \ 96 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_LOCK, mask_sh), \ 97 ABM_SF(BL_PWM_GRP1_REG_LOCK, BL_PWM_GRP1_REG_UPDATE_PENDING, mask_sh), \ 98 ABM_SF(LVTMA_PWRSEQ_REF_DIV, BL_PWM_REF_DIV, mask_sh), \ 99 ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 100 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 101 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \ 102 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh) 103 104 #define ABM_MASK_SH_LIST_DCE110(mask_sh) \ 105 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 106 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 107 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 108 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 109 ABM1_HG_VMAX_SEL, mask_sh), \ 110 ABM_SF(DC_ABM1_HG_MISC_CTRL, \ 111 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 112 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 113 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 114 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 115 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 116 ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \ 117 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 118 ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \ 119 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 120 ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \ 121 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 122 ABM_SF(BL1_PWM_USER_LEVEL, \ 123 BL1_PWM_USER_LEVEL, mask_sh), \ 124 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 125 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 126 ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 127 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 128 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 129 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 130 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 131 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 132 ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \ 133 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 134 135 #define ABM_MASK_SH_LIST_DCN10(mask_sh) \ 136 ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 137 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 138 ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \ 139 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 140 ABM1_HG_VMAX_SEL, mask_sh), \ 141 ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \ 142 ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \ 143 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 144 ABM1_IPCSC_COEFF_SEL_R, mask_sh), \ 145 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 146 ABM1_IPCSC_COEFF_SEL_G, mask_sh), \ 147 ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \ 148 ABM1_IPCSC_COEFF_SEL_B, mask_sh), \ 149 ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \ 150 BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \ 151 ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \ 152 BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \ 153 ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \ 154 BL1_PWM_USER_LEVEL, mask_sh), \ 155 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 156 ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \ 157 ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \ 158 ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \ 159 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 160 ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 161 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 162 ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \ 163 ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \ 164 ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh) 165 166 #define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh) 167 168 #define ABM_REG_FIELD_LIST(type) \ 169 type ABM1_HG_NUM_OF_BINS_SEL; \ 170 type ABM1_HG_VMAX_SEL; \ 171 type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \ 172 type ABM1_IPCSC_COEFF_SEL_R; \ 173 type ABM1_IPCSC_COEFF_SEL_G; \ 174 type ABM1_IPCSC_COEFF_SEL_B; \ 175 type BL1_PWM_CURRENT_ABM_LEVEL; \ 176 type BL1_PWM_TARGET_ABM_LEVEL; \ 177 type BL1_PWM_USER_LEVEL; \ 178 type ABM1_LS_MIN_PIXEL_VALUE_THRES; \ 179 type ABM1_LS_MAX_PIXEL_VALUE_THRES; \ 180 type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \ 181 type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \ 182 type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \ 183 type BL_PWM_PERIOD; \ 184 type BL_PWM_PERIOD_BITCNT; \ 185 type BL_ACTIVE_INT_FRAC_CNT; \ 186 type BL_PWM_FRACTIONAL_EN; \ 187 type MASTER_COMM_INTERRUPT; \ 188 type MASTER_COMM_CMD_REG_BYTE0; \ 189 type MASTER_COMM_CMD_REG_BYTE1; \ 190 type MASTER_COMM_CMD_REG_BYTE2; \ 191 type BL_PWM_REF_DIV; \ 192 type BL_PWM_EN; \ 193 type BL_PWM_GRP1_IGNORE_MASTER_LOCK_EN; \ 194 type BL_PWM_GRP1_REG_LOCK; \ 195 type BL_PWM_GRP1_REG_UPDATE_PENDING 196 197 struct dce_abm_shift { 198 ABM_REG_FIELD_LIST(uint8_t); 199 }; 200 201 struct dce_abm_mask { 202 ABM_REG_FIELD_LIST(uint32_t); 203 }; 204 205 struct dce_abm_registers { 206 uint32_t BL_PWM_PERIOD_CNTL; 207 uint32_t BL_PWM_CNTL; 208 uint32_t BL_PWM_CNTL2; 209 uint32_t LVTMA_PWRSEQ_REF_DIV; 210 uint32_t DC_ABM1_HG_SAMPLE_RATE; 211 uint32_t DC_ABM1_LS_SAMPLE_RATE; 212 uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE; 213 uint32_t DC_ABM1_HG_MISC_CTRL; 214 uint32_t DC_ABM1_IPCSC_COEFF_SEL; 215 uint32_t BL1_PWM_CURRENT_ABM_LEVEL; 216 uint32_t BL1_PWM_TARGET_ABM_LEVEL; 217 uint32_t BL1_PWM_USER_LEVEL; 218 uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES; 219 uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS; 220 uint32_t MASTER_COMM_CNTL_REG; 221 uint32_t MASTER_COMM_CMD_REG; 222 uint32_t MASTER_COMM_DATA_REG1; 223 uint32_t BIOS_SCRATCH_2; 224 uint32_t BL_PWM_GRP1_REG_LOCK; 225 }; 226 227 struct dce_abm { 228 struct abm base; 229 const struct dce_abm_registers *regs; 230 const struct dce_abm_shift *abm_shift; 231 const struct dce_abm_mask *abm_mask; 232 }; 233 234 struct abm *dce_abm_create( 235 struct dc_context *ctx, 236 const struct dce_abm_registers *regs, 237 const struct dce_abm_shift *abm_shift, 238 const struct dce_abm_mask *abm_mask); 239 240 void dce_abm_destroy(struct abm **abm); 241 242 #endif /* _DCE_ABM_H_ */ 243
Indexes created Sat Sep 20 22:09:52 GMT 2025