1 /* $NetBSD: amdgpu_dce_audio.c,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dce_audio.c,v 1.2 2021/12/18 23:45:02 riastradh Exp $"); 30 31 #include <linux/slab.h> 32 33 #include "reg_helper.h" 34 #include "dce_audio.h" 35 #include "dce/dce_11_0_d.h" 36 #include "dce/dce_11_0_sh_mask.h" 37 38 #define DCE_AUD(audio)\ 39 container_of(audio, struct dce_audio, base) 40 41 #define CTX \ 42 aud->base.ctx 43 44 #define DC_LOGGER_INIT() 45 46 #define REG(reg)\ 47 (aud->regs->reg) 48 49 #undef FN 50 #define FN(reg_name, field_name) \ 51 aud->shifts->field_name, aud->masks->field_name 52 53 #define IX_REG(reg)\ 54 ix ## reg 55 56 #define AZ_REG_READ(reg_name) \ 57 read_indirect_azalia_reg(audio, IX_REG(reg_name)) 58 59 #define AZ_REG_WRITE(reg_name, value) \ 60 write_indirect_azalia_reg(audio, IX_REG(reg_name), value) 61 62 static void write_indirect_azalia_reg(struct audio *audio, 63 uint32_t reg_index, 64 uint32_t reg_data) 65 { 66 struct dce_audio *aud = DCE_AUD(audio); 67 68 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 69 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 70 AZALIA_ENDPOINT_REG_INDEX, reg_index); 71 72 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 73 REG_SET(AZALIA_F0_CODEC_ENDPOINT_DATA, 0, 74 AZALIA_ENDPOINT_REG_DATA, reg_data); 75 76 DC_LOG_HW_AUDIO("AUDIO:write_indirect_azalia_reg: index: %u data: %u\n", 77 reg_index, reg_data); 78 } 79 80 static uint32_t read_indirect_azalia_reg(struct audio *audio, uint32_t reg_index) 81 { 82 struct dce_audio *aud = DCE_AUD(audio); 83 84 uint32_t value = 0; 85 86 /* AZALIA_F0_CODEC_ENDPOINT_INDEX endpoint index */ 87 REG_SET(AZALIA_F0_CODEC_ENDPOINT_INDEX, 0, 88 AZALIA_ENDPOINT_REG_INDEX, reg_index); 89 90 /* AZALIA_F0_CODEC_ENDPOINT_DATA endpoint data */ 91 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); 92 93 DC_LOG_HW_AUDIO("AUDIO:read_indirect_azalia_reg: index: %u data: %u\n", 94 reg_index, value); 95 96 return value; 97 } 98 99 static bool is_audio_format_supported( 100 const struct audio_info *audio_info, 101 enum audio_format_code audio_format_code, 102 uint32_t *format_index) 103 { 104 uint32_t index; 105 uint32_t max_channe_index = 0; 106 bool found = false; 107 108 if (audio_info == NULL) 109 return found; 110 111 /* pass through whole array */ 112 for (index = 0; index < audio_info->mode_count; index++) { 113 if (audio_info->modes[index].format_code == audio_format_code) { 114 if (found) { 115 /* format has multiply entries, choose one with 116 * highst number of channels */ 117 if (audio_info->modes[index].channel_count > 118 audio_info->modes[max_channe_index].channel_count) { 119 max_channe_index = index; 120 } 121 } else { 122 /* format found, save it's index */ 123 found = true; 124 max_channe_index = index; 125 } 126 } 127 } 128 129 /* return index */ 130 if (found && format_index != NULL) 131 *format_index = max_channe_index; 132 133 return found; 134 } 135 136 /*For HDMI, calculate if specified sample rates can fit into a given timing */ 137 static void check_audio_bandwidth_hdmi( 138 const struct audio_crtc_info *crtc_info, 139 uint32_t channel_count, 140 union audio_sample_rates *sample_rates) 141 { 142 uint32_t samples; 143 uint32_t h_blank; 144 bool limit_freq_to_48_khz = false; 145 bool limit_freq_to_88_2_khz = false; 146 bool limit_freq_to_96_khz = false; 147 bool limit_freq_to_174_4_khz = false; 148 149 /* For two channels supported return whatever sink support,unmodified*/ 150 if (channel_count > 2) { 151 152 /* Based on HDMI spec 1.3 Table 7.5 */ 153 if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 154 (crtc_info->v_active <= 576) && 155 !(crtc_info->interlaced) && 156 !(crtc_info->pixel_repetition == 2 || 157 crtc_info->pixel_repetition == 4)) { 158 limit_freq_to_48_khz = true; 159 160 } else if ((crtc_info->requested_pixel_clock_100Hz <= 270000) && 161 (crtc_info->v_active <= 576) && 162 (crtc_info->interlaced) && 163 (crtc_info->pixel_repetition == 2)) { 164 limit_freq_to_88_2_khz = true; 165 166 } else if ((crtc_info->requested_pixel_clock_100Hz <= 540000) && 167 (crtc_info->v_active <= 576) && 168 !(crtc_info->interlaced)) { 169 limit_freq_to_174_4_khz = true; 170 } 171 } 172 173 /* Also do some calculation for the available Audio Bandwidth for the 174 * 8 ch (i.e. for the Layout 1 => ch > 2) 175 */ 176 h_blank = crtc_info->h_total - crtc_info->h_active; 177 178 if (crtc_info->pixel_repetition) 179 h_blank *= crtc_info->pixel_repetition; 180 181 /*based on HDMI spec 1.3 Table 7.5 */ 182 h_blank -= 58; 183 /*for Control Period */ 184 h_blank -= 16; 185 186 samples = h_blank * 10; 187 /* Number of Audio Packets (multiplied by 10) per Line (for 8 ch number 188 * of Audio samples per line multiplied by 10 - Layout 1) 189 */ 190 samples /= 32; 191 samples *= crtc_info->v_active; 192 /*Number of samples multiplied by 10, per second */ 193 samples *= crtc_info->refresh_rate; 194 /*Number of Audio samples per second */ 195 samples /= 10; 196 197 /* @todo do it after deep color is implemented 198 * 8xx - deep color bandwidth scaling 199 * Extra bandwidth is avaliable in deep color b/c link runs faster than 200 * pixel rate. This has the effect of allowing more tmds characters to 201 * be transmitted during blank 202 */ 203 204 switch (crtc_info->color_depth) { 205 case COLOR_DEPTH_888: 206 samples *= 4; 207 break; 208 case COLOR_DEPTH_101010: 209 samples *= 5; 210 break; 211 case COLOR_DEPTH_121212: 212 samples *= 6; 213 break; 214 default: 215 samples *= 4; 216 break; 217 } 218 219 samples /= 4; 220 221 /*check limitation*/ 222 if (samples < 88200) 223 limit_freq_to_48_khz = true; 224 else if (samples < 96000) 225 limit_freq_to_88_2_khz = true; 226 else if (samples < 176400) 227 limit_freq_to_96_khz = true; 228 else if (samples < 192000) 229 limit_freq_to_174_4_khz = true; 230 231 if (sample_rates != NULL) { 232 /* limit frequencies */ 233 if (limit_freq_to_174_4_khz) 234 sample_rates->rate.RATE_192 = 0; 235 236 if (limit_freq_to_96_khz) { 237 sample_rates->rate.RATE_192 = 0; 238 sample_rates->rate.RATE_176_4 = 0; 239 } 240 if (limit_freq_to_88_2_khz) { 241 sample_rates->rate.RATE_192 = 0; 242 sample_rates->rate.RATE_176_4 = 0; 243 sample_rates->rate.RATE_96 = 0; 244 } 245 if (limit_freq_to_48_khz) { 246 sample_rates->rate.RATE_192 = 0; 247 sample_rates->rate.RATE_176_4 = 0; 248 sample_rates->rate.RATE_96 = 0; 249 sample_rates->rate.RATE_88_2 = 0; 250 } 251 } 252 } 253 254 /*For DP SST, calculate if specified sample rates can fit into a given timing */ 255 static void check_audio_bandwidth_dpsst( 256 const struct audio_crtc_info *crtc_info, 257 uint32_t channel_count, 258 union audio_sample_rates *sample_rates) 259 { 260 /* do nothing */ 261 } 262 263 /*For DP MST, calculate if specified sample rates can fit into a given timing */ 264 static void check_audio_bandwidth_dpmst( 265 const struct audio_crtc_info *crtc_info, 266 uint32_t channel_count, 267 union audio_sample_rates *sample_rates) 268 { 269 /* do nothing */ 270 } 271 272 static void check_audio_bandwidth( 273 const struct audio_crtc_info *crtc_info, 274 uint32_t channel_count, 275 enum signal_type signal, 276 union audio_sample_rates *sample_rates) 277 { 278 switch (signal) { 279 case SIGNAL_TYPE_HDMI_TYPE_A: 280 check_audio_bandwidth_hdmi( 281 crtc_info, channel_count, sample_rates); 282 break; 283 case SIGNAL_TYPE_EDP: 284 case SIGNAL_TYPE_DISPLAY_PORT: 285 check_audio_bandwidth_dpsst( 286 crtc_info, channel_count, sample_rates); 287 break; 288 case SIGNAL_TYPE_DISPLAY_PORT_MST: 289 check_audio_bandwidth_dpmst( 290 crtc_info, channel_count, sample_rates); 291 break; 292 default: 293 break; 294 } 295 } 296 297 /* expose/not expose HBR capability to Audio driver */ 298 static void set_high_bit_rate_capable( 299 struct audio *audio, 300 bool capable) 301 { 302 uint32_t value = 0; 303 304 /* set high bit rate audio capable*/ 305 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); 306 307 set_reg_field_value(value, capable, 308 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, 309 HBR_CAPABLE); 310 311 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); 312 } 313 314 /* set video latency in in ms/2+1 */ 315 static void set_video_latency( 316 struct audio *audio, 317 int latency_in_ms) 318 { 319 uint32_t value = 0; 320 321 if ((latency_in_ms < 0) || (latency_in_ms > 255)) 322 return; 323 324 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 325 326 set_reg_field_value(value, latency_in_ms, 327 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 328 VIDEO_LIPSYNC); 329 330 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 331 value); 332 } 333 334 /* set audio latency in in ms/2+1 */ 335 static void set_audio_latency( 336 struct audio *audio, 337 int latency_in_ms) 338 { 339 uint32_t value = 0; 340 341 if (latency_in_ms < 0) 342 latency_in_ms = 0; 343 344 if (latency_in_ms > 255) 345 latency_in_ms = 255; 346 347 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC); 348 349 set_reg_field_value(value, latency_in_ms, 350 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 351 AUDIO_LIPSYNC); 352 353 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, 354 value); 355 } 356 357 void dce_aud_az_enable(struct audio *audio) 358 { 359 uint32_t value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 360 DC_LOGGER_INIT(); 361 362 set_reg_field_value(value, 1, 363 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 364 CLOCK_GATING_DISABLE); 365 set_reg_field_value(value, 1, 366 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 367 AUDIO_ENABLED); 368 369 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 370 set_reg_field_value(value, 0, 371 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 372 CLOCK_GATING_DISABLE); 373 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 374 375 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_enable: index: %u data: 0x%x\n", 376 audio->inst, value); 377 } 378 379 void dce_aud_az_disable(struct audio *audio) 380 { 381 uint32_t value; 382 DC_LOGGER_INIT(); 383 384 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 385 set_reg_field_value(value, 1, 386 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 387 CLOCK_GATING_DISABLE); 388 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 389 390 set_reg_field_value(value, 0, 391 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 392 AUDIO_ENABLED); 393 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 394 395 set_reg_field_value(value, 0, 396 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 397 CLOCK_GATING_DISABLE); 398 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 399 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 400 DC_LOG_HW_AUDIO("\n\t========= AUDIO:dce_aud_az_disable: index: %u data: 0x%x\n", 401 audio->inst, value); 402 } 403 404 void dce_aud_az_configure( 405 struct audio *audio, 406 enum signal_type signal, 407 const struct audio_crtc_info *crtc_info, 408 const struct audio_info *audio_info) 409 { 410 struct dce_audio *aud = DCE_AUD(audio); 411 412 uint32_t speakers = audio_info->flags.info.ALLSPEAKERS; 413 uint32_t value; 414 uint32_t field = 0; 415 enum audio_format_code audio_format_code; 416 uint32_t format_index; 417 uint32_t index; 418 bool is_ac3_supported = false; 419 union audio_sample_rates sample_rate; 420 uint32_t strlen = 0; 421 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 422 set_reg_field_value(value, 1, 423 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 424 CLOCK_GATING_DISABLE); 425 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 426 427 /* Speaker Allocation */ 428 /* 429 uint32_t value; 430 uint32_t field = 0;*/ 431 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); 432 433 set_reg_field_value(value, 434 speakers, 435 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 436 SPEAKER_ALLOCATION); 437 438 /* LFE_PLAYBACK_LEVEL = LFEPBL 439 * LFEPBL = 0 : Unknown or refer to other information 440 * LFEPBL = 1 : 0dB playback 441 * LFEPBL = 2 : +10dB playback 442 * LFE_BL = 3 : Reserved 443 */ 444 set_reg_field_value(value, 445 0, 446 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 447 LFE_PLAYBACK_LEVEL); 448 /* todo: according to reg spec LFE_PLAYBACK_LEVEL is read only. 449 * why are we writing to it? DCE8 does not write this */ 450 451 452 set_reg_field_value(value, 453 0, 454 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 455 HDMI_CONNECTION); 456 457 set_reg_field_value(value, 458 0, 459 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 460 DP_CONNECTION); 461 462 field = get_reg_field_value(value, 463 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 464 EXTRA_CONNECTION_INFO); 465 466 field &= ~0x1; 467 468 set_reg_field_value(value, 469 field, 470 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 471 EXTRA_CONNECTION_INFO); 472 473 /* set audio for output signal */ 474 switch (signal) { 475 case SIGNAL_TYPE_HDMI_TYPE_A: 476 set_reg_field_value(value, 477 1, 478 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 479 HDMI_CONNECTION); 480 481 break; 482 483 case SIGNAL_TYPE_EDP: 484 case SIGNAL_TYPE_DISPLAY_PORT: 485 case SIGNAL_TYPE_DISPLAY_PORT_MST: 486 set_reg_field_value(value, 487 1, 488 AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, 489 DP_CONNECTION); 490 break; 491 default: 492 BREAK_TO_DEBUGGER(); 493 break; 494 } 495 496 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, value); 497 498 /* Audio Descriptors */ 499 /* pass through all formats */ 500 for (format_index = 0; format_index < AUDIO_FORMAT_CODE_COUNT; 501 format_index++) { 502 audio_format_code = 503 (AUDIO_FORMAT_CODE_FIRST + format_index); 504 505 /* those are unsupported, skip programming */ 506 if (audio_format_code == AUDIO_FORMAT_CODE_1BITAUDIO || 507 audio_format_code == AUDIO_FORMAT_CODE_DST) 508 continue; 509 510 value = 0; 511 512 /* check if supported */ 513 if (is_audio_format_supported( 514 audio_info, audio_format_code, &index)) { 515 const struct audio_mode *audio_mode = 516 &audio_info->modes[index]; 517 union audio_sample_rates sample_rates = 518 audio_mode->sample_rates; 519 uint8_t byte2 = audio_mode->max_bit_rate; 520 521 /* adjust specific properties */ 522 switch (audio_format_code) { 523 case AUDIO_FORMAT_CODE_LINEARPCM: { 524 check_audio_bandwidth( 525 crtc_info, 526 audio_mode->channel_count, 527 signal, 528 &sample_rates); 529 530 byte2 = audio_mode->sample_size; 531 532 set_reg_field_value(value, 533 sample_rates.all, 534 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 535 SUPPORTED_FREQUENCIES_STEREO); 536 } 537 break; 538 case AUDIO_FORMAT_CODE_AC3: 539 is_ac3_supported = true; 540 break; 541 case AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS: 542 case AUDIO_FORMAT_CODE_DTS_HD: 543 case AUDIO_FORMAT_CODE_MAT_MLP: 544 case AUDIO_FORMAT_CODE_DST: 545 case AUDIO_FORMAT_CODE_WMAPRO: 546 byte2 = audio_mode->vendor_specific; 547 break; 548 default: 549 break; 550 } 551 552 /* fill audio format data */ 553 set_reg_field_value(value, 554 audio_mode->channel_count - 1, 555 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 556 MAX_CHANNELS); 557 558 set_reg_field_value(value, 559 sample_rates.all, 560 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 561 SUPPORTED_FREQUENCIES); 562 563 set_reg_field_value(value, 564 byte2, 565 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, 566 DESCRIPTOR_BYTE_2); 567 } /* if */ 568 569 AZ_REG_WRITE( 570 AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 + format_index, 571 value); 572 } /* for */ 573 574 if (is_ac3_supported) 575 /* todo: this reg global. why program global register? */ 576 REG_WRITE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS, 577 0x05); 578 579 /* check for 192khz/8-Ch support for HBR requirements */ 580 sample_rate.all = 0; 581 sample_rate.rate.RATE_192 = 1; 582 583 check_audio_bandwidth( 584 crtc_info, 585 8, 586 signal, 587 &sample_rate); 588 589 set_high_bit_rate_capable(audio, sample_rate.rate.RATE_192); 590 591 /* Audio and Video Lipsync */ 592 set_video_latency(audio, audio_info->video_latency); 593 set_audio_latency(audio, audio_info->audio_latency); 594 595 value = 0; 596 set_reg_field_value(value, audio_info->manufacture_id, 597 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 598 MANUFACTURER_ID); 599 600 set_reg_field_value(value, audio_info->product_id, 601 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 602 PRODUCT_ID); 603 604 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0, 605 value); 606 607 value = 0; 608 609 /*get display name string length */ 610 while (audio_info->display_name[strlen++] != '\0') { 611 if (strlen >= 612 MAX_HW_AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS) 613 break; 614 } 615 set_reg_field_value(value, strlen, 616 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 617 SINK_DESCRIPTION_LEN); 618 619 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1, 620 value); 621 DC_LOG_HW_AUDIO("\n\tAUDIO:az_configure: index: %u data, 0x%x, displayName %s: \n", 622 audio->inst, value, audio_info->display_name); 623 624 /* 625 *write the port ID: 626 *PORT_ID0 = display index 627 *PORT_ID1 = 16bit BDF 628 *(format MSB->LSB: 8bit Bus, 5bit Device, 3bit Function) 629 */ 630 631 value = 0; 632 633 set_reg_field_value(value, audio_info->port_id[0], 634 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, 635 PORT_ID0); 636 637 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2, value); 638 639 value = 0; 640 set_reg_field_value(value, audio_info->port_id[1], 641 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, 642 PORT_ID1); 643 644 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3, value); 645 646 /*write the 18 char monitor string */ 647 648 value = 0; 649 set_reg_field_value(value, audio_info->display_name[0], 650 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 651 DESCRIPTION0); 652 653 set_reg_field_value(value, audio_info->display_name[1], 654 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 655 DESCRIPTION1); 656 657 set_reg_field_value(value, audio_info->display_name[2], 658 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 659 DESCRIPTION2); 660 661 set_reg_field_value(value, audio_info->display_name[3], 662 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, 663 DESCRIPTION3); 664 665 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4, value); 666 667 value = 0; 668 set_reg_field_value(value, audio_info->display_name[4], 669 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 670 DESCRIPTION4); 671 672 set_reg_field_value(value, audio_info->display_name[5], 673 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 674 DESCRIPTION5); 675 676 set_reg_field_value(value, audio_info->display_name[6], 677 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 678 DESCRIPTION6); 679 680 set_reg_field_value(value, audio_info->display_name[7], 681 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, 682 DESCRIPTION7); 683 684 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5, value); 685 686 value = 0; 687 set_reg_field_value(value, audio_info->display_name[8], 688 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 689 DESCRIPTION8); 690 691 set_reg_field_value(value, audio_info->display_name[9], 692 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 693 DESCRIPTION9); 694 695 set_reg_field_value(value, audio_info->display_name[10], 696 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 697 DESCRIPTION10); 698 699 set_reg_field_value(value, audio_info->display_name[11], 700 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, 701 DESCRIPTION11); 702 703 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6, value); 704 705 value = 0; 706 set_reg_field_value(value, audio_info->display_name[12], 707 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 708 DESCRIPTION12); 709 710 set_reg_field_value(value, audio_info->display_name[13], 711 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 712 DESCRIPTION13); 713 714 set_reg_field_value(value, audio_info->display_name[14], 715 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 716 DESCRIPTION14); 717 718 set_reg_field_value(value, audio_info->display_name[15], 719 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, 720 DESCRIPTION15); 721 722 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7, value); 723 724 value = 0; 725 set_reg_field_value(value, audio_info->display_name[16], 726 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 727 DESCRIPTION16); 728 729 set_reg_field_value(value, audio_info->display_name[17], 730 AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, 731 DESCRIPTION17); 732 733 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8, value); 734 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 735 set_reg_field_value(value, 0, 736 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 737 CLOCK_GATING_DISABLE); 738 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 739 } 740 741 /* 742 * todo: wall clk related functionality probably belong to clock_src. 743 */ 744 745 /* search pixel clock value for Azalia HDMI Audio */ 746 static void get_azalia_clock_info_hdmi( 747 uint32_t crtc_pixel_clock_100hz, 748 uint32_t actual_pixel_clock_100Hz, 749 struct azalia_clock_info *azalia_clock_info) 750 { 751 /* audio_dto_phase= 24 * 10,000; 752 * 24MHz in [100Hz] units */ 753 azalia_clock_info->audio_dto_phase = 754 24 * 10000; 755 756 /* audio_dto_module = PCLKFrequency * 10,000; 757 * [khz] -> [100Hz] */ 758 azalia_clock_info->audio_dto_module = 759 actual_pixel_clock_100Hz; 760 } 761 762 static void get_azalia_clock_info_dp( 763 uint32_t requested_pixel_clock_100Hz, 764 const struct audio_pll_info *pll_info, 765 struct azalia_clock_info *azalia_clock_info) 766 { 767 /* Reported dpDtoSourceClockInkhz value for 768 * DCE8 already adjusted for SS, do not need any 769 * adjustment here anymore 770 */ 771 772 /*audio_dto_phase = 24 * 10,000; 773 * 24MHz in [100Hz] units */ 774 azalia_clock_info->audio_dto_phase = 24 * 10000; 775 776 /*audio_dto_module = dpDtoSourceClockInkhz * 10,000; 777 * [khz] ->[100Hz] */ 778 azalia_clock_info->audio_dto_module = 779 pll_info->dp_dto_source_clock_in_khz * 10; 780 } 781 782 void dce_aud_wall_dto_setup( 783 struct audio *audio, 784 enum signal_type signal, 785 const struct audio_crtc_info *crtc_info, 786 const struct audio_pll_info *pll_info) 787 { 788 struct dce_audio *aud = DCE_AUD(audio); 789 790 struct azalia_clock_info clock_info = { 0 }; 791 792 if (dc_is_hdmi_signal(signal)) { 793 uint32_t src_sel; 794 795 /*DTO0 Programming goal: 796 -generate 24MHz, 128*Fs from 24MHz 797 -use DTO0 when an active HDMI port is connected 798 (optionally a DP is connected) */ 799 800 /* calculate DTO settings */ 801 get_azalia_clock_info_hdmi( 802 crtc_info->requested_pixel_clock_100Hz, 803 crtc_info->calculated_pixel_clock_100Hz, 804 &clock_info); 805 806 DC_LOG_HW_AUDIO("\n%s:Input::requested_pixel_clock_100Hz = %d"\ 807 "calculated_pixel_clock_100Hz =%d\n"\ 808 "audio_dto_module = %d audio_dto_phase =%d \n\n", __func__,\ 809 crtc_info->requested_pixel_clock_100Hz,\ 810 crtc_info->calculated_pixel_clock_100Hz,\ 811 clock_info.audio_dto_module,\ 812 clock_info.audio_dto_phase); 813 814 /* On TN/SI, Program DTO source select and DTO select before 815 programming DTO modulo and DTO phase. These bits must be 816 programmed first, otherwise there will be no HDMI audio at boot 817 up. This is a HW sequence change (different from old ASICs). 818 Caution when changing this programming sequence. 819 820 HDMI enabled, using DTO0 821 program master CRTC for DTO0 */ 822 src_sel = pll_info->dto_source - DTO_SOURCE_ID0; 823 REG_UPDATE_2(DCCG_AUDIO_DTO_SOURCE, 824 DCCG_AUDIO_DTO0_SOURCE_SEL, src_sel, 825 DCCG_AUDIO_DTO_SEL, 0); 826 827 /* module */ 828 REG_UPDATE(DCCG_AUDIO_DTO0_MODULE, 829 DCCG_AUDIO_DTO0_MODULE, clock_info.audio_dto_module); 830 831 /* phase */ 832 REG_UPDATE(DCCG_AUDIO_DTO0_PHASE, 833 DCCG_AUDIO_DTO0_PHASE, clock_info.audio_dto_phase); 834 } else { 835 /*DTO1 Programming goal: 836 -generate 24MHz, 512*Fs, 128*Fs from 24MHz 837 -default is to used DTO1, and switch to DTO0 when an audio 838 master HDMI port is connected 839 -use as default for DP 840 841 calculate DTO settings */ 842 get_azalia_clock_info_dp( 843 crtc_info->requested_pixel_clock_100Hz, 844 pll_info, 845 &clock_info); 846 847 /* Program DTO select before programming DTO modulo and DTO 848 phase. default to use DTO1 */ 849 850 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 851 DCCG_AUDIO_DTO_SEL, 1); 852 853 /* DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1) 854 * Select 512fs for DP TODO: web register definition 855 * does not match register header file 856 * DCE11 version it's commented out while DCE8 it's set to 1 857 */ 858 859 /* module */ 860 REG_UPDATE(DCCG_AUDIO_DTO1_MODULE, 861 DCCG_AUDIO_DTO1_MODULE, clock_info.audio_dto_module); 862 863 /* phase */ 864 REG_UPDATE(DCCG_AUDIO_DTO1_PHASE, 865 DCCG_AUDIO_DTO1_PHASE, clock_info.audio_dto_phase); 866 867 REG_UPDATE(DCCG_AUDIO_DTO_SOURCE, 868 DCCG_AUDIO_DTO2_USE_512FBR_DTO, 1); 869 870 } 871 } 872 873 static bool dce_aud_endpoint_valid(struct audio *audio) 874 { 875 uint32_t value; 876 uint32_t port_connectivity; 877 878 value = AZ_REG_READ( 879 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); 880 881 port_connectivity = get_reg_field_value(value, 882 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT, 883 PORT_CONNECTIVITY); 884 885 return !(port_connectivity == 1); 886 } 887 888 /* initialize HW state */ 889 void dce_aud_hw_init( 890 struct audio *audio) 891 { 892 uint32_t value; 893 struct dce_audio *aud = DCE_AUD(audio); 894 895 /* we only need to program the following registers once, so we only do 896 it for the inst 0*/ 897 if (audio->inst != 0) 898 return; 899 900 /* Suport R5 - 32khz 901 * Suport R6 - 44.1khz 902 * Suport R7 - 48khz 903 */ 904 /*disable clock gating before write to endpoint register*/ 905 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL); 906 set_reg_field_value(value, 1, 907 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 908 CLOCK_GATING_DISABLE); 909 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 910 REG_UPDATE(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, 911 AUDIO_RATE_CAPABILITIES, 0x70); 912 913 /*Keep alive bit to verify HW block in BU. */ 914 REG_UPDATE_2(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, 915 CLKSTOP, 1, 916 EPSS, 1); 917 set_reg_field_value(value, 0, 918 AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, 919 CLOCK_GATING_DISABLE); 920 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, value); 921 } 922 923 static const struct audio_funcs funcs = { 924 .endpoint_valid = dce_aud_endpoint_valid, 925 .hw_init = dce_aud_hw_init, 926 .wall_dto_setup = dce_aud_wall_dto_setup, 927 .az_enable = dce_aud_az_enable, 928 .az_disable = dce_aud_az_disable, 929 .az_configure = dce_aud_az_configure, 930 .destroy = dce_aud_destroy, 931 }; 932 void dce_aud_destroy(struct audio **audio) 933 { 934 struct dce_audio *aud = DCE_AUD(*audio); 935 936 kfree(aud); 937 *audio = NULL; 938 } 939 940 struct audio *dce_audio_create( 941 struct dc_context *ctx, 942 unsigned int inst, 943 const struct dce_audio_registers *reg, 944 const struct dce_audio_shift *shifts, 945 const struct dce_audio_mask *masks 946 ) 947 { 948 struct dce_audio *audio = kzalloc(sizeof(*audio), GFP_KERNEL); 949 950 if (audio == NULL) { 951 ASSERT_CRITICAL(audio); 952 return NULL; 953 } 954 955 audio->base.ctx = ctx; 956 audio->base.inst = inst; 957 audio->base.funcs = &funcs; 958 959 audio->regs = reg; 960 audio->shifts = shifts; 961 audio->masks = masks; 962 return &audio->base; 963 } 964 965
Indexes created Sat Sep 20 22:09:52 GMT 2025