1 /* $NetBSD: dce_dmcu.h,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-16 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 29 #ifndef _DCE_DMCU_H_ 30 #define _DCE_DMCU_H_ 31 32 #include "dmcu.h" 33 34 #define DMCU_COMMON_REG_LIST_DCE_BASE() \ 35 SR(DMCU_CTRL), \ 36 SR(DMCU_STATUS), \ 37 SR(DMCU_RAM_ACCESS_CTRL), \ 38 SR(DMCU_IRAM_WR_CTRL), \ 39 SR(DMCU_IRAM_WR_DATA), \ 40 SR(MASTER_COMM_DATA_REG1), \ 41 SR(MASTER_COMM_DATA_REG2), \ 42 SR(MASTER_COMM_DATA_REG3), \ 43 SR(MASTER_COMM_CMD_REG), \ 44 SR(MASTER_COMM_CNTL_REG), \ 45 SR(DMCU_IRAM_RD_CTRL), \ 46 SR(DMCU_IRAM_RD_DATA), \ 47 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 48 SR(SMU_INTERRUPT_CONTROL), \ 49 SR(DC_DMCU_SCRATCH) 50 51 #define DMCU_DCE80_REG_LIST() \ 52 SR(DMCU_CTRL), \ 53 SR(DMCU_STATUS), \ 54 SR(DMCU_RAM_ACCESS_CTRL), \ 55 SR(DMCU_IRAM_WR_CTRL), \ 56 SR(DMCU_IRAM_WR_DATA), \ 57 SR(MASTER_COMM_DATA_REG1), \ 58 SR(MASTER_COMM_DATA_REG2), \ 59 SR(MASTER_COMM_DATA_REG3), \ 60 SR(MASTER_COMM_CMD_REG), \ 61 SR(MASTER_COMM_CNTL_REG), \ 62 SR(DMCU_IRAM_RD_CTRL), \ 63 SR(DMCU_IRAM_RD_DATA), \ 64 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \ 65 SR(SMU_INTERRUPT_CONTROL), \ 66 SR(DC_DMCU_SCRATCH) 67 68 #define DMCU_DCE110_COMMON_REG_LIST() \ 69 DMCU_COMMON_REG_LIST_DCE_BASE(), \ 70 SR(DCI_MEM_PWR_STATUS) 71 72 #define DMCU_DCN10_REG_LIST()\ 73 DMCU_COMMON_REG_LIST_DCE_BASE(), \ 74 SR(DMU_MEM_PWR_CNTL) 75 76 #define DMCU_DCN20_REG_LIST()\ 77 DMCU_DCN10_REG_LIST(), \ 78 SR(DMCUB_SCRATCH15) 79 80 #define DMCU_SF(reg_name, field_name, post_fix)\ 81 .field_name = reg_name ## __ ## field_name ## post_fix 82 83 #define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \ 84 DMCU_SF(DMCU_CTRL, \ 85 DMCU_ENABLE, mask_sh), \ 86 DMCU_SF(DMCU_STATUS, \ 87 UC_IN_STOP_MODE, mask_sh), \ 88 DMCU_SF(DMCU_STATUS, \ 89 UC_IN_RESET, mask_sh), \ 90 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 91 IRAM_HOST_ACCESS_EN, mask_sh), \ 92 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 93 IRAM_WR_ADDR_AUTO_INC, mask_sh), \ 94 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 95 IRAM_RD_ADDR_AUTO_INC, mask_sh), \ 96 DMCU_SF(MASTER_COMM_CMD_REG, \ 97 MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 98 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 99 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 100 STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \ 101 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 102 STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \ 103 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 104 STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \ 105 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \ 106 STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \ 107 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh) 108 109 #define DMCU_MASK_SH_LIST_DCE80(mask_sh) \ 110 DMCU_SF(DMCU_CTRL, \ 111 DMCU_ENABLE, mask_sh), \ 112 DMCU_SF(DMCU_STATUS, \ 113 UC_IN_STOP_MODE, mask_sh), \ 114 DMCU_SF(DMCU_STATUS, \ 115 UC_IN_RESET, mask_sh), \ 116 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 117 IRAM_HOST_ACCESS_EN, mask_sh), \ 118 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 119 IRAM_WR_ADDR_AUTO_INC, mask_sh), \ 120 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \ 121 IRAM_RD_ADDR_AUTO_INC, mask_sh), \ 122 DMCU_SF(MASTER_COMM_CMD_REG, \ 123 MASTER_COMM_CMD_REG_BYTE0, mask_sh), \ 124 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \ 125 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh) 126 127 #define DMCU_MASK_SH_LIST_DCE110(mask_sh) \ 128 DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 129 DMCU_SF(DCI_MEM_PWR_STATUS, \ 130 DMCU_IRAM_MEM_PWR_STATE, mask_sh) 131 132 #define DMCU_MASK_SH_LIST_DCN10(mask_sh) \ 133 DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \ 134 DMCU_SF(DMU_MEM_PWR_CNTL, \ 135 DMCU_IRAM_MEM_PWR_STATE, mask_sh) 136 137 #define DMCU_REG_FIELD_LIST(type) \ 138 type DMCU_IRAM_MEM_PWR_STATE; \ 139 type IRAM_HOST_ACCESS_EN; \ 140 type IRAM_WR_ADDR_AUTO_INC; \ 141 type IRAM_RD_ADDR_AUTO_INC; \ 142 type DMCU_ENABLE; \ 143 type UC_IN_STOP_MODE; \ 144 type UC_IN_RESET; \ 145 type MASTER_COMM_CMD_REG_BYTE0; \ 146 type MASTER_COMM_INTERRUPT; \ 147 type DPHY_RX_FAST_TRAINING_CAPABLE; \ 148 type DPHY_LOAD_BS_COUNT; \ 149 type STATIC_SCREEN1_INT_TO_UC_EN; \ 150 type STATIC_SCREEN2_INT_TO_UC_EN; \ 151 type STATIC_SCREEN3_INT_TO_UC_EN; \ 152 type STATIC_SCREEN4_INT_TO_UC_EN; \ 153 type DP_SEC_GSP0_LINE_NUM; \ 154 type DP_SEC_GSP0_PRIORITY; \ 155 type DC_SMU_INT_ENABLE 156 157 struct dce_dmcu_shift { 158 DMCU_REG_FIELD_LIST(uint8_t); 159 }; 160 161 struct dce_dmcu_mask { 162 DMCU_REG_FIELD_LIST(uint32_t); 163 }; 164 165 struct dce_dmcu_registers { 166 uint32_t DMCU_CTRL; 167 uint32_t DMCU_STATUS; 168 uint32_t DMCU_RAM_ACCESS_CTRL; 169 uint32_t DCI_MEM_PWR_STATUS; 170 uint32_t DMU_MEM_PWR_CNTL; 171 uint32_t DMCU_IRAM_WR_CTRL; 172 uint32_t DMCU_IRAM_WR_DATA; 173 174 uint32_t MASTER_COMM_DATA_REG1; 175 uint32_t MASTER_COMM_DATA_REG2; 176 uint32_t MASTER_COMM_DATA_REG3; 177 uint32_t MASTER_COMM_CMD_REG; 178 uint32_t MASTER_COMM_CNTL_REG; 179 uint32_t DMCU_IRAM_RD_CTRL; 180 uint32_t DMCU_IRAM_RD_DATA; 181 uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK; 182 uint32_t SMU_INTERRUPT_CONTROL; 183 uint32_t DC_DMCU_SCRATCH; 184 uint32_t DMCUB_SCRATCH15; 185 }; 186 187 struct dce_dmcu { 188 struct dmcu base; 189 const struct dce_dmcu_registers *regs; 190 const struct dce_dmcu_shift *dmcu_shift; 191 const struct dce_dmcu_mask *dmcu_mask; 192 }; 193 194 /******************************************************************* 195 * MASTER_COMM_DATA_REG1 Bit position Data 196 * 7:0 hyst_frames[7:0] 197 * 14:8 hyst_lines[6:0] 198 * 15 RFB_UPDATE_AUTO_EN 199 * 18:16 phy_num[2:0] 200 * 21:19 dcp_sel[2:0] 201 * 22 phy_type 202 * 23 frame_cap_ind 203 * 26:24 aux_chan[2:0] 204 * 30:27 aux_repeat[3:0] 205 * 31:31 reserved[31:31] 206 ******************************************************************/ 207 union dce_dmcu_psr_config_data_reg1 { 208 struct { 209 unsigned int timehyst_frames:8; /*[7:0]*/ 210 unsigned int hyst_lines:7; /*[14:8]*/ 211 unsigned int rfb_update_auto_en:1; /*[15:15]*/ 212 unsigned int dp_port_num:3; /*[18:16]*/ 213 unsigned int dcp_sel:3; /*[21:19]*/ 214 unsigned int phy_type:1; /*[22:22]*/ 215 unsigned int frame_cap_ind:1; /*[23:23]*/ 216 unsigned int aux_chan:3; /*[26:24]*/ 217 unsigned int aux_repeat:4; /*[30:27]*/ 218 unsigned int allow_smu_optimizations:1; /*[31:31]*/ 219 } bits; 220 unsigned int u32All; 221 }; 222 223 /******************************************************************* 224 * MASTER_COMM_DATA_REG2 225 *******************************************************************/ 226 union dce_dmcu_psr_config_data_reg2 { 227 struct { 228 unsigned int dig_fe:3; /*[2:0]*/ 229 unsigned int dig_be:3; /*[5:3]*/ 230 unsigned int skip_wait_for_pll_lock:1; /*[6:6]*/ 231 unsigned int reserved:9; /*[15:7]*/ 232 unsigned int frame_delay:8; /*[23:16]*/ 233 unsigned int smu_phy_id:4; /*[27:24]*/ 234 unsigned int num_of_controllers:4; /*[31:28]*/ 235 } bits; 236 unsigned int u32All; 237 }; 238 239 /******************************************************************* 240 * MASTER_COMM_DATA_REG3 241 *******************************************************************/ 242 union dce_dmcu_psr_config_data_reg3 { 243 struct { 244 unsigned int psr_level:16; /*[15:0]*/ 245 unsigned int link_rate:4; /*[19:16]*/ 246 unsigned int reserved:12; /*[31:20]*/ 247 } bits; 248 unsigned int u32All; 249 }; 250 251 union dce_dmcu_psr_config_data_wait_loop_reg1 { 252 struct { 253 unsigned int wait_loop:16; /* [15:0] */ 254 unsigned int reserved:16; /* [31:16] */ 255 } bits; 256 unsigned int u32; 257 }; 258 259 struct dmcu *dce_dmcu_create( 260 struct dc_context *ctx, 261 const struct dce_dmcu_registers *regs, 262 const struct dce_dmcu_shift *dmcu_shift, 263 const struct dce_dmcu_mask *dmcu_mask); 264 265 struct dmcu *dcn10_dmcu_create( 266 struct dc_context *ctx, 267 const struct dce_dmcu_registers *regs, 268 const struct dce_dmcu_shift *dmcu_shift, 269 const struct dce_dmcu_mask *dmcu_mask); 270 271 struct dmcu *dcn20_dmcu_create( 272 struct dc_context *ctx, 273 const struct dce_dmcu_registers *regs, 274 const struct dce_dmcu_shift *dmcu_shift, 275 const struct dce_dmcu_mask *dmcu_mask); 276 277 struct dmcu *dcn21_dmcu_create( 278 struct dc_context *ctx, 279 const struct dce_dmcu_registers *regs, 280 const struct dce_dmcu_shift *dmcu_shift, 281 const struct dce_dmcu_mask *dmcu_mask); 282 283 void dce_dmcu_destroy(struct dmcu **dmcu); 284 285 static const uint32_t abm_gain_stepsize = 0x0060; 286 287 #endif /* _DCE_ABM_H_ */ 288
Indexes created Sun Sep 21 20:09:37 GMT 2025