1 /* $NetBSD: dce_mem_input.h,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 #ifndef __DCE_MEM_INPUT_H__ 28 #define __DCE_MEM_INPUT_H__ 29 30 #include "dc_hw_types.h" 31 #include "mem_input.h" 32 33 #define TO_DCE_MEM_INPUT(mem_input)\ 34 container_of(mem_input, struct dce_mem_input, base) 35 36 #define MI_DCE_BASE_REG_LIST(id)\ 37 SRI(GRPH_ENABLE, DCP, id),\ 38 SRI(GRPH_CONTROL, DCP, id),\ 39 SRI(GRPH_X_START, DCP, id),\ 40 SRI(GRPH_Y_START, DCP, id),\ 41 SRI(GRPH_X_END, DCP, id),\ 42 SRI(GRPH_Y_END, DCP, id),\ 43 SRI(GRPH_PITCH, DCP, id),\ 44 SRI(HW_ROTATION, DCP, id),\ 45 SRI(GRPH_SWAP_CNTL, DCP, id),\ 46 SRI(PRESCALE_GRPH_CONTROL, DCP, id),\ 47 SRI(GRPH_UPDATE, DCP, id),\ 48 SRI(GRPH_FLIP_CONTROL, DCP, id),\ 49 SRI(GRPH_PRIMARY_SURFACE_ADDRESS, DCP, id),\ 50 SRI(GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, DCP, id),\ 51 SRI(GRPH_SECONDARY_SURFACE_ADDRESS, DCP, id),\ 52 SRI(GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, DCP, id),\ 53 SRI(DPG_PIPE_ARBITRATION_CONTROL1, DMIF_PG, id),\ 54 SRI(DPG_WATERMARK_MASK_CONTROL, DMIF_PG, id),\ 55 SRI(DPG_PIPE_URGENCY_CONTROL, DMIF_PG, id),\ 56 SRI(DPG_PIPE_STUTTER_CONTROL, DMIF_PG, id),\ 57 SRI(DMIF_BUFFER_CONTROL, PIPE, id) 58 59 #define MI_DCE_PTE_REG_LIST(id)\ 60 SRI(DVMM_PTE_CONTROL, DCP, id),\ 61 SRI(DVMM_PTE_ARB_CONTROL, DCP, id) 62 63 #define MI_DCE8_REG_LIST(id)\ 64 MI_DCE_BASE_REG_LIST(id),\ 65 SRI(DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, DMIF_PG, id) 66 67 #define MI_DCE11_2_REG_LIST(id)\ 68 MI_DCE8_REG_LIST(id),\ 69 SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id) 70 71 #define MI_DCE11_REG_LIST(id)\ 72 MI_DCE11_2_REG_LIST(id),\ 73 MI_DCE_PTE_REG_LIST(id) 74 75 #define MI_DCE12_REG_LIST(id)\ 76 MI_DCE_BASE_REG_LIST(id),\ 77 MI_DCE_PTE_REG_LIST(id),\ 78 SRI(GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, DCP, id),\ 79 SRI(DPG_PIPE_STUTTER_CONTROL2, DMIF_PG, id),\ 80 SRI(DPG_PIPE_LOW_POWER_CONTROL, DMIF_PG, id),\ 81 SR(DCHUB_FB_LOCATION),\ 82 SR(DCHUB_AGP_BASE),\ 83 SR(DCHUB_AGP_BOT),\ 84 SR(DCHUB_AGP_TOP) 85 86 struct dce_mem_input_registers { 87 /* DCP */ 88 uint32_t GRPH_ENABLE; 89 uint32_t GRPH_CONTROL; 90 uint32_t GRPH_X_START; 91 uint32_t GRPH_Y_START; 92 uint32_t GRPH_X_END; 93 uint32_t GRPH_Y_END; 94 uint32_t GRPH_PITCH; 95 uint32_t HW_ROTATION; 96 uint32_t GRPH_SWAP_CNTL; 97 uint32_t PRESCALE_GRPH_CONTROL; 98 uint32_t GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; 99 uint32_t DVMM_PTE_CONTROL; 100 uint32_t DVMM_PTE_ARB_CONTROL; 101 uint32_t GRPH_UPDATE; 102 uint32_t GRPH_FLIP_CONTROL; 103 uint32_t GRPH_PRIMARY_SURFACE_ADDRESS; 104 uint32_t GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; 105 uint32_t GRPH_SECONDARY_SURFACE_ADDRESS; 106 uint32_t GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; 107 /* DMIF_PG */ 108 uint32_t DPG_PIPE_ARBITRATION_CONTROL1; 109 uint32_t DPG_WATERMARK_MASK_CONTROL; 110 uint32_t DPG_PIPE_URGENCY_CONTROL; 111 uint32_t DPG_PIPE_URGENT_LEVEL_CONTROL; 112 uint32_t DPG_PIPE_NB_PSTATE_CHANGE_CONTROL; 113 uint32_t DPG_PIPE_LOW_POWER_CONTROL; 114 uint32_t DPG_PIPE_STUTTER_CONTROL; 115 uint32_t DPG_PIPE_STUTTER_CONTROL2; 116 /* DCI */ 117 uint32_t DMIF_BUFFER_CONTROL; 118 /* MC_HUB */ 119 uint32_t MC_HUB_RDREQ_DMIF_LIMIT; 120 /*DCHUB*/ 121 uint32_t DCHUB_FB_LOCATION; 122 uint32_t DCHUB_AGP_BASE; 123 uint32_t DCHUB_AGP_BOT; 124 uint32_t DCHUB_AGP_TOP; 125 }; 126 127 /* Set_Filed_for_Block */ 128 #define SFB(blk_name, reg_name, field_name, post_fix)\ 129 .field_name = blk_name ## reg_name ## __ ## field_name ## post_fix 130 131 #define MI_GFX8_TILE_MASK_SH_LIST(mask_sh, blk)\ 132 SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ 133 SFB(blk, GRPH_CONTROL, GRPH_BANK_WIDTH, mask_sh),\ 134 SFB(blk, GRPH_CONTROL, GRPH_BANK_HEIGHT, mask_sh),\ 135 SFB(blk, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT, mask_sh),\ 136 SFB(blk, GRPH_CONTROL, GRPH_TILE_SPLIT, mask_sh),\ 137 SFB(blk, GRPH_CONTROL, GRPH_MICRO_TILE_MODE, mask_sh),\ 138 SFB(blk, GRPH_CONTROL, GRPH_PIPE_CONFIG, mask_sh),\ 139 SFB(blk, GRPH_CONTROL, GRPH_ARRAY_MODE, mask_sh),\ 140 SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) 141 142 #define MI_DCP_MASK_SH_LIST(mask_sh, blk)\ 143 SFB(blk, GRPH_ENABLE, GRPH_ENABLE, mask_sh),\ 144 SFB(blk, GRPH_CONTROL, GRPH_DEPTH, mask_sh),\ 145 SFB(blk, GRPH_CONTROL, GRPH_FORMAT, mask_sh),\ 146 SFB(blk, GRPH_CONTROL, GRPH_NUM_BANKS, mask_sh),\ 147 SFB(blk, GRPH_X_START, GRPH_X_START, mask_sh),\ 148 SFB(blk, GRPH_Y_START, GRPH_Y_START, mask_sh),\ 149 SFB(blk, GRPH_X_END, GRPH_X_END, mask_sh),\ 150 SFB(blk, GRPH_Y_END, GRPH_Y_END, mask_sh),\ 151 SFB(blk, GRPH_PITCH, GRPH_PITCH, mask_sh),\ 152 SFB(blk, HW_ROTATION, GRPH_ROTATION_ANGLE, mask_sh),\ 153 SFB(blk, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, mask_sh),\ 154 SFB(blk, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, mask_sh),\ 155 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_SELECT, mask_sh),\ 156 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_R_SIGN, mask_sh),\ 157 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_G_SIGN, mask_sh),\ 158 SFB(blk, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_B_SIGN, mask_sh),\ 159 SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, mask_sh),\ 160 SFB(blk, GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_SURFACE_ADDRESS, mask_sh),\ 161 SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, mask_sh),\ 162 SFB(blk, GRPH_PRIMARY_SURFACE_ADDRESS, GRPH_PRIMARY_SURFACE_ADDRESS, mask_sh),\ 163 SFB(blk, GRPH_UPDATE, GRPH_SURFACE_UPDATE_PENDING, mask_sh),\ 164 SFB(blk, GRPH_UPDATE, GRPH_UPDATE_LOCK, mask_sh),\ 165 SFB(blk, GRPH_FLIP_CONTROL, GRPH_SURFACE_UPDATE_H_RETRACE_EN, mask_sh) 166 167 #define MI_DCP_DCE11_MASK_SH_LIST(mask_sh, blk)\ 168 SFB(blk, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT, mask_sh) 169 170 #define MI_DCP_PTE_MASK_SH_LIST(mask_sh, blk)\ 171 SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_WIDTH, mask_sh),\ 172 SFB(blk, DVMM_PTE_CONTROL, DVMM_PAGE_HEIGHT, mask_sh),\ 173 SFB(blk, DVMM_PTE_CONTROL, DVMM_MIN_PTE_BEFORE_FLIP, mask_sh),\ 174 SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_PTE_REQ_PER_CHUNK, mask_sh),\ 175 SFB(blk, DVMM_PTE_ARB_CONTROL, DVMM_MAX_PTE_REQ_OUTSTANDING, mask_sh) 176 177 #define MI_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ 178 SFB(blk, DPG_PIPE_ARBITRATION_CONTROL1, PIXEL_DURATION, mask_sh),\ 179 SFB(blk, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, mask_sh),\ 180 SFB(blk, DPG_WATERMARK_MASK_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK, mask_sh),\ 181 SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ 182 SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ 183 SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE, mask_sh),\ 184 SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_IGNORE_FBC, mask_sh),\ 185 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, mask_sh),\ 186 SF(PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED, mask_sh) 187 188 #define MI_DMIF_PG_MASK_SH_DCE(mask_sh, blk)\ 189 SFB(blk, DPG_PIPE_STUTTER_CONTROL, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ 190 SFB(blk, DPG_WATERMARK_MASK_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ 191 SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_ENABLE, mask_sh),\ 192 SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ 193 SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ 194 SFB(blk, DPG_PIPE_NB_PSTATE_CHANGE_CONTROL, NB_PSTATE_CHANGE_WATERMARK, mask_sh) 195 196 #define MI_DCE8_MASK_SH_LIST(mask_sh)\ 197 MI_DCP_MASK_SH_LIST(mask_sh, ),\ 198 MI_DMIF_PG_MASK_SH_LIST(mask_sh, ),\ 199 MI_DMIF_PG_MASK_SH_DCE(mask_sh, ),\ 200 MI_GFX8_TILE_MASK_SH_LIST(mask_sh, ) 201 202 #define MI_DCE11_2_MASK_SH_LIST(mask_sh)\ 203 MI_DCE8_MASK_SH_LIST(mask_sh),\ 204 MI_DCP_DCE11_MASK_SH_LIST(mask_sh, ) 205 206 #define MI_DCE11_MASK_SH_LIST(mask_sh)\ 207 MI_DCE11_2_MASK_SH_LIST(mask_sh),\ 208 MI_DCP_PTE_MASK_SH_LIST(mask_sh, ) 209 210 #define MI_GFX9_TILE_MASK_SH_LIST(mask_sh, blk)\ 211 SFB(blk, GRPH_CONTROL, GRPH_SW_MODE, mask_sh),\ 212 SFB(blk, GRPH_CONTROL, GRPH_SE_ENABLE, mask_sh),\ 213 SFB(blk, GRPH_CONTROL, GRPH_NUM_SHADER_ENGINES, mask_sh),\ 214 SFB(blk, GRPH_CONTROL, GRPH_NUM_PIPES, mask_sh),\ 215 SFB(blk, GRPH_CONTROL, GRPH_COLOR_EXPANSION_MODE, mask_sh) 216 217 #define MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, blk)\ 218 SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_EXIT_SELF_REFRESH_WATERMARK, mask_sh),\ 219 SFB(blk, DPG_PIPE_STUTTER_CONTROL2, STUTTER_ENTER_SELF_REFRESH_WATERMARK, mask_sh),\ 220 SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_LOW_WATERMARK, mask_sh),\ 221 SFB(blk, DPG_PIPE_URGENT_LEVEL_CONTROL, URGENT_LEVEL_HIGH_WATERMARK, mask_sh),\ 222 SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, mask_sh),\ 223 SFB(blk, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, mask_sh),\ 224 SFB(blk, DPG_WATERMARK_MASK_CONTROL, PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ 225 SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_ENABLE, mask_sh),\ 226 SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ 227 SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST, mask_sh),\ 228 SFB(blk, DPG_PIPE_LOW_POWER_CONTROL, PSTATE_CHANGE_WATERMARK, mask_sh) 229 230 #define MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh)\ 231 SF(DCHUB_FB_LOCATION, FB_TOP, mask_sh),\ 232 SF(DCHUB_FB_LOCATION, FB_BASE, mask_sh),\ 233 SF(DCHUB_AGP_BASE, AGP_BASE, mask_sh),\ 234 SF(DCHUB_AGP_BOT, AGP_BOT, mask_sh),\ 235 SF(DCHUB_AGP_TOP, AGP_TOP, mask_sh) 236 237 #define MI_DCE12_MASK_SH_LIST(mask_sh)\ 238 MI_DCP_MASK_SH_LIST(mask_sh, DCP0_),\ 239 SF(DCP0_GRPH_SECONDARY_SURFACE_ADDRESS, GRPH_SECONDARY_DFQ_ENABLE, mask_sh),\ 240 MI_DCP_DCE11_MASK_SH_LIST(mask_sh, DCP0_),\ 241 MI_DCP_PTE_MASK_SH_LIST(mask_sh, DCP0_),\ 242 MI_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ 243 MI_DCE12_DMIF_PG_MASK_SH_LIST(mask_sh, DMIF_PG0_),\ 244 MI_GFX9_TILE_MASK_SH_LIST(mask_sh, DCP0_),\ 245 MI_GFX9_DCHUB_MASK_SH_LIST(mask_sh) 246 247 #define MI_REG_FIELD_LIST(type) \ 248 type GRPH_ENABLE; \ 249 type GRPH_X_START; \ 250 type GRPH_Y_START; \ 251 type GRPH_X_END; \ 252 type GRPH_Y_END; \ 253 type GRPH_PITCH; \ 254 type GRPH_ROTATION_ANGLE; \ 255 type GRPH_RED_CROSSBAR; \ 256 type GRPH_BLUE_CROSSBAR; \ 257 type GRPH_PRESCALE_SELECT; \ 258 type GRPH_PRESCALE_R_SIGN; \ 259 type GRPH_PRESCALE_G_SIGN; \ 260 type GRPH_PRESCALE_B_SIGN; \ 261 type GRPH_PIPE_OUTSTANDING_REQUEST_LIMIT; \ 262 type DVMM_PAGE_WIDTH; \ 263 type DVMM_PAGE_HEIGHT; \ 264 type DVMM_MIN_PTE_BEFORE_FLIP; \ 265 type DVMM_PTE_REQ_PER_CHUNK; \ 266 type DVMM_MAX_PTE_REQ_OUTSTANDING; \ 267 type GRPH_DEPTH; \ 268 type GRPH_FORMAT; \ 269 type GRPH_NUM_BANKS; \ 270 type GRPH_BANK_WIDTH;\ 271 type GRPH_BANK_HEIGHT;\ 272 type GRPH_MACRO_TILE_ASPECT;\ 273 type GRPH_TILE_SPLIT;\ 274 type GRPH_MICRO_TILE_MODE;\ 275 type GRPH_PIPE_CONFIG;\ 276 type GRPH_ARRAY_MODE;\ 277 type GRPH_COLOR_EXPANSION_MODE;\ 278 type GRPH_SW_MODE; \ 279 type GRPH_SE_ENABLE; \ 280 type GRPH_NUM_SHADER_ENGINES; \ 281 type GRPH_NUM_PIPES; \ 282 type GRPH_SECONDARY_SURFACE_ADDRESS_HIGH; \ 283 type GRPH_SECONDARY_SURFACE_ADDRESS; \ 284 type GRPH_SECONDARY_DFQ_ENABLE; \ 285 type GRPH_PRIMARY_SURFACE_ADDRESS_HIGH; \ 286 type GRPH_PRIMARY_SURFACE_ADDRESS; \ 287 type GRPH_SURFACE_UPDATE_PENDING; \ 288 type GRPH_SURFACE_UPDATE_H_RETRACE_EN; \ 289 type GRPH_UPDATE_LOCK; \ 290 type PIXEL_DURATION; \ 291 type URGENCY_WATERMARK_MASK; \ 292 type PSTATE_CHANGE_WATERMARK_MASK; \ 293 type NB_PSTATE_CHANGE_WATERMARK_MASK; \ 294 type STUTTER_EXIT_SELF_REFRESH_WATERMARK_MASK; \ 295 type URGENCY_LOW_WATERMARK; \ 296 type URGENCY_HIGH_WATERMARK; \ 297 type URGENT_LEVEL_LOW_WATERMARK;\ 298 type URGENT_LEVEL_HIGH_WATERMARK;\ 299 type NB_PSTATE_CHANGE_ENABLE; \ 300 type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST; \ 301 type NB_PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \ 302 type NB_PSTATE_CHANGE_WATERMARK; \ 303 type PSTATE_CHANGE_ENABLE; \ 304 type PSTATE_CHANGE_URGENT_DURING_REQUEST; \ 305 type PSTATE_CHANGE_NOT_SELF_REFRESH_DURING_REQUEST; \ 306 type PSTATE_CHANGE_WATERMARK; \ 307 type STUTTER_ENABLE; \ 308 type STUTTER_IGNORE_FBC; \ 309 type STUTTER_EXIT_SELF_REFRESH_WATERMARK; \ 310 type STUTTER_ENTER_SELF_REFRESH_WATERMARK; \ 311 type DMIF_BUFFERS_ALLOCATED; \ 312 type DMIF_BUFFERS_ALLOCATION_COMPLETED; \ 313 type ENABLE; /* MC_HUB_RDREQ_DMIF_LIMIT */\ 314 type FB_BASE; \ 315 type FB_TOP; \ 316 type AGP_BASE; \ 317 type AGP_TOP; \ 318 type AGP_BOT; \ 319 320 struct dce_mem_input_shift { 321 MI_REG_FIELD_LIST(uint8_t) 322 }; 323 324 struct dce_mem_input_mask { 325 MI_REG_FIELD_LIST(uint32_t) 326 }; 327 328 struct dce_mem_input_wa { 329 uint8_t single_head_rdreq_dmif_limit; 330 }; 331 332 struct dce_mem_input { 333 struct mem_input base; 334 335 const struct dce_mem_input_registers *regs; 336 const struct dce_mem_input_shift *shifts; 337 const struct dce_mem_input_mask *masks; 338 339 struct dce_mem_input_wa wa; 340 }; 341 342 void dce_mem_input_construct( 343 struct dce_mem_input *dce_mi, 344 struct dc_context *ctx, 345 int inst, 346 const struct dce_mem_input_registers *regs, 347 const struct dce_mem_input_shift *mi_shift, 348 const struct dce_mem_input_mask *mi_mask); 349 350 void dce112_mem_input_construct( 351 struct dce_mem_input *dce_mi, 352 struct dc_context *ctx, 353 int inst, 354 const struct dce_mem_input_registers *regs, 355 const struct dce_mem_input_shift *mi_shift, 356 const struct dce_mem_input_mask *mi_mask); 357 358 void dce120_mem_input_construct( 359 struct dce_mem_input *dce_mi, 360 struct dc_context *ctx, 361 int inst, 362 const struct dce_mem_input_registers *regs, 363 const struct dce_mem_input_shift *mi_shift, 364 const struct dce_mem_input_mask *mi_mask); 365 366 #endif /*__DCE_MEM_INPUT_H__*/ 367
Indexes created Sun Sep 21 20:09:37 GMT 2025