1 /* $NetBSD: dce_opp.h,v 1.2 2021/12/18 23:45:02 riastradh Exp $ */ 2 3 /* Copyright 2012-15 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DC_OPP_DCE_H__ 28 #define __DC_OPP_DCE_H__ 29 30 #include "dc_types.h" 31 #include "opp.h" 32 #include "core_types.h" 33 34 #define FROM_DCE11_OPP(opp)\ 35 container_of(opp, struct dce110_opp, base) 36 37 enum dce110_opp_reg_type { 38 DCE110_OPP_REG_DCP = 0, 39 DCE110_OPP_REG_DCFE, 40 DCE110_OPP_REG_FMT, 41 42 DCE110_OPP_REG_MAX 43 }; 44 45 #define OPP_COMMON_REG_LIST_BASE(id) \ 46 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 47 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 48 SRI(FMT_CONTROL, FMT, id), \ 49 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 50 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 51 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 52 SRI(FMT_CLAMP_CNTL, FMT, id), \ 53 SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \ 54 SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \ 55 SRI(FMT_CLAMP_COMPONENT_B, FMT, id) 56 57 #define OPP_DCE_80_REG_LIST(id) \ 58 OPP_COMMON_REG_LIST_BASE(id), \ 59 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 60 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 61 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 62 63 #define OPP_DCE_100_REG_LIST(id) \ 64 OPP_COMMON_REG_LIST_BASE(id), \ 65 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 66 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 67 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 68 69 #define OPP_DCE_110_REG_LIST(id) \ 70 OPP_COMMON_REG_LIST_BASE(id), \ 71 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 72 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 73 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id) 74 75 #define OPP_DCE_112_REG_LIST(id) \ 76 OPP_COMMON_REG_LIST_BASE(id), \ 77 SRI(FMT_TEMPORAL_DITHER_PATTERN_CONTROL, FMT, id), \ 78 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX, FMT, id), \ 79 SRI(FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX, FMT, id), \ 80 SRI(CONTROL, FMT_MEMORY, id) 81 82 #define OPP_DCE_120_REG_LIST(id) \ 83 OPP_COMMON_REG_LIST_BASE(id), \ 84 SRI(CONTROL, FMT_MEMORY, id) 85 86 #define OPP_SF(reg_name, field_name, post_fix)\ 87 .field_name = reg_name ## __ ## field_name ## post_fix 88 89 #define OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 90 OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 91 OPP_SF(FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 92 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 93 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 94 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 95 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 96 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 97 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 98 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 99 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 100 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 101 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 102 OPP_SF(FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 103 OPP_SF(FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 104 OPP_SF(FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 105 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 106 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 107 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 108 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 109 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 110 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 111 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 112 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 113 OPP_SF(FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ 114 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 115 OPP_SF(FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 116 OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ 117 OPP_SF(FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ 118 OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ 119 OPP_SF(FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ 120 OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ 121 OPP_SF(FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ 122 OPP_SF(FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ 123 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ 124 OPP_SF(FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh) 125 126 #define OPP_COMMON_MASK_SH_LIST_DCE_110(mask_sh)\ 127 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 128 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 129 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 130 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 131 132 #define OPP_COMMON_MASK_SH_LIST_DCE_100(mask_sh)\ 133 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 134 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 135 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 136 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 137 138 #define OPP_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 139 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh),\ 140 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ 141 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ 142 OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ 143 OPP_SF(FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ 144 OPP_SF(FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh),\ 145 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 146 OPP_SF(FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 147 OPP_SF(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh) 148 149 #define OPP_COMMON_MASK_SH_LIST_DCE_80(mask_sh)\ 150 OPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) 151 152 #define OPP_COMMON_MASK_SH_LIST_DCE_120(mask_sh)\ 153 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh),\ 154 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh),\ 155 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\ 156 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\ 157 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\ 158 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\ 159 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\ 160 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\ 161 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 162 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_RESET, mask_sh),\ 163 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_OFFSET, mask_sh),\ 164 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_DEPTH, mask_sh),\ 165 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_LEVEL, mask_sh),\ 166 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_25FRC_SEL, mask_sh),\ 167 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_50FRC_SEL, mask_sh),\ 168 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_75FRC_SEL, mask_sh),\ 169 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\ 170 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\ 171 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\ 172 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh),\ 173 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh),\ 174 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh),\ 175 OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh),\ 176 OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh),\ 177 OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh),\ 178 OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh),\ 179 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_SOURCE_SEL, mask_sh),\ 180 OPP_SF(FMT_MEMORY0_CONTROL, FMT420_MEM0_PWR_FORCE, mask_sh),\ 181 OPP_SF(FMT0_FMT_CONTROL, FMT_SRC_SELECT, mask_sh),\ 182 OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED_CLEAR, mask_sh),\ 183 OPP_SF(FMT0_FMT_CONTROL, FMT_420_PIXEL_PHASE_LOCKED, mask_sh),\ 184 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh),\ 185 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh),\ 186 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_LOWER_R, mask_sh),\ 187 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_R, FMT_CLAMP_UPPER_R, mask_sh),\ 188 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_LOWER_G, mask_sh),\ 189 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_G, FMT_CLAMP_UPPER_G, mask_sh),\ 190 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_LOWER_B, mask_sh),\ 191 OPP_SF(FMT0_FMT_CLAMP_COMPONENT_B, FMT_CLAMP_UPPER_B, mask_sh),\ 192 OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh),\ 193 OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_MODE, mask_sh),\ 194 OPP_SF(FMT0_FMT_CONTROL, FMT_SUBSAMPLING_ORDER, mask_sh),\ 195 OPP_SF(FMT0_FMT_CONTROL, FMT_CBCR_BIT_REDUCTION_BYPASS, mask_sh) 196 197 #define OPP_REG_FIELD_LIST(type) \ 198 type FMT_DYNAMIC_EXP_EN; \ 199 type FMT_DYNAMIC_EXP_MODE; \ 200 type FMT_TRUNCATE_EN; \ 201 type FMT_TRUNCATE_DEPTH; \ 202 type FMT_TRUNCATE_MODE; \ 203 type FMT_SPATIAL_DITHER_EN; \ 204 type FMT_SPATIAL_DITHER_DEPTH; \ 205 type FMT_SPATIAL_DITHER_MODE; \ 206 type FMT_TEMPORAL_DITHER_EN; \ 207 type FMT_TEMPORAL_DITHER_RESET; \ 208 type FMT_TEMPORAL_DITHER_OFFSET; \ 209 type FMT_TEMPORAL_DITHER_DEPTH; \ 210 type FMT_TEMPORAL_LEVEL; \ 211 type FMT_25FRC_SEL; \ 212 type FMT_50FRC_SEL; \ 213 type FMT_75FRC_SEL; \ 214 type FMT_HIGHPASS_RANDOM_ENABLE; \ 215 type FMT_FRAME_RANDOM_ENABLE; \ 216 type FMT_RGB_RANDOM_ENABLE; \ 217 type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ 218 type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ 219 type FMT_STEREOSYNC_OVERRIDE; \ 220 type FMT_RAND_R_SEED; \ 221 type FMT_RAND_G_SEED; \ 222 type FMT_RAND_B_SEED; \ 223 type FMT420_MEM0_SOURCE_SEL; \ 224 type FMT420_MEM0_PWR_FORCE; \ 225 type FMT_SRC_SELECT; \ 226 type FMT_420_PIXEL_PHASE_LOCKED_CLEAR; \ 227 type FMT_420_PIXEL_PHASE_LOCKED; \ 228 type FMT_CLAMP_DATA_EN; \ 229 type FMT_CLAMP_COLOR_FORMAT; \ 230 type FMT_CLAMP_LOWER_R; \ 231 type FMT_CLAMP_UPPER_R; \ 232 type FMT_CLAMP_LOWER_G; \ 233 type FMT_CLAMP_UPPER_G; \ 234 type FMT_CLAMP_LOWER_B; \ 235 type FMT_CLAMP_UPPER_B; \ 236 type FMT_PIXEL_ENCODING; \ 237 type FMT_SUBSAMPLING_ORDER; \ 238 type FMT_SUBSAMPLING_MODE; \ 239 type FMT_CBCR_BIT_REDUCTION_BYPASS;\ 240 241 struct dce_opp_shift { 242 OPP_REG_FIELD_LIST(uint8_t) 243 }; 244 245 struct dce_opp_mask { 246 OPP_REG_FIELD_LIST(uint32_t) 247 }; 248 249 struct dce_opp_registers { 250 uint32_t FMT_DYNAMIC_EXP_CNTL; 251 uint32_t FMT_BIT_DEPTH_CONTROL; 252 uint32_t FMT_CONTROL; 253 uint32_t FMT_DITHER_RAND_R_SEED; 254 uint32_t FMT_DITHER_RAND_G_SEED; 255 uint32_t FMT_DITHER_RAND_B_SEED; 256 uint32_t FMT_TEMPORAL_DITHER_PATTERN_CONTROL; 257 uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_S_MATRIX; 258 uint32_t FMT_TEMPORAL_DITHER_PROGRAMMABLE_PATTERN_T_MATRIX; 259 uint32_t CONTROL; 260 uint32_t FMT_CLAMP_CNTL; 261 uint32_t FMT_CLAMP_COMPONENT_R; 262 uint32_t FMT_CLAMP_COMPONENT_G; 263 uint32_t FMT_CLAMP_COMPONENT_B; 264 }; 265 266 /* OPP RELATED */ 267 #define TO_DCE110_OPP(opp)\ 268 container_of(opp, struct dce110_opp, base) 269 270 struct dce110_opp { 271 struct output_pixel_processor base; 272 const struct dce_opp_registers *regs; 273 const struct dce_opp_shift *opp_shift; 274 const struct dce_opp_mask *opp_mask; 275 }; 276 277 void dce110_opp_construct(struct dce110_opp *opp110, 278 struct dc_context *ctx, 279 uint32_t inst, 280 const struct dce_opp_registers *regs, 281 const struct dce_opp_shift *opp_shift, 282 const struct dce_opp_mask *opp_mask); 283 284 void dce110_opp_destroy(struct output_pixel_processor **opp); 285 286 287 288 /* FORMATTER RELATED */ 289 void dce110_opp_program_bit_depth_reduction( 290 struct output_pixel_processor *opp, 291 const struct bit_depth_reduction_params *params); 292 293 void dce110_opp_program_clamping_and_pixel_encoding( 294 struct output_pixel_processor *opp, 295 const struct clamping_and_pixel_encoding_params *params); 296 297 void dce110_opp_set_dyn_expansion( 298 struct output_pixel_processor *opp, 299 enum dc_color_space color_sp, 300 enum dc_color_depth color_dpth, 301 enum signal_type signal); 302 303 void dce110_opp_program_fmt( 304 struct output_pixel_processor *opp, 305 struct bit_depth_reduction_params *fmt_bit_depth, 306 struct clamping_and_pixel_encoding_params *clamping); 307 308 void dce110_opp_set_clamping( 309 struct dce110_opp *opp110, 310 const struct clamping_and_pixel_encoding_params *params); 311 312 #endif 313
Indexes created Sun Sep 21 19:09:51 GMT 2025