1 /* $NetBSD: amdgpu_dcn10_link_encoder.c,v 1.3 2021/12/19 11:25:01 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn10_link_encoder.c,v 1.3 2021/12/19 11:25:01 riastradh Exp $"); 30 31 #include <linux/delay.h> 32 #include <linux/slab.h> 33 34 #include "reg_helper.h" 35 36 #include "core_types.h" 37 #include "link_encoder.h" 38 #include "dcn10_link_encoder.h" 39 #include "stream_encoder.h" 40 #include "i2caux_interface.h" 41 #include "dc_bios_types.h" 42 43 #include "gpio_service_interface.h" 44 45 #define CTX \ 46 enc10->base.ctx 47 #define DC_LOGGER \ 48 enc10->base.ctx->logger 49 50 #define REG(reg)\ 51 (enc10->link_regs->reg) 52 53 #undef FN 54 #define FN(reg_name, field_name) \ 55 enc10->link_shift->field_name, enc10->link_mask->field_name 56 57 58 /* 59 * @brief 60 * Trigger Source Select 61 * ASIC-dependent, actual values for register programming 62 */ 63 #define DCN10_DIG_FE_SOURCE_SELECT_INVALID 0x0 64 #define DCN10_DIG_FE_SOURCE_SELECT_DIGA 0x1 65 #define DCN10_DIG_FE_SOURCE_SELECT_DIGB 0x2 66 #define DCN10_DIG_FE_SOURCE_SELECT_DIGC 0x4 67 #define DCN10_DIG_FE_SOURCE_SELECT_DIGD 0x08 68 #define DCN10_DIG_FE_SOURCE_SELECT_DIGE 0x10 69 #define DCN10_DIG_FE_SOURCE_SELECT_DIGF 0x20 70 #define DCN10_DIG_FE_SOURCE_SELECT_DIGG 0x40 71 72 enum { 73 DP_MST_UPDATE_MAX_RETRY = 50 74 }; 75 76 static const struct link_encoder_funcs dcn10_lnk_enc_funcs = { 77 .validate_output_with_stream = 78 dcn10_link_encoder_validate_output_with_stream, 79 .hw_init = dcn10_link_encoder_hw_init, 80 .setup = dcn10_link_encoder_setup, 81 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, 82 .enable_dp_output = dcn10_link_encoder_enable_dp_output, 83 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, 84 .disable_output = dcn10_link_encoder_disable_output, 85 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, 86 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, 87 .update_mst_stream_allocation_table = 88 dcn10_link_encoder_update_mst_stream_allocation_table, 89 .psr_program_dp_dphy_fast_training = 90 dcn10_psr_program_dp_dphy_fast_training, 91 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, 92 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, 93 .enable_hpd = dcn10_link_encoder_enable_hpd, 94 .disable_hpd = dcn10_link_encoder_disable_hpd, 95 .is_dig_enabled = dcn10_is_dig_enabled, 96 .get_dig_frontend = dcn10_get_dig_frontend, 97 .get_dig_mode = dcn10_get_dig_mode, 98 .destroy = dcn10_link_encoder_destroy 99 }; 100 101 static enum bp_result link_transmitter_control( 102 struct dcn10_link_encoder *enc10, 103 struct bp_transmitter_control *cntl) 104 { 105 enum bp_result result; 106 struct dc_bios *bp = enc10->base.ctx->dc_bios; 107 108 result = bp->funcs->transmitter_control(bp, cntl); 109 110 return result; 111 } 112 113 static void enable_phy_bypass_mode( 114 struct dcn10_link_encoder *enc10, 115 bool enable) 116 { 117 /* This register resides in DP back end block; 118 * transmitter is used for the offset 119 */ 120 REG_UPDATE(DP_DPHY_CNTL, DPHY_BYPASS, enable); 121 122 } 123 124 static void disable_prbs_symbols( 125 struct dcn10_link_encoder *enc10, 126 bool disable) 127 { 128 /* This register resides in DP back end block; 129 * transmitter is used for the offset 130 */ 131 REG_UPDATE_4(DP_DPHY_CNTL, 132 DPHY_ATEST_SEL_LANE0, disable, 133 DPHY_ATEST_SEL_LANE1, disable, 134 DPHY_ATEST_SEL_LANE2, disable, 135 DPHY_ATEST_SEL_LANE3, disable); 136 } 137 138 static void disable_prbs_mode( 139 struct dcn10_link_encoder *enc10) 140 { 141 REG_UPDATE(DP_DPHY_PRBS_CNTL, DPHY_PRBS_EN, 0); 142 } 143 144 static void program_pattern_symbols( 145 struct dcn10_link_encoder *enc10, 146 uint16_t pattern_symbols[8]) 147 { 148 /* This register resides in DP back end block; 149 * transmitter is used for the offset 150 */ 151 REG_SET_3(DP_DPHY_SYM0, 0, 152 DPHY_SYM1, pattern_symbols[0], 153 DPHY_SYM2, pattern_symbols[1], 154 DPHY_SYM3, pattern_symbols[2]); 155 156 /* This register resides in DP back end block; 157 * transmitter is used for the offset 158 */ 159 REG_SET_3(DP_DPHY_SYM1, 0, 160 DPHY_SYM4, pattern_symbols[3], 161 DPHY_SYM5, pattern_symbols[4], 162 DPHY_SYM6, pattern_symbols[5]); 163 164 /* This register resides in DP back end block; 165 * transmitter is used for the offset 166 */ 167 REG_SET_2(DP_DPHY_SYM2, 0, 168 DPHY_SYM7, pattern_symbols[6], 169 DPHY_SYM8, pattern_symbols[7]); 170 } 171 172 static void set_dp_phy_pattern_d102( 173 struct dcn10_link_encoder *enc10) 174 { 175 /* Disable PHY Bypass mode to setup the test pattern */ 176 enable_phy_bypass_mode(enc10, false); 177 178 /* For 10-bit PRBS or debug symbols 179 * please use the following sequence: 180 * 181 * Enable debug symbols on the lanes 182 */ 183 disable_prbs_symbols(enc10, true); 184 185 /* Disable PRBS mode */ 186 disable_prbs_mode(enc10); 187 188 /* Program debug symbols to be output */ 189 { 190 uint16_t pattern_symbols[8] = { 191 0x2AA, 0x2AA, 0x2AA, 0x2AA, 192 0x2AA, 0x2AA, 0x2AA, 0x2AA 193 }; 194 195 program_pattern_symbols(enc10, pattern_symbols); 196 } 197 198 /* Enable phy bypass mode to enable the test pattern */ 199 200 enable_phy_bypass_mode(enc10, true); 201 } 202 203 static void set_link_training_complete( 204 struct dcn10_link_encoder *enc10, 205 bool complete) 206 { 207 /* This register resides in DP back end block; 208 * transmitter is used for the offset 209 */ 210 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, complete); 211 212 } 213 214 void dcn10_link_encoder_set_dp_phy_pattern_training_pattern( 215 struct link_encoder *enc, 216 uint32_t index) 217 { 218 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 219 /* Write Training Pattern */ 220 221 REG_WRITE(DP_DPHY_TRAINING_PATTERN_SEL, index); 222 223 /* Set HW Register Training Complete to false */ 224 225 set_link_training_complete(enc10, false); 226 227 /* Disable PHY Bypass mode to output Training Pattern */ 228 229 enable_phy_bypass_mode(enc10, false); 230 231 /* Disable PRBS mode */ 232 disable_prbs_mode(enc10); 233 } 234 235 static void setup_panel_mode( 236 struct dcn10_link_encoder *enc10, 237 enum dp_panel_mode panel_mode) 238 { 239 uint32_t value; 240 241 if (!REG(DP_DPHY_INTERNAL_CTRL)) 242 return; 243 244 value = REG_READ(DP_DPHY_INTERNAL_CTRL); 245 246 switch (panel_mode) { 247 case DP_PANEL_MODE_EDP: 248 value = 0x1; 249 break; 250 case DP_PANEL_MODE_SPECIAL: 251 value = 0x11; 252 break; 253 default: 254 value = 0x0; 255 break; 256 } 257 258 REG_WRITE(DP_DPHY_INTERNAL_CTRL, value); 259 } 260 261 static void set_dp_phy_pattern_symbol_error( 262 struct dcn10_link_encoder *enc10) 263 { 264 /* Disable PHY Bypass mode to setup the test pattern */ 265 enable_phy_bypass_mode(enc10, false); 266 267 /* program correct panel mode*/ 268 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT); 269 270 /* A PRBS23 pattern is used for most DP electrical measurements. */ 271 272 /* Enable PRBS symbols on the lanes */ 273 disable_prbs_symbols(enc10, false); 274 275 /* For PRBS23 Set bit DPHY_PRBS_SEL=1 and Set bit DPHY_PRBS_EN=1 */ 276 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 277 DPHY_PRBS_SEL, 1, 278 DPHY_PRBS_EN, 1); 279 280 /* Enable phy bypass mode to enable the test pattern */ 281 enable_phy_bypass_mode(enc10, true); 282 } 283 284 static void set_dp_phy_pattern_prbs7( 285 struct dcn10_link_encoder *enc10) 286 { 287 /* Disable PHY Bypass mode to setup the test pattern */ 288 enable_phy_bypass_mode(enc10, false); 289 290 /* A PRBS7 pattern is used for most DP electrical measurements. */ 291 292 /* Enable PRBS symbols on the lanes */ 293 disable_prbs_symbols(enc10, false); 294 295 /* For PRBS7 Set bit DPHY_PRBS_SEL=0 and Set bit DPHY_PRBS_EN=1 */ 296 REG_UPDATE_2(DP_DPHY_PRBS_CNTL, 297 DPHY_PRBS_SEL, 0, 298 DPHY_PRBS_EN, 1); 299 300 /* Enable phy bypass mode to enable the test pattern */ 301 enable_phy_bypass_mode(enc10, true); 302 } 303 304 static void set_dp_phy_pattern_80bit_custom( 305 struct dcn10_link_encoder *enc10, 306 const uint8_t *pattern) 307 { 308 /* Disable PHY Bypass mode to setup the test pattern */ 309 enable_phy_bypass_mode(enc10, false); 310 311 /* Enable debug symbols on the lanes */ 312 313 disable_prbs_symbols(enc10, true); 314 315 /* Enable PHY bypass mode to enable the test pattern */ 316 /* TODO is it really needed ? */ 317 318 enable_phy_bypass_mode(enc10, true); 319 320 /* Program 80 bit custom pattern */ 321 { 322 uint16_t pattern_symbols[8]; 323 324 pattern_symbols[0] = 325 ((pattern[1] & 0x03) << 8) | pattern[0]; 326 pattern_symbols[1] = 327 ((pattern[2] & 0x0f) << 6) | ((pattern[1] >> 2) & 0x3f); 328 pattern_symbols[2] = 329 ((pattern[3] & 0x3f) << 4) | ((pattern[2] >> 4) & 0x0f); 330 pattern_symbols[3] = 331 (pattern[4] << 2) | ((pattern[3] >> 6) & 0x03); 332 pattern_symbols[4] = 333 ((pattern[6] & 0x03) << 8) | pattern[5]; 334 pattern_symbols[5] = 335 ((pattern[7] & 0x0f) << 6) | ((pattern[6] >> 2) & 0x3f); 336 pattern_symbols[6] = 337 ((pattern[8] & 0x3f) << 4) | ((pattern[7] >> 4) & 0x0f); 338 pattern_symbols[7] = 339 (pattern[9] << 2) | ((pattern[8] >> 6) & 0x03); 340 341 program_pattern_symbols(enc10, pattern_symbols); 342 } 343 344 /* Enable phy bypass mode to enable the test pattern */ 345 346 enable_phy_bypass_mode(enc10, true); 347 } 348 349 static void set_dp_phy_pattern_hbr2_compliance_cp2520_2( 350 struct dcn10_link_encoder *enc10, 351 unsigned int cp2520_pattern) 352 { 353 354 /* previously there is a register DP_HBR2_EYE_PATTERN 355 * that is enabled to get the pattern. 356 * But it does not work with the latest spec change, 357 * so we are programming the following registers manually. 358 * 359 * The following settings have been confirmed 360 * by Nick Chorney and Sandra Liu 361 */ 362 363 /* Disable PHY Bypass mode to setup the test pattern */ 364 365 enable_phy_bypass_mode(enc10, false); 366 367 /* Setup DIG encoder in DP SST mode */ 368 enc10->base.funcs->setup(&enc10->base, SIGNAL_TYPE_DISPLAY_PORT); 369 370 /* ensure normal panel mode. */ 371 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT); 372 373 /* no vbid after BS (SR) 374 * DP_LINK_FRAMING_CNTL changed history Sandra Liu 375 * 11000260 / 11000104 / 110000FC 376 */ 377 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 378 DP_IDLE_BS_INTERVAL, 0xFC, 379 DP_VBID_DISABLE, 1, 380 DP_VID_ENHANCED_FRAME_MODE, 1); 381 382 /* swap every BS with SR */ 383 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0); 384 385 /* select cp2520 patterns */ 386 if (REG(DP_DPHY_HBR2_PATTERN_CONTROL)) 387 REG_UPDATE(DP_DPHY_HBR2_PATTERN_CONTROL, 388 DP_DPHY_HBR2_PATTERN_CONTROL, cp2520_pattern); 389 else 390 /* pre-DCE11 can only generate CP2520 pattern 2 */ 391 ASSERT(cp2520_pattern == 2); 392 393 /* set link training complete */ 394 set_link_training_complete(enc10, true); 395 396 /* disable video stream */ 397 REG_UPDATE(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, 0); 398 399 /* Disable PHY Bypass mode to setup the test pattern */ 400 enable_phy_bypass_mode(enc10, false); 401 } 402 403 static void set_dp_phy_pattern_passthrough_mode( 404 struct dcn10_link_encoder *enc10, 405 enum dp_panel_mode panel_mode) 406 { 407 /* program correct panel mode */ 408 setup_panel_mode(enc10, panel_mode); 409 410 /* restore LINK_FRAMING_CNTL and DPHY_SCRAMBLER_BS_COUNT 411 * in case we were doing HBR2 compliance pattern before 412 */ 413 REG_UPDATE_3(DP_LINK_FRAMING_CNTL, 414 DP_IDLE_BS_INTERVAL, 0x2000, 415 DP_VBID_DISABLE, 0, 416 DP_VID_ENHANCED_FRAME_MODE, 1); 417 418 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_BS_COUNT, 0x1FF); 419 420 /* set link training complete */ 421 set_link_training_complete(enc10, true); 422 423 /* Disable PHY Bypass mode to setup the test pattern */ 424 enable_phy_bypass_mode(enc10, false); 425 426 /* Disable PRBS mode */ 427 disable_prbs_mode(enc10); 428 } 429 430 /* return value is bit-vector */ 431 static uint8_t get_frontend_source( 432 enum engine_id engine) 433 { 434 switch (engine) { 435 case ENGINE_ID_DIGA: 436 return DCN10_DIG_FE_SOURCE_SELECT_DIGA; 437 case ENGINE_ID_DIGB: 438 return DCN10_DIG_FE_SOURCE_SELECT_DIGB; 439 case ENGINE_ID_DIGC: 440 return DCN10_DIG_FE_SOURCE_SELECT_DIGC; 441 case ENGINE_ID_DIGD: 442 return DCN10_DIG_FE_SOURCE_SELECT_DIGD; 443 case ENGINE_ID_DIGE: 444 return DCN10_DIG_FE_SOURCE_SELECT_DIGE; 445 case ENGINE_ID_DIGF: 446 return DCN10_DIG_FE_SOURCE_SELECT_DIGF; 447 case ENGINE_ID_DIGG: 448 return DCN10_DIG_FE_SOURCE_SELECT_DIGG; 449 default: 450 ASSERT_CRITICAL(false); 451 return DCN10_DIG_FE_SOURCE_SELECT_INVALID; 452 } 453 } 454 455 unsigned int dcn10_get_dig_frontend(struct link_encoder *enc) 456 { 457 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 458 int32_t value; 459 enum engine_id result; 460 461 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &value); 462 463 switch (value) { 464 case DCN10_DIG_FE_SOURCE_SELECT_DIGA: 465 result = ENGINE_ID_DIGA; 466 break; 467 case DCN10_DIG_FE_SOURCE_SELECT_DIGB: 468 result = ENGINE_ID_DIGB; 469 break; 470 case DCN10_DIG_FE_SOURCE_SELECT_DIGC: 471 result = ENGINE_ID_DIGC; 472 break; 473 case DCN10_DIG_FE_SOURCE_SELECT_DIGD: 474 result = ENGINE_ID_DIGD; 475 break; 476 case DCN10_DIG_FE_SOURCE_SELECT_DIGE: 477 result = ENGINE_ID_DIGE; 478 break; 479 case DCN10_DIG_FE_SOURCE_SELECT_DIGF: 480 result = ENGINE_ID_DIGF; 481 break; 482 case DCN10_DIG_FE_SOURCE_SELECT_DIGG: 483 result = ENGINE_ID_DIGG; 484 break; 485 default: 486 // invalid source select DIG 487 ASSERT(false); 488 result = ENGINE_ID_UNKNOWN; 489 } 490 491 return result; 492 493 } 494 495 void enc1_configure_encoder( 496 struct dcn10_link_encoder *enc10, 497 const struct dc_link_settings *link_settings) 498 { 499 /* set number of lanes */ 500 REG_SET(DP_CONFIG, 0, 501 DP_UDI_LANES, link_settings->lane_count - LANE_COUNT_ONE); 502 503 /* setup scrambler */ 504 REG_UPDATE(DP_DPHY_SCRAM_CNTL, DPHY_SCRAMBLER_ADVANCE, 1); 505 } 506 507 void dcn10_psr_program_dp_dphy_fast_training(struct link_encoder *enc, 508 bool exit_link_training_required) 509 { 510 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 511 512 if (exit_link_training_required) 513 REG_UPDATE(DP_DPHY_FAST_TRAINING, 514 DPHY_RX_FAST_TRAINING_CAPABLE, 1); 515 else { 516 REG_UPDATE(DP_DPHY_FAST_TRAINING, 517 DPHY_RX_FAST_TRAINING_CAPABLE, 0); 518 /*In DCE 11, we are able to pre-program a Force SR register 519 * to be able to trigger SR symbol after 5 idle patterns 520 * transmitted. Upon PSR Exit, DMCU can trigger 521 * DPHY_LOAD_BS_COUNT_START = 1. Upon writing 1 to 522 * DPHY_LOAD_BS_COUNT_START and the internal counter 523 * reaches DPHY_LOAD_BS_COUNT, the next BS symbol will be 524 * replaced by SR symbol once. 525 */ 526 527 REG_UPDATE(DP_DPHY_BS_SR_SWAP_CNTL, DPHY_LOAD_BS_COUNT, 0x5); 528 } 529 } 530 531 void dcn10_psr_program_secondary_packet(struct link_encoder *enc, 532 unsigned int sdp_transmit_line_num_deadline) 533 { 534 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 535 536 REG_UPDATE_2(DP_SEC_CNTL1, 537 DP_SEC_GSP0_LINE_NUM, sdp_transmit_line_num_deadline, 538 DP_SEC_GSP0_PRIORITY, 1); 539 } 540 541 bool dcn10_is_dig_enabled(struct link_encoder *enc) 542 { 543 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 544 uint32_t value; 545 546 REG_GET(DIG_BE_EN_CNTL, DIG_ENABLE, &value); 547 return value; 548 } 549 550 static void link_encoder_disable(struct dcn10_link_encoder *enc10) 551 { 552 /* reset training pattern */ 553 REG_SET(DP_DPHY_TRAINING_PATTERN_SEL, 0, 554 DPHY_TRAINING_PATTERN_SEL, 0); 555 556 /* reset training complete */ 557 REG_UPDATE(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, 0); 558 559 /* reset panel mode */ 560 setup_panel_mode(enc10, DP_PANEL_MODE_DEFAULT); 561 } 562 563 static void hpd_initialize( 564 struct dcn10_link_encoder *enc10) 565 { 566 /* Associate HPD with DIG_BE */ 567 enum hpd_source_id hpd_source = enc10->base.hpd_source; 568 569 REG_UPDATE(DIG_BE_CNTL, DIG_HPD_SELECT, hpd_source); 570 } 571 572 bool dcn10_link_encoder_validate_dvi_output( 573 const struct dcn10_link_encoder *enc10, 574 enum signal_type connector_signal, 575 enum signal_type signal, 576 const struct dc_crtc_timing *crtc_timing) 577 { 578 uint32_t max_pixel_clock = TMDS_MAX_PIXEL_CLOCK; 579 580 if (signal == SIGNAL_TYPE_DVI_DUAL_LINK) 581 max_pixel_clock *= 2; 582 583 /* This handles the case of HDMI downgrade to DVI we don't want to 584 * we don't want to cap the pixel clock if the DDI is not DVI. 585 */ 586 if (connector_signal != SIGNAL_TYPE_DVI_DUAL_LINK && 587 connector_signal != SIGNAL_TYPE_DVI_SINGLE_LINK) 588 max_pixel_clock = enc10->base.features.max_hdmi_pixel_clock; 589 590 /* DVI only support RGB pixel encoding */ 591 if (crtc_timing->pixel_encoding != PIXEL_ENCODING_RGB) 592 return false; 593 594 /*connect DVI via adpater's HDMI connector*/ 595 if ((connector_signal == SIGNAL_TYPE_DVI_SINGLE_LINK || 596 connector_signal == SIGNAL_TYPE_HDMI_TYPE_A) && 597 signal != SIGNAL_TYPE_HDMI_TYPE_A && 598 crtc_timing->pix_clk_100hz > (TMDS_MAX_PIXEL_CLOCK * 10)) 599 return false; 600 if (crtc_timing->pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) 601 return false; 602 603 if (crtc_timing->pix_clk_100hz > (max_pixel_clock * 10)) 604 return false; 605 606 /* DVI supports 6/8bpp single-link and 10/16bpp dual-link */ 607 switch (crtc_timing->display_color_depth) { 608 case COLOR_DEPTH_666: 609 case COLOR_DEPTH_888: 610 break; 611 case COLOR_DEPTH_101010: 612 case COLOR_DEPTH_161616: 613 if (signal != SIGNAL_TYPE_DVI_DUAL_LINK) 614 return false; 615 break; 616 default: 617 return false; 618 } 619 620 return true; 621 } 622 623 static bool dcn10_link_encoder_validate_hdmi_output( 624 const struct dcn10_link_encoder *enc10, 625 const struct dc_crtc_timing *crtc_timing, 626 int adjusted_pix_clk_100hz) 627 { 628 enum dc_color_depth max_deep_color = 629 enc10->base.features.max_hdmi_deep_color; 630 631 if (max_deep_color < crtc_timing->display_color_depth) 632 return false; 633 634 if (crtc_timing->display_color_depth < COLOR_DEPTH_888) 635 return false; 636 if (adjusted_pix_clk_100hz < (TMDS_MIN_PIXEL_CLOCK * 10)) 637 return false; 638 639 if ((adjusted_pix_clk_100hz == 0) || 640 (adjusted_pix_clk_100hz > (enc10->base.features.max_hdmi_pixel_clock * 10))) 641 return false; 642 643 /* DCE11 HW does not support 420 */ 644 if (!enc10->base.features.hdmi_ycbcr420_supported && 645 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 646 return false; 647 648 if (!enc10->base.features.flags.bits.HDMI_6GB_EN && 649 adjusted_pix_clk_100hz >= 3000000) 650 return false; 651 if (enc10->base.ctx->dc->debug.hdmi20_disable && 652 crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) 653 return false; 654 return true; 655 } 656 657 bool dcn10_link_encoder_validate_dp_output( 658 const struct dcn10_link_encoder *enc10, 659 const struct dc_crtc_timing *crtc_timing) 660 { 661 if (crtc_timing->pixel_encoding == PIXEL_ENCODING_YCBCR420) { 662 if (!enc10->base.features.dp_ycbcr420_supported) 663 return false; 664 } 665 666 return true; 667 } 668 669 void dcn10_link_encoder_construct( 670 struct dcn10_link_encoder *enc10, 671 const struct encoder_init_data *init_data, 672 const struct encoder_feature_support *enc_features, 673 const struct dcn10_link_enc_registers *link_regs, 674 const struct dcn10_link_enc_aux_registers *aux_regs, 675 const struct dcn10_link_enc_hpd_registers *hpd_regs, 676 const struct dcn10_link_enc_shift *link_shift, 677 const struct dcn10_link_enc_mask *link_mask) 678 { 679 struct bp_encoder_cap_info bp_cap_info = {0}; 680 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 681 enum bp_result result = BP_RESULT_OK; 682 683 enc10->base.funcs = &dcn10_lnk_enc_funcs; 684 enc10->base.ctx = init_data->ctx; 685 enc10->base.id = init_data->encoder; 686 687 enc10->base.hpd_source = init_data->hpd_source; 688 enc10->base.connector = init_data->connector; 689 690 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 691 692 enc10->base.features = *enc_features; 693 694 enc10->base.transmitter = init_data->transmitter; 695 696 /* set the flag to indicate whether driver poll the I2C data pin 697 * while doing the DP sink detect 698 */ 699 700 /* if (dal_adapter_service_is_feature_supported(as, 701 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 702 enc10->base.features.flags.bits. 703 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 704 705 enc10->base.output_signals = 706 SIGNAL_TYPE_DVI_SINGLE_LINK | 707 SIGNAL_TYPE_DVI_DUAL_LINK | 708 SIGNAL_TYPE_LVDS | 709 SIGNAL_TYPE_DISPLAY_PORT | 710 SIGNAL_TYPE_DISPLAY_PORT_MST | 711 SIGNAL_TYPE_EDP | 712 SIGNAL_TYPE_HDMI_TYPE_A; 713 714 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 715 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 716 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 717 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 718 * Prefer DIG assignment is decided by board design. 719 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 720 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 721 * By this, adding DIGG should not hurt DCE 8.0. 722 * This will let DCE 8.1 share DCE 8.0 as much as possible 723 */ 724 725 enc10->link_regs = link_regs; 726 enc10->aux_regs = aux_regs; 727 enc10->hpd_regs = hpd_regs; 728 enc10->link_shift = link_shift; 729 enc10->link_mask = link_mask; 730 731 switch (enc10->base.transmitter) { 732 case TRANSMITTER_UNIPHY_A: 733 enc10->base.preferred_engine = ENGINE_ID_DIGA; 734 break; 735 case TRANSMITTER_UNIPHY_B: 736 enc10->base.preferred_engine = ENGINE_ID_DIGB; 737 break; 738 case TRANSMITTER_UNIPHY_C: 739 enc10->base.preferred_engine = ENGINE_ID_DIGC; 740 break; 741 case TRANSMITTER_UNIPHY_D: 742 enc10->base.preferred_engine = ENGINE_ID_DIGD; 743 break; 744 case TRANSMITTER_UNIPHY_E: 745 enc10->base.preferred_engine = ENGINE_ID_DIGE; 746 break; 747 case TRANSMITTER_UNIPHY_F: 748 enc10->base.preferred_engine = ENGINE_ID_DIGF; 749 break; 750 case TRANSMITTER_UNIPHY_G: 751 enc10->base.preferred_engine = ENGINE_ID_DIGG; 752 break; 753 default: 754 ASSERT_CRITICAL(false); 755 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 756 } 757 758 /* default to one to mirror Windows behavior */ 759 enc10->base.features.flags.bits.HDMI_6GB_EN = 1; 760 761 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, 762 enc10->base.id, &bp_cap_info); 763 764 /* Override features with DCE-specific values */ 765 if (result == BP_RESULT_OK) { 766 enc10->base.features.flags.bits.IS_HBR2_CAPABLE = 767 bp_cap_info.DP_HBR2_EN; 768 enc10->base.features.flags.bits.IS_HBR3_CAPABLE = 769 bp_cap_info.DP_HBR3_EN; 770 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 771 enc10->base.features.flags.bits.DP_IS_USB_C = 772 bp_cap_info.DP_IS_USB_C; 773 } else { 774 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 775 __func__, 776 result); 777 } 778 if (enc10->base.ctx->dc->debug.hdmi20_disable) { 779 enc10->base.features.flags.bits.HDMI_6GB_EN = 0; 780 } 781 } 782 783 bool dcn10_link_encoder_validate_output_with_stream( 784 struct link_encoder *enc, 785 const struct dc_stream_state *stream) 786 { 787 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 788 bool is_valid; 789 790 switch (stream->signal) { 791 case SIGNAL_TYPE_DVI_SINGLE_LINK: 792 case SIGNAL_TYPE_DVI_DUAL_LINK: 793 is_valid = dcn10_link_encoder_validate_dvi_output( 794 enc10, 795 stream->link->connector_signal, 796 stream->signal, 797 &stream->timing); 798 break; 799 case SIGNAL_TYPE_HDMI_TYPE_A: 800 is_valid = dcn10_link_encoder_validate_hdmi_output( 801 enc10, 802 &stream->timing, 803 stream->phy_pix_clk * 10); 804 break; 805 case SIGNAL_TYPE_DISPLAY_PORT: 806 case SIGNAL_TYPE_DISPLAY_PORT_MST: 807 is_valid = dcn10_link_encoder_validate_dp_output( 808 enc10, &stream->timing); 809 break; 810 case SIGNAL_TYPE_EDP: 811 is_valid = (stream->timing.pixel_encoding == PIXEL_ENCODING_RGB) ? true : false; 812 break; 813 case SIGNAL_TYPE_VIRTUAL: 814 is_valid = true; 815 break; 816 default: 817 is_valid = false; 818 break; 819 } 820 821 return is_valid; 822 } 823 824 void dcn10_link_encoder_hw_init( 825 struct link_encoder *enc) 826 { 827 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 828 struct bp_transmitter_control cntl = { 0 }; 829 enum bp_result result; 830 831 cntl.action = TRANSMITTER_CONTROL_INIT; 832 cntl.engine_id = ENGINE_ID_UNKNOWN; 833 cntl.transmitter = enc10->base.transmitter; 834 cntl.connector_obj_id = enc10->base.connector; 835 cntl.lanes_number = LANE_COUNT_FOUR; 836 cntl.coherent = false; 837 cntl.hpd_sel = enc10->base.hpd_source; 838 839 if (enc10->base.connector.id == CONNECTOR_ID_EDP) 840 cntl.signal = SIGNAL_TYPE_EDP; 841 842 result = link_transmitter_control(enc10, &cntl); 843 844 if (result != BP_RESULT_OK) { 845 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 846 __func__); 847 BREAK_TO_DEBUGGER(); 848 return; 849 } 850 851 if (enc10->base.connector.id == CONNECTOR_ID_LVDS) { 852 cntl.action = TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS; 853 854 result = link_transmitter_control(enc10, &cntl); 855 856 ASSERT(result == BP_RESULT_OK); 857 858 } 859 dcn10_aux_initialize(enc10); 860 861 /* reinitialize HPD. 862 * hpd_initialize() will pass DIG_FE id to HW context. 863 * All other routine within HW context will use fe_engine_offset 864 * as DIG_FE id even caller pass DIG_FE id. 865 * So this routine must be called first. 866 */ 867 hpd_initialize(enc10); 868 } 869 870 void dcn10_link_encoder_destroy(struct link_encoder **enc) 871 { 872 kfree(TO_DCN10_LINK_ENC(*enc)); 873 *enc = NULL; 874 } 875 876 void dcn10_link_encoder_setup( 877 struct link_encoder *enc, 878 enum signal_type signal) 879 { 880 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 881 882 switch (signal) { 883 case SIGNAL_TYPE_EDP: 884 case SIGNAL_TYPE_DISPLAY_PORT: 885 /* DP SST */ 886 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 0); 887 break; 888 case SIGNAL_TYPE_LVDS: 889 /* LVDS */ 890 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 1); 891 break; 892 case SIGNAL_TYPE_DVI_SINGLE_LINK: 893 case SIGNAL_TYPE_DVI_DUAL_LINK: 894 /* TMDS-DVI */ 895 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 2); 896 break; 897 case SIGNAL_TYPE_HDMI_TYPE_A: 898 /* TMDS-HDMI */ 899 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 3); 900 break; 901 case SIGNAL_TYPE_DISPLAY_PORT_MST: 902 /* DP MST */ 903 REG_UPDATE(DIG_BE_CNTL, DIG_MODE, 5); 904 break; 905 default: 906 ASSERT_CRITICAL(false); 907 /* invalid mode ! */ 908 break; 909 } 910 911 } 912 913 /* TODO: still need depth or just pass in adjusted pixel clock? */ 914 void dcn10_link_encoder_enable_tmds_output( 915 struct link_encoder *enc, 916 enum clock_source_id clock_source, 917 enum dc_color_depth color_depth, 918 enum signal_type signal, 919 uint32_t pixel_clock) 920 { 921 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 922 struct bp_transmitter_control cntl = { 0 }; 923 enum bp_result result; 924 925 /* Enable the PHY */ 926 927 cntl.action = TRANSMITTER_CONTROL_ENABLE; 928 cntl.engine_id = enc->preferred_engine; 929 cntl.transmitter = enc10->base.transmitter; 930 cntl.pll_id = clock_source; 931 cntl.signal = signal; 932 if (cntl.signal == SIGNAL_TYPE_DVI_DUAL_LINK) 933 cntl.lanes_number = 8; 934 else 935 cntl.lanes_number = 4; 936 937 cntl.hpd_sel = enc10->base.hpd_source; 938 939 cntl.pixel_clock = pixel_clock; 940 cntl.color_depth = color_depth; 941 942 result = link_transmitter_control(enc10, &cntl); 943 944 if (result != BP_RESULT_OK) { 945 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 946 __func__); 947 BREAK_TO_DEBUGGER(); 948 } 949 } 950 951 /* enables DP PHY output */ 952 void dcn10_link_encoder_enable_dp_output( 953 struct link_encoder *enc, 954 const struct dc_link_settings *link_settings, 955 enum clock_source_id clock_source) 956 { 957 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 958 struct bp_transmitter_control cntl = { 0 }; 959 enum bp_result result; 960 961 /* Enable the PHY */ 962 963 /* number_of_lanes is used for pixel clock adjust, 964 * but it's not passed to asic_control. 965 * We need to set number of lanes manually. 966 */ 967 enc1_configure_encoder(enc10, link_settings); 968 969 cntl.action = TRANSMITTER_CONTROL_ENABLE; 970 cntl.engine_id = enc->preferred_engine; 971 cntl.transmitter = enc10->base.transmitter; 972 cntl.pll_id = clock_source; 973 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT; 974 cntl.lanes_number = link_settings->lane_count; 975 cntl.hpd_sel = enc10->base.hpd_source; 976 cntl.pixel_clock = link_settings->link_rate 977 * LINK_RATE_REF_FREQ_IN_KHZ; 978 /* TODO: check if undefined works */ 979 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 980 981 result = link_transmitter_control(enc10, &cntl); 982 983 if (result != BP_RESULT_OK) { 984 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 985 __func__); 986 BREAK_TO_DEBUGGER(); 987 } 988 } 989 990 /* enables DP PHY output in MST mode */ 991 void dcn10_link_encoder_enable_dp_mst_output( 992 struct link_encoder *enc, 993 const struct dc_link_settings *link_settings, 994 enum clock_source_id clock_source) 995 { 996 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 997 struct bp_transmitter_control cntl = { 0 }; 998 enum bp_result result; 999 1000 /* Enable the PHY */ 1001 1002 /* number_of_lanes is used for pixel clock adjust, 1003 * but it's not passed to asic_control. 1004 * We need to set number of lanes manually. 1005 */ 1006 enc1_configure_encoder(enc10, link_settings); 1007 1008 cntl.action = TRANSMITTER_CONTROL_ENABLE; 1009 cntl.engine_id = ENGINE_ID_UNKNOWN; 1010 cntl.transmitter = enc10->base.transmitter; 1011 cntl.pll_id = clock_source; 1012 cntl.signal = SIGNAL_TYPE_DISPLAY_PORT_MST; 1013 cntl.lanes_number = link_settings->lane_count; 1014 cntl.hpd_sel = enc10->base.hpd_source; 1015 cntl.pixel_clock = link_settings->link_rate 1016 * LINK_RATE_REF_FREQ_IN_KHZ; 1017 /* TODO: check if undefined works */ 1018 cntl.color_depth = COLOR_DEPTH_UNDEFINED; 1019 1020 result = link_transmitter_control(enc10, &cntl); 1021 1022 if (result != BP_RESULT_OK) { 1023 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1024 __func__); 1025 BREAK_TO_DEBUGGER(); 1026 } 1027 } 1028 /* 1029 * @brief 1030 * Disable transmitter and its encoder 1031 */ 1032 void dcn10_link_encoder_disable_output( 1033 struct link_encoder *enc, 1034 enum signal_type signal) 1035 { 1036 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 1037 struct bp_transmitter_control cntl = { 0 }; 1038 enum bp_result result; 1039 1040 if (!dcn10_is_dig_enabled(enc)) { 1041 /* OF_SKIP_POWER_DOWN_INACTIVE_ENCODER */ 1042 /*in DP_Alt_No_Connect case, we turn off the dig already, 1043 after excuation the PHY w/a sequence, not allow touch PHY any more*/ 1044 return; 1045 } 1046 /* Power-down RX and disable GPU PHY should be paired. 1047 * Disabling PHY without powering down RX may cause 1048 * symbol lock loss, on which we will get DP Sink interrupt. 1049 */ 1050 1051 /* There is a case for the DP active dongles 1052 * where we want to disable the PHY but keep RX powered, 1053 * for those we need to ignore DP Sink interrupt 1054 * by checking lane count that has been set 1055 * on the last do_enable_output(). 1056 */ 1057 1058 /* disable transmitter */ 1059 cntl.action = TRANSMITTER_CONTROL_DISABLE; 1060 cntl.transmitter = enc10->base.transmitter; 1061 cntl.hpd_sel = enc10->base.hpd_source; 1062 cntl.signal = signal; 1063 cntl.connector_obj_id = enc10->base.connector; 1064 1065 result = link_transmitter_control(enc10, &cntl); 1066 1067 if (result != BP_RESULT_OK) { 1068 DC_LOG_ERROR("%s: Failed to execute VBIOS command table!\n", 1069 __func__); 1070 BREAK_TO_DEBUGGER(); 1071 return; 1072 } 1073 1074 /* disable encoder */ 1075 if (dc_is_dp_signal(signal)) 1076 link_encoder_disable(enc10); 1077 } 1078 1079 void dcn10_link_encoder_dp_set_lane_settings( 1080 struct link_encoder *enc, 1081 const struct link_training_settings *link_settings) 1082 { 1083 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 1084 union dpcd_training_lane_set training_lane_set = { { 0 } }; 1085 int32_t lane = 0; 1086 struct bp_transmitter_control cntl = { 0 }; 1087 1088 if (!link_settings) { 1089 BREAK_TO_DEBUGGER(); 1090 return; 1091 } 1092 1093 cntl.action = TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS; 1094 cntl.transmitter = enc10->base.transmitter; 1095 cntl.connector_obj_id = enc10->base.connector; 1096 cntl.lanes_number = link_settings->link_settings.lane_count; 1097 cntl.hpd_sel = enc10->base.hpd_source; 1098 cntl.pixel_clock = link_settings->link_settings.link_rate * 1099 LINK_RATE_REF_FREQ_IN_KHZ; 1100 1101 for (lane = 0; lane < link_settings->link_settings.lane_count; lane++) { 1102 /* translate lane settings */ 1103 1104 training_lane_set.bits.VOLTAGE_SWING_SET = 1105 link_settings->lane_settings[lane].VOLTAGE_SWING; 1106 training_lane_set.bits.PRE_EMPHASIS_SET = 1107 link_settings->lane_settings[lane].PRE_EMPHASIS; 1108 1109 /* post cursor 2 setting only applies to HBR2 link rate */ 1110 if (link_settings->link_settings.link_rate == LINK_RATE_HIGH2) { 1111 /* this is passed to VBIOS 1112 * to program post cursor 2 level 1113 */ 1114 training_lane_set.bits.POST_CURSOR2_SET = 1115 link_settings->lane_settings[lane].POST_CURSOR2; 1116 } 1117 1118 cntl.lane_select = lane; 1119 cntl.lane_settings = training_lane_set.raw; 1120 1121 /* call VBIOS table to set voltage swing and pre-emphasis */ 1122 link_transmitter_control(enc10, &cntl); 1123 } 1124 } 1125 1126 /* set DP PHY test and training patterns */ 1127 void dcn10_link_encoder_dp_set_phy_pattern( 1128 struct link_encoder *enc, 1129 const struct encoder_set_dp_phy_pattern_param *param) 1130 { 1131 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 1132 1133 switch (param->dp_phy_pattern) { 1134 case DP_TEST_PATTERN_TRAINING_PATTERN1: 1135 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 0); 1136 break; 1137 case DP_TEST_PATTERN_TRAINING_PATTERN2: 1138 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 1); 1139 break; 1140 case DP_TEST_PATTERN_TRAINING_PATTERN3: 1141 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 2); 1142 break; 1143 case DP_TEST_PATTERN_TRAINING_PATTERN4: 1144 dcn10_link_encoder_set_dp_phy_pattern_training_pattern(enc, 3); 1145 break; 1146 case DP_TEST_PATTERN_D102: 1147 set_dp_phy_pattern_d102(enc10); 1148 break; 1149 case DP_TEST_PATTERN_SYMBOL_ERROR: 1150 set_dp_phy_pattern_symbol_error(enc10); 1151 break; 1152 case DP_TEST_PATTERN_PRBS7: 1153 set_dp_phy_pattern_prbs7(enc10); 1154 break; 1155 case DP_TEST_PATTERN_80BIT_CUSTOM: 1156 set_dp_phy_pattern_80bit_custom( 1157 enc10, param->custom_pattern); 1158 break; 1159 case DP_TEST_PATTERN_CP2520_1: 1160 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 1); 1161 break; 1162 case DP_TEST_PATTERN_CP2520_2: 1163 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 2); 1164 break; 1165 case DP_TEST_PATTERN_CP2520_3: 1166 set_dp_phy_pattern_hbr2_compliance_cp2520_2(enc10, 3); 1167 break; 1168 case DP_TEST_PATTERN_VIDEO_MODE: { 1169 set_dp_phy_pattern_passthrough_mode( 1170 enc10, param->dp_panel_mode); 1171 break; 1172 } 1173 1174 default: 1175 /* invalid phy pattern */ 1176 ASSERT_CRITICAL(false); 1177 break; 1178 } 1179 } 1180 1181 static void fill_stream_allocation_row_info( 1182 const struct link_mst_stream_allocation *stream_allocation, 1183 uint32_t *src, 1184 uint32_t *slots) 1185 { 1186 const struct stream_encoder *stream_enc = stream_allocation->stream_enc; 1187 1188 if (stream_enc) { 1189 *src = stream_enc->id; 1190 *slots = stream_allocation->slot_count; 1191 } else { 1192 *src = 0; 1193 *slots = 0; 1194 } 1195 } 1196 1197 /* programs DP MST VC payload allocation */ 1198 void dcn10_link_encoder_update_mst_stream_allocation_table( 1199 struct link_encoder *enc, 1200 const struct link_mst_stream_allocation_table *table) 1201 { 1202 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 1203 uint32_t value0 __unused = 0; 1204 uint32_t value1 = 0; 1205 uint32_t value2 = 0; 1206 uint32_t slots = 0; 1207 uint32_t src = 0; 1208 uint32_t retries = 0; 1209 1210 /* For CZ, there are only 3 pipes. So Virtual channel is up 3.*/ 1211 1212 /* --- Set MSE Stream Attribute - 1213 * Setup VC Payload Table on Tx Side, 1214 * Issue allocation change trigger 1215 * to commit payload on both tx and rx side 1216 */ 1217 1218 /* we should clean-up table each time */ 1219 1220 if (table->stream_count >= 1) { 1221 fill_stream_allocation_row_info( 1222 &table->stream_allocations[0], 1223 &src, 1224 &slots); 1225 } else { 1226 src = 0; 1227 slots = 0; 1228 } 1229 1230 REG_UPDATE_2(DP_MSE_SAT0, 1231 DP_MSE_SAT_SRC0, src, 1232 DP_MSE_SAT_SLOT_COUNT0, slots); 1233 1234 if (table->stream_count >= 2) { 1235 fill_stream_allocation_row_info( 1236 &table->stream_allocations[1], 1237 &src, 1238 &slots); 1239 } else { 1240 src = 0; 1241 slots = 0; 1242 } 1243 1244 REG_UPDATE_2(DP_MSE_SAT0, 1245 DP_MSE_SAT_SRC1, src, 1246 DP_MSE_SAT_SLOT_COUNT1, slots); 1247 1248 if (table->stream_count >= 3) { 1249 fill_stream_allocation_row_info( 1250 &table->stream_allocations[2], 1251 &src, 1252 &slots); 1253 } else { 1254 src = 0; 1255 slots = 0; 1256 } 1257 1258 REG_UPDATE_2(DP_MSE_SAT1, 1259 DP_MSE_SAT_SRC2, src, 1260 DP_MSE_SAT_SLOT_COUNT2, slots); 1261 1262 if (table->stream_count >= 4) { 1263 fill_stream_allocation_row_info( 1264 &table->stream_allocations[3], 1265 &src, 1266 &slots); 1267 } else { 1268 src = 0; 1269 slots = 0; 1270 } 1271 1272 REG_UPDATE_2(DP_MSE_SAT1, 1273 DP_MSE_SAT_SRC3, src, 1274 DP_MSE_SAT_SLOT_COUNT3, slots); 1275 1276 /* --- wait for transaction finish */ 1277 1278 /* send allocation change trigger (ACT) ? 1279 * this step first sends the ACT, 1280 * then double buffers the SAT into the hardware 1281 * making the new allocation active on the DP MST mode link 1282 */ 1283 1284 /* DP_MSE_SAT_UPDATE: 1285 * 0 - No Action 1286 * 1 - Update SAT with trigger 1287 * 2 - Update SAT without trigger 1288 */ 1289 REG_UPDATE(DP_MSE_SAT_UPDATE, 1290 DP_MSE_SAT_UPDATE, 1); 1291 1292 /* wait for update to complete 1293 * (i.e. DP_MSE_SAT_UPDATE field is reset to 0) 1294 * then wait for the transmission 1295 * of at least 16 MTP headers on immediate local link. 1296 * i.e. DP_MSE_16_MTP_KEEPOUT field (read only) is reset to 0 1297 * a value of 1 indicates that DP MST mode 1298 * is in the 16 MTP keepout region after a VC has been added. 1299 * MST stream bandwidth (VC rate) can be configured 1300 * after this bit is cleared 1301 */ 1302 do { 1303 udelay(10); 1304 1305 value0 = REG_READ(DP_MSE_SAT_UPDATE); 1306 1307 REG_GET(DP_MSE_SAT_UPDATE, 1308 DP_MSE_SAT_UPDATE, &value1); 1309 1310 REG_GET(DP_MSE_SAT_UPDATE, 1311 DP_MSE_16_MTP_KEEPOUT, &value2); 1312 1313 /* bit field DP_MSE_SAT_UPDATE is set to 1 already */ 1314 if (!value1 && !value2) 1315 break; 1316 ++retries; 1317 } while (retries < DP_MST_UPDATE_MAX_RETRY); 1318 } 1319 1320 void dcn10_link_encoder_connect_dig_be_to_fe( 1321 struct link_encoder *enc, 1322 enum engine_id engine, 1323 bool connect) 1324 { 1325 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 1326 uint32_t field; 1327 1328 if (engine != ENGINE_ID_UNKNOWN) { 1329 1330 REG_GET(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, &field); 1331 1332 if (connect) 1333 field |= get_frontend_source(engine); 1334 else 1335 field &= ~get_frontend_source(engine); 1336 1337 REG_UPDATE(DIG_BE_CNTL, DIG_FE_SOURCE_SELECT, field); 1338 } 1339 } 1340 1341 1342 #define HPD_REG(reg)\ 1343 (enc10->hpd_regs->reg) 1344 1345 #define HPD_REG_READ(reg_name) \ 1346 dm_read_reg(CTX, HPD_REG(reg_name)) 1347 1348 #define HPD_REG_UPDATE_N(reg_name, n, ...) \ 1349 generic_reg_update_ex(CTX, \ 1350 HPD_REG(reg_name), \ 1351 n, __VA_ARGS__) 1352 1353 #define HPD_REG_UPDATE(reg_name, field, val) \ 1354 HPD_REG_UPDATE_N(reg_name, 1, \ 1355 FN(reg_name, field), val) 1356 1357 void dcn10_link_encoder_enable_hpd(struct link_encoder *enc) 1358 { 1359 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 1360 1361 HPD_REG_UPDATE(DC_HPD_CONTROL, 1362 DC_HPD_EN, 1); 1363 } 1364 1365 void dcn10_link_encoder_disable_hpd(struct link_encoder *enc) 1366 { 1367 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 1368 1369 HPD_REG_UPDATE(DC_HPD_CONTROL, 1370 DC_HPD_EN, 0); 1371 } 1372 1373 1374 #define AUX_REG(reg)\ 1375 (enc10->aux_regs->reg) 1376 1377 #define AUX_REG_READ(reg_name) \ 1378 dm_read_reg(CTX, AUX_REG(reg_name)) 1379 1380 #define AUX_REG_UPDATE_N(reg_name, n, ...) \ 1381 generic_reg_update_ex(CTX, \ 1382 AUX_REG(reg_name), \ 1383 n, __VA_ARGS__) 1384 1385 #define AUX_REG_UPDATE(reg_name, field, val) \ 1386 AUX_REG_UPDATE_N(reg_name, 1, \ 1387 FN(reg_name, field), val) 1388 1389 #define AUX_REG_UPDATE_2(reg, f1, v1, f2, v2) \ 1390 AUX_REG_UPDATE_N(reg, 2,\ 1391 FN(reg, f1), v1,\ 1392 FN(reg, f2), v2) 1393 1394 void dcn10_aux_initialize(struct dcn10_link_encoder *enc10) 1395 { 1396 enum hpd_source_id hpd_source = enc10->base.hpd_source; 1397 1398 AUX_REG_UPDATE_2(AUX_CONTROL, 1399 AUX_HPD_SEL, hpd_source, 1400 AUX_LS_READ_EN, 0); 1401 1402 /* 1/4 window (the maximum allowed) */ 1403 AUX_REG_UPDATE(AUX_DPHY_RX_CONTROL0, 1404 AUX_RX_RECEIVE_WINDOW, 0); 1405 } 1406 1407 enum signal_type dcn10_get_dig_mode( 1408 struct link_encoder *enc) 1409 { 1410 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 1411 uint32_t value; 1412 REG_GET(DIG_BE_CNTL, DIG_MODE, &value); 1413 switch (value) { 1414 case 1: 1415 return SIGNAL_TYPE_DISPLAY_PORT; 1416 case 2: 1417 return SIGNAL_TYPE_DVI_SINGLE_LINK; 1418 case 3: 1419 return SIGNAL_TYPE_HDMI_TYPE_A; 1420 case 5: 1421 return SIGNAL_TYPE_DISPLAY_PORT_MST; 1422 default: 1423 return SIGNAL_TYPE_NONE; 1424 } 1425 return SIGNAL_TYPE_NONE; 1426 } 1427 1428
Indexes created Sun Sep 21 20:09:37 GMT 2025