1 /* $NetBSD: dcn10_opp.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* Copyright 2012-15 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DC_OPP_DCN10_H__ 28 #define __DC_OPP_DCN10_H__ 29 30 #include "opp.h" 31 32 #define TO_DCN10_OPP(opp)\ 33 container_of(opp, struct dcn10_opp, base) 34 35 #define OPP_SF(reg_name, field_name, post_fix)\ 36 .field_name = reg_name ## __ ## field_name ## post_fix 37 38 #define OPP_REG_LIST_DCN(id) \ 39 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \ 40 SRI(FMT_CONTROL, FMT, id), \ 41 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \ 42 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \ 43 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \ 44 SRI(FMT_CLAMP_CNTL, FMT, id), \ 45 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \ 46 SRI(FMT_MAP420_MEMORY_CONTROL, FMT, id), \ 47 SRI(OPPBUF_CONTROL, OPPBUF, id),\ 48 SRI(OPPBUF_3D_PARAMETERS_0, OPPBUF, id), \ 49 SRI(OPPBUF_3D_PARAMETERS_1, OPPBUF, id), \ 50 SRI(OPP_PIPE_CONTROL, OPP_PIPE, id) 51 52 #define OPP_REG_LIST_DCN10(id) \ 53 OPP_REG_LIST_DCN(id) 54 55 #define OPP_COMMON_REG_VARIABLE_LIST \ 56 uint32_t FMT_BIT_DEPTH_CONTROL; \ 57 uint32_t FMT_CONTROL; \ 58 uint32_t FMT_DITHER_RAND_R_SEED; \ 59 uint32_t FMT_DITHER_RAND_G_SEED; \ 60 uint32_t FMT_DITHER_RAND_B_SEED; \ 61 uint32_t FMT_CLAMP_CNTL; \ 62 uint32_t FMT_DYNAMIC_EXP_CNTL; \ 63 uint32_t FMT_MAP420_MEMORY_CONTROL; \ 64 uint32_t OPPBUF_CONTROL; \ 65 uint32_t OPPBUF_CONTROL1; \ 66 uint32_t OPPBUF_3D_PARAMETERS_0; \ 67 uint32_t OPPBUF_3D_PARAMETERS_1; \ 68 uint32_t OPP_PIPE_CONTROL 69 70 #define OPP_MASK_SH_LIST_DCN(mask_sh) \ 71 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh), \ 72 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh), \ 73 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh), \ 74 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh), \ 75 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh), \ 76 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh), \ 77 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_TEMPORAL_DITHER_EN, mask_sh), \ 78 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh), \ 79 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh), \ 80 OPP_SF(FMT0_FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh), \ 81 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, mask_sh), \ 82 OPP_SF(FMT0_FMT_CONTROL, FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, mask_sh), \ 83 OPP_SF(FMT0_FMT_CONTROL, FMT_PIXEL_ENCODING, mask_sh), \ 84 OPP_SF(FMT0_FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, mask_sh), \ 85 OPP_SF(FMT0_FMT_DITHER_RAND_R_SEED, FMT_RAND_R_SEED, mask_sh), \ 86 OPP_SF(FMT0_FMT_DITHER_RAND_G_SEED, FMT_RAND_G_SEED, mask_sh), \ 87 OPP_SF(FMT0_FMT_DITHER_RAND_B_SEED, FMT_RAND_B_SEED, mask_sh), \ 88 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_DATA_EN, mask_sh), \ 89 OPP_SF(FMT0_FMT_CLAMP_CNTL, FMT_CLAMP_COLOR_FORMAT, mask_sh), \ 90 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_EN, mask_sh), \ 91 OPP_SF(FMT0_FMT_DYNAMIC_EXP_CNTL, FMT_DYNAMIC_EXP_MODE, mask_sh), \ 92 OPP_SF(FMT0_FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, mask_sh), \ 93 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_ACTIVE_WIDTH, mask_sh),\ 94 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_PIXEL_REPETITION, mask_sh),\ 95 OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE1_SIZE, mask_sh), \ 96 OPP_SF(OPPBUF0_OPPBUF_3D_PARAMETERS_0, OPPBUF_3D_VACT_SPACE2_SIZE, mask_sh), \ 97 OPP_SF(OPP_PIPE0_OPP_PIPE_CONTROL, OPP_PIPE_CLOCK_EN, mask_sh) 98 99 #define OPP_MASK_SH_LIST_DCN10(mask_sh) \ 100 OPP_MASK_SH_LIST_DCN(mask_sh), \ 101 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_DISPLAY_SEGMENTATION, mask_sh),\ 102 OPP_SF(OPPBUF0_OPPBUF_CONTROL, OPPBUF_OVERLAP_PIXEL_NUM, mask_sh) 103 104 #define OPP_DCN10_REG_FIELD_LIST(type) \ 105 type FMT_TRUNCATE_EN; \ 106 type FMT_TRUNCATE_DEPTH; \ 107 type FMT_TRUNCATE_MODE; \ 108 type FMT_SPATIAL_DITHER_EN; \ 109 type FMT_SPATIAL_DITHER_MODE; \ 110 type FMT_SPATIAL_DITHER_DEPTH; \ 111 type FMT_TEMPORAL_DITHER_EN; \ 112 type FMT_HIGHPASS_RANDOM_ENABLE; \ 113 type FMT_FRAME_RANDOM_ENABLE; \ 114 type FMT_RGB_RANDOM_ENABLE; \ 115 type FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX; \ 116 type FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP; \ 117 type FMT_RAND_R_SEED; \ 118 type FMT_RAND_G_SEED; \ 119 type FMT_RAND_B_SEED; \ 120 type FMT_PIXEL_ENCODING; \ 121 type FMT_SUBSAMPLING_MODE; \ 122 type FMT_CBCR_BIT_REDUCTION_BYPASS; \ 123 type FMT_CLAMP_DATA_EN; \ 124 type FMT_CLAMP_COLOR_FORMAT; \ 125 type FMT_DYNAMIC_EXP_EN; \ 126 type FMT_DYNAMIC_EXP_MODE; \ 127 type FMT_MAP420MEM_PWR_FORCE; \ 128 type FMT_STEREOSYNC_OVERRIDE; \ 129 type OPPBUF_ACTIVE_WIDTH;\ 130 type OPPBUF_PIXEL_REPETITION;\ 131 type OPPBUF_DISPLAY_SEGMENTATION;\ 132 type OPPBUF_OVERLAP_PIXEL_NUM;\ 133 type OPPBUF_NUM_SEGMENT_PADDED_PIXELS; \ 134 type OPPBUF_3D_VACT_SPACE1_SIZE; \ 135 type OPPBUF_3D_VACT_SPACE2_SIZE; \ 136 type OPP_PIPE_CLOCK_EN 137 138 struct dcn10_opp_registers { 139 OPP_COMMON_REG_VARIABLE_LIST; 140 }; 141 142 struct dcn10_opp_shift { 143 OPP_DCN10_REG_FIELD_LIST(uint8_t); 144 }; 145 146 struct dcn10_opp_mask { 147 OPP_DCN10_REG_FIELD_LIST(uint32_t); 148 }; 149 150 struct dcn10_opp { 151 struct output_pixel_processor base; 152 153 const struct dcn10_opp_registers *regs; 154 const struct dcn10_opp_shift *opp_shift; 155 const struct dcn10_opp_mask *opp_mask; 156 157 bool is_write_to_ram_a_safe; 158 }; 159 160 void dcn10_opp_construct(struct dcn10_opp *oppn10, 161 struct dc_context *ctx, 162 uint32_t inst, 163 const struct dcn10_opp_registers *regs, 164 const struct dcn10_opp_shift *opp_shift, 165 const struct dcn10_opp_mask *opp_mask); 166 167 void opp1_set_dyn_expansion( 168 struct output_pixel_processor *opp, 169 enum dc_color_space color_sp, 170 enum dc_color_depth color_dpth, 171 enum signal_type signal); 172 173 void opp1_program_fmt( 174 struct output_pixel_processor *opp, 175 struct bit_depth_reduction_params *fmt_bit_depth, 176 struct clamping_and_pixel_encoding_params *clamping); 177 178 void opp1_program_bit_depth_reduction( 179 struct output_pixel_processor *opp, 180 const struct bit_depth_reduction_params *params); 181 182 void opp1_program_stereo( 183 struct output_pixel_processor *opp, 184 bool enable, 185 const struct dc_crtc_timing *timing); 186 187 void opp1_pipe_clock_control(struct output_pixel_processor *opp, bool enable); 188 189 void opp1_destroy(struct output_pixel_processor **opp); 190 191 #endif 192
Indexes created Wed Sep 24 05:09:52 GMT 2025