1 /* $NetBSD: amdgpu_dcn20_init.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn20_init.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $"); 30 31 #include "dce110/dce110_hw_sequencer.h" 32 #include "dcn10/dcn10_hw_sequencer.h" 33 #include "dcn20_hwseq.h" 34 35 static const struct hw_sequencer_funcs dcn20_funcs = { 36 .program_gamut_remap = dcn10_program_gamut_remap, 37 .init_hw = dcn10_init_hw, 38 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 39 .apply_ctx_for_surface = NULL, 40 .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, 41 .update_plane_addr = dcn20_update_plane_addr, 42 .update_dchub = dcn10_update_dchub, 43 .update_pending_status = dcn10_update_pending_status, 44 .program_output_csc = dcn20_program_output_csc, 45 .enable_accelerated_mode = dce110_enable_accelerated_mode, 46 .enable_timing_synchronization = dcn10_enable_timing_synchronization, 47 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, 48 .update_info_frame = dce110_update_info_frame, 49 .send_immediate_sdp_message = dcn10_send_immediate_sdp_message, 50 .enable_stream = dcn20_enable_stream, 51 .disable_stream = dce110_disable_stream, 52 .unblank_stream = dcn20_unblank_stream, 53 .blank_stream = dce110_blank_stream, 54 .enable_audio_stream = dce110_enable_audio_stream, 55 .disable_audio_stream = dce110_disable_audio_stream, 56 .disable_plane = dcn20_disable_plane, 57 .pipe_control_lock = dcn20_pipe_control_lock, 58 .pipe_control_lock_global = dcn20_pipe_control_lock_global, 59 .prepare_bandwidth = dcn20_prepare_bandwidth, 60 .optimize_bandwidth = dcn20_optimize_bandwidth, 61 .update_bandwidth = dcn20_update_bandwidth, 62 .set_drr = dcn10_set_drr, 63 .get_position = dcn10_get_position, 64 .set_static_screen_control = dcn10_set_static_screen_control, 65 .setup_stereo = dcn10_setup_stereo, 66 .set_avmute = dce110_set_avmute, 67 .log_hw_state = dcn10_log_hw_state, 68 .get_hw_state = dcn10_get_hw_state, 69 .clear_status_bits = dcn10_clear_status_bits, 70 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, 71 .edp_power_control = dce110_edp_power_control, 72 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 73 .set_cursor_position = dcn10_set_cursor_position, 74 .set_cursor_attribute = dcn10_set_cursor_attribute, 75 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, 76 .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, 77 .set_clock = dcn10_set_clock, 78 .get_clock = dcn10_get_clock, 79 .program_triplebuffer = dcn20_program_triple_buffer, 80 .enable_writeback = dcn20_enable_writeback, 81 .disable_writeback = dcn20_disable_writeback, 82 .dmdata_status_done = dcn20_dmdata_status_done, 83 .program_dmdata_engine = dcn20_program_dmdata_engine, 84 .set_dmdata_attributes = dcn20_set_dmdata_attributes, 85 .init_sys_ctx = dcn20_init_sys_ctx, 86 .init_vm_ctx = dcn20_init_vm_ctx, 87 .set_flip_control_gsl = dcn20_set_flip_control_gsl, 88 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, 89 }; 90 91 static const struct hwseq_private_funcs dcn20_private_funcs = { 92 .init_pipes = dcn10_init_pipes, 93 .update_plane_addr = dcn20_update_plane_addr, 94 .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, 95 .update_mpcc = dcn20_update_mpcc, 96 .set_input_transfer_func = dcn20_set_input_transfer_func, 97 .set_output_transfer_func = dcn20_set_output_transfer_func, 98 .power_down = dce110_power_down, 99 .enable_display_power_gating = dcn10_dummy_display_power_gating, 100 .blank_pixel_data = dcn20_blank_pixel_data, 101 .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap, 102 .enable_stream_timing = dcn20_enable_stream_timing, 103 .edp_backlight_control = dce110_edp_backlight_control, 104 .disable_stream_gating = dcn20_disable_stream_gating, 105 .enable_stream_gating = dcn20_enable_stream_gating, 106 .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, 107 .did_underflow_occur = dcn10_did_underflow_occur, 108 .init_blank = dcn20_init_blank, 109 .disable_vga = dcn20_disable_vga, 110 .bios_golden_init = dcn10_bios_golden_init, 111 .plane_atomic_disable = dcn20_plane_atomic_disable, 112 .plane_atomic_power_down = dcn10_plane_atomic_power_down, 113 .enable_power_gating_plane = dcn20_enable_power_gating_plane, 114 .dpp_pg_control = dcn20_dpp_pg_control, 115 .hubp_pg_control = dcn20_hubp_pg_control, 116 .dsc_pg_control = NULL, 117 .update_odm = dcn20_update_odm, 118 .dsc_pg_control = dcn20_dsc_pg_control, 119 .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color, 120 .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color, 121 .set_hdr_multiplier = dcn10_set_hdr_multiplier, 122 .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, 123 .wait_for_blank_complete = dcn20_wait_for_blank_complete, 124 .dccg_init = dcn20_dccg_init, 125 .set_blend_lut = dcn20_set_blend_lut, 126 .set_shaper_3dlut = dcn20_set_shaper_3dlut, 127 }; 128 129 void dcn20_hw_sequencer_construct(struct dc *dc) 130 { 131 dc->hwss = dcn20_funcs; 132 dc->hwseq->funcs = dcn20_private_funcs; 133 134 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 135 dc->hwss.init_hw = dcn20_fpga_init_hw; 136 dc->hwseq->funcs.init_pipes = NULL; 137 } 138 } 139
Indexes created Mon Sep 22 13:09:51 GMT 2025