1 /* $NetBSD: amdgpu_dcn20_link_encoder.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn20_link_encoder.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $"); 30 31 #include "reg_helper.h" 32 33 #include "core_types.h" 34 #include "link_encoder.h" 35 #include "dcn20_link_encoder.h" 36 #include "stream_encoder.h" 37 #include "i2caux_interface.h" 38 #include "dc_bios_types.h" 39 40 #include "gpio_service_interface.h" 41 42 #define CTX \ 43 enc10->base.ctx 44 #define DC_LOGGER \ 45 enc10->base.ctx->logger 46 47 #define REG(reg)\ 48 (enc10->link_regs->reg) 49 50 #undef FN 51 #define FN(reg_name, field_name) \ 52 enc10->link_shift->field_name, enc10->link_mask->field_name 53 54 #define IND_REG(index) \ 55 (enc10->link_regs->index) 56 57 58 static struct mpll_cfg dcn2_mpll_cfg[] = { 59 // RBR 60 { 61 .hdmimode_enable = 1, 62 .ref_range = 3, 63 .ref_clk_mpllb_div = 2, 64 .mpllb_ssc_en = 1, 65 .mpllb_div5_clk_en = 1, 66 .mpllb_multiplier = 226, 67 .mpllb_fracn_en = 1, 68 .mpllb_fracn_quot = 39321, 69 .mpllb_fracn_rem = 3, 70 .mpllb_fracn_den = 5, 71 .mpllb_ssc_up_spread = 0, 72 .mpllb_ssc_peak = 38221, 73 .mpllb_ssc_stepsize = 49314, 74 .mpllb_div_clk_en = 0, 75 .mpllb_div_multiplier = 0, 76 .mpllb_hdmi_div = 0, 77 .mpllb_tx_clk_div = 2, 78 .tx_vboost_lvl = 4, 79 .mpllb_pmix_en = 1, 80 .mpllb_word_div2_en = 0, 81 .mpllb_ana_v2i = 2, 82 .mpllb_ana_freq_vco = 2, 83 .mpllb_ana_cp_int = 7, 84 .mpllb_ana_cp_prop = 18, 85 .hdmi_pixel_clk_div = 0, 86 }, 87 // HBR 88 { 89 .hdmimode_enable = 1, 90 .ref_range = 3, 91 .ref_clk_mpllb_div = 2, 92 .mpllb_ssc_en = 1, 93 .mpllb_div5_clk_en = 1, 94 .mpllb_multiplier = 184, 95 .mpllb_fracn_en = 0, 96 .mpllb_fracn_quot = 0, 97 .mpllb_fracn_rem = 0, 98 .mpllb_fracn_den = 1, 99 .mpllb_ssc_up_spread = 0, 100 .mpllb_ssc_peak = 31850, 101 .mpllb_ssc_stepsize = 41095, 102 .mpllb_div_clk_en = 0, 103 .mpllb_div_multiplier = 0, 104 .mpllb_hdmi_div = 0, 105 .mpllb_tx_clk_div = 1, 106 .tx_vboost_lvl = 4, 107 .mpllb_pmix_en = 1, 108 .mpllb_word_div2_en = 0, 109 .mpllb_ana_v2i = 2, 110 .mpllb_ana_freq_vco = 3, 111 .mpllb_ana_cp_int = 7, 112 .mpllb_ana_cp_prop = 18, 113 .hdmi_pixel_clk_div = 0, 114 }, 115 //HBR2 116 { 117 .hdmimode_enable = 1, 118 .ref_range = 3, 119 .ref_clk_mpllb_div = 2, 120 .mpllb_ssc_en = 1, 121 .mpllb_div5_clk_en = 1, 122 .mpllb_multiplier = 184, 123 .mpllb_fracn_en = 0, 124 .mpllb_fracn_quot = 0, 125 .mpllb_fracn_rem = 0, 126 .mpllb_fracn_den = 1, 127 .mpllb_ssc_up_spread = 0, 128 .mpllb_ssc_peak = 31850, 129 .mpllb_ssc_stepsize = 41095, 130 .mpllb_div_clk_en = 0, 131 .mpllb_div_multiplier = 0, 132 .mpllb_hdmi_div = 0, 133 .mpllb_tx_clk_div = 0, 134 .tx_vboost_lvl = 4, 135 .mpllb_pmix_en = 1, 136 .mpllb_word_div2_en = 0, 137 .mpllb_ana_v2i = 2, 138 .mpllb_ana_freq_vco = 3, 139 .mpllb_ana_cp_int = 7, 140 .mpllb_ana_cp_prop = 18, 141 .hdmi_pixel_clk_div = 0, 142 }, 143 //HBR3 144 { 145 .hdmimode_enable = 1, 146 .ref_range = 3, 147 .ref_clk_mpllb_div = 2, 148 .mpllb_ssc_en = 1, 149 .mpllb_div5_clk_en = 1, 150 .mpllb_multiplier = 292, 151 .mpllb_fracn_en = 0, 152 .mpllb_fracn_quot = 0, 153 .mpllb_fracn_rem = 0, 154 .mpllb_fracn_den = 1, 155 .mpllb_ssc_up_spread = 0, 156 .mpllb_ssc_peak = 47776, 157 .mpllb_ssc_stepsize = 61642, 158 .mpllb_div_clk_en = 0, 159 .mpllb_div_multiplier = 0, 160 .mpllb_hdmi_div = 0, 161 .mpllb_tx_clk_div = 0, 162 .tx_vboost_lvl = 4, 163 .mpllb_pmix_en = 1, 164 .mpllb_word_div2_en = 0, 165 .mpllb_ana_v2i = 2, 166 .mpllb_ana_freq_vco = 0, 167 .mpllb_ana_cp_int = 7, 168 .mpllb_ana_cp_prop = 18, 169 .hdmi_pixel_clk_div = 0, 170 }, 171 }; 172 173 void enc2_fec_set_enable(struct link_encoder *enc, bool enable) 174 { 175 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 176 DC_LOG_DSC("%s FEC at link encoder inst %d", 177 enable ? "Enabling" : "Disabling", enc->id.enum_id); 178 REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable); 179 } 180 181 void enc2_fec_set_ready(struct link_encoder *enc, bool ready) 182 { 183 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 184 185 REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, ready); 186 } 187 188 bool enc2_fec_is_active(struct link_encoder *enc) 189 { 190 uint32_t active = 0; 191 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 192 193 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &active); 194 195 return (active != 0); 196 } 197 198 /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state 199 * into a dcn_dsc_state struct. 200 */ 201 void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) 202 { 203 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 204 205 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); 206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); 207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); 208 REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); 209 } 210 211 static bool update_cfg_data( 212 struct dcn10_link_encoder *enc10, 213 const struct dc_link_settings *link_settings, 214 struct dpcssys_phy_seq_cfg *cfg) 215 { 216 int i; 217 218 cfg->load_sram_fw = false; 219 220 for (i = 0; i < link_settings->lane_count; i++) 221 cfg->lane_en[i] = true; 222 223 switch (link_settings->link_rate) { 224 case LINK_RATE_LOW: 225 cfg->mpll_cfg = dcn2_mpll_cfg[0]; 226 break; 227 case LINK_RATE_HIGH: 228 cfg->mpll_cfg = dcn2_mpll_cfg[1]; 229 break; 230 case LINK_RATE_HIGH2: 231 cfg->mpll_cfg = dcn2_mpll_cfg[2]; 232 break; 233 case LINK_RATE_HIGH3: 234 cfg->mpll_cfg = dcn2_mpll_cfg[3]; 235 break; 236 default: 237 DC_LOG_ERROR("%s: No supported link rate found %X!\n", 238 __func__, link_settings->link_rate); 239 return false; 240 } 241 242 return true; 243 } 244 245 void dcn20_link_encoder_enable_dp_output( 246 struct link_encoder *enc, 247 const struct dc_link_settings *link_settings, 248 enum clock_source_id clock_source) 249 { 250 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 251 struct dcn20_link_encoder *enc20 = (struct dcn20_link_encoder *) enc10; 252 struct dpcssys_phy_seq_cfg *cfg = &enc20->phy_seq_cfg; 253 254 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 255 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); 256 return; 257 } 258 259 if (!update_cfg_data(enc10, link_settings, cfg)) 260 return; 261 262 enc1_configure_encoder(enc10, link_settings); 263 264 dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT); 265 266 } 267 268 #define AUX_REG(reg)\ 269 (enc10->aux_regs->reg) 270 271 #define AUX_REG_READ(reg_name) \ 272 dm_read_reg(CTX, AUX_REG(reg_name)) 273 274 #define AUX_REG_WRITE(reg_name, val) \ 275 dm_write_reg(CTX, AUX_REG(reg_name), val) 276 void enc2_hw_init(struct link_encoder *enc) 277 { 278 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 279 280 /* 281 00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2 282 01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4 283 02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8 284 03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16 285 04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32 286 05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64 287 06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128 288 07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256 289 */ 290 291 /* 292 AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0, 293 AUX_RX_START_WINDOW = 1 [6:4] 294 AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8] 295 AUX_RX_HALF_SYM_DETECT_LEN = 1 [13:12] default is 1 296 AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1 297 AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0 default is 0 298 AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1 default is 1 299 AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1 default is 1 300 AUX_RX_PHASE_DETECT_LEN, [21,20] = 0x3 default is 3 301 AUX_RX_DETECTION_THRESHOLD [30:28] = 1 302 */ 303 AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110); 304 305 AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a); 306 307 //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32; 308 // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk 309 // 27MHz -> 0xd 310 // 100MHz -> 0x32 311 // 48MHz -> 0x18 312 313 // Set TMDS_CTL0 to 1. This is a legacy setting. 314 REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1); 315 316 dcn10_aux_initialize(enc10); 317 } 318 319 static const struct link_encoder_funcs dcn20_link_enc_funcs = { 320 .read_state = link_enc2_read_state, 321 .validate_output_with_stream = 322 dcn10_link_encoder_validate_output_with_stream, 323 .hw_init = enc2_hw_init, 324 .setup = dcn10_link_encoder_setup, 325 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, 326 .enable_dp_output = dcn20_link_encoder_enable_dp_output, 327 .enable_dp_mst_output = dcn10_link_encoder_enable_dp_mst_output, 328 .disable_output = dcn10_link_encoder_disable_output, 329 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, 330 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, 331 .update_mst_stream_allocation_table = 332 dcn10_link_encoder_update_mst_stream_allocation_table, 333 .psr_program_dp_dphy_fast_training = 334 dcn10_psr_program_dp_dphy_fast_training, 335 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, 336 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, 337 .enable_hpd = dcn10_link_encoder_enable_hpd, 338 .disable_hpd = dcn10_link_encoder_disable_hpd, 339 .is_dig_enabled = dcn10_is_dig_enabled, 340 .destroy = dcn10_link_encoder_destroy, 341 .fec_set_enable = enc2_fec_set_enable, 342 .fec_set_ready = enc2_fec_set_ready, 343 .fec_is_active = enc2_fec_is_active, 344 .get_dig_mode = dcn10_get_dig_mode, 345 .get_dig_frontend = dcn10_get_dig_frontend, 346 }; 347 348 void dcn20_link_encoder_construct( 349 struct dcn20_link_encoder *enc20, 350 const struct encoder_init_data *init_data, 351 const struct encoder_feature_support *enc_features, 352 const struct dcn10_link_enc_registers *link_regs, 353 const struct dcn10_link_enc_aux_registers *aux_regs, 354 const struct dcn10_link_enc_hpd_registers *hpd_regs, 355 const struct dcn10_link_enc_shift *link_shift, 356 const struct dcn10_link_enc_mask *link_mask) 357 { 358 struct bp_encoder_cap_info bp_cap_info = {0}; 359 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 360 enum bp_result result = BP_RESULT_OK; 361 struct dcn10_link_encoder *enc10 = &enc20->enc10; 362 363 enc10->base.funcs = &dcn20_link_enc_funcs; 364 enc10->base.ctx = init_data->ctx; 365 enc10->base.id = init_data->encoder; 366 367 enc10->base.hpd_source = init_data->hpd_source; 368 enc10->base.connector = init_data->connector; 369 370 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 371 372 enc10->base.features = *enc_features; 373 374 enc10->base.transmitter = init_data->transmitter; 375 376 /* set the flag to indicate whether driver poll the I2C data pin 377 * while doing the DP sink detect 378 */ 379 380 /* if (dal_adapter_service_is_feature_supported(as, 381 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 382 enc10->base.features.flags.bits. 383 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 384 385 enc10->base.output_signals = 386 SIGNAL_TYPE_DVI_SINGLE_LINK | 387 SIGNAL_TYPE_DVI_DUAL_LINK | 388 SIGNAL_TYPE_LVDS | 389 SIGNAL_TYPE_DISPLAY_PORT | 390 SIGNAL_TYPE_DISPLAY_PORT_MST | 391 SIGNAL_TYPE_EDP | 392 SIGNAL_TYPE_HDMI_TYPE_A; 393 394 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 395 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 396 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 397 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 398 * Prefer DIG assignment is decided by board design. 399 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 400 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 401 * By this, adding DIGG should not hurt DCE 8.0. 402 * This will let DCE 8.1 share DCE 8.0 as much as possible 403 */ 404 405 enc10->link_regs = link_regs; 406 enc10->aux_regs = aux_regs; 407 enc10->hpd_regs = hpd_regs; 408 enc10->link_shift = link_shift; 409 enc10->link_mask = link_mask; 410 411 switch (enc10->base.transmitter) { 412 case TRANSMITTER_UNIPHY_A: 413 enc10->base.preferred_engine = ENGINE_ID_DIGA; 414 break; 415 case TRANSMITTER_UNIPHY_B: 416 enc10->base.preferred_engine = ENGINE_ID_DIGB; 417 break; 418 case TRANSMITTER_UNIPHY_C: 419 enc10->base.preferred_engine = ENGINE_ID_DIGC; 420 break; 421 case TRANSMITTER_UNIPHY_D: 422 enc10->base.preferred_engine = ENGINE_ID_DIGD; 423 break; 424 case TRANSMITTER_UNIPHY_E: 425 enc10->base.preferred_engine = ENGINE_ID_DIGE; 426 break; 427 case TRANSMITTER_UNIPHY_F: 428 enc10->base.preferred_engine = ENGINE_ID_DIGF; 429 break; 430 case TRANSMITTER_UNIPHY_G: 431 enc10->base.preferred_engine = ENGINE_ID_DIGG; 432 break; 433 default: 434 ASSERT_CRITICAL(false); 435 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 436 } 437 438 /* default to one to mirror Windows behavior */ 439 enc10->base.features.flags.bits.HDMI_6GB_EN = 1; 440 441 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, 442 enc10->base.id, &bp_cap_info); 443 444 /* Override features with DCE-specific values */ 445 if (result == BP_RESULT_OK) { 446 enc10->base.features.flags.bits.IS_HBR2_CAPABLE = 447 bp_cap_info.DP_HBR2_EN; 448 enc10->base.features.flags.bits.IS_HBR3_CAPABLE = 449 bp_cap_info.DP_HBR3_EN; 450 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 451 enc10->base.features.flags.bits.DP_IS_USB_C = 452 bp_cap_info.DP_IS_USB_C; 453 } else { 454 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 455 __func__, 456 result); 457 } 458 if (enc10->base.ctx->dc->debug.hdmi20_disable) { 459 enc10->base.features.flags.bits.HDMI_6GB_EN = 0; 460 } 461 } 462
Indexes created Sat Sep 20 22:09:52 GMT 2025