1 /* $NetBSD: amdgpu_dcn21_init.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn21_init.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $"); 30 31 #include "dce110/dce110_hw_sequencer.h" 32 #include "dcn10/dcn10_hw_sequencer.h" 33 #include "dcn20/dcn20_hwseq.h" 34 #include "dcn21_hwseq.h" 35 36 static const struct hw_sequencer_funcs dcn21_funcs = { 37 .program_gamut_remap = dcn10_program_gamut_remap, 38 .init_hw = dcn10_init_hw, 39 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 40 .apply_ctx_for_surface = NULL, 41 .program_front_end_for_ctx = dcn20_program_front_end_for_ctx, 42 .update_plane_addr = dcn20_update_plane_addr, 43 .update_dchub = dcn10_update_dchub, 44 .update_pending_status = dcn10_update_pending_status, 45 .program_output_csc = dcn20_program_output_csc, 46 .enable_accelerated_mode = dce110_enable_accelerated_mode, 47 .enable_timing_synchronization = dcn10_enable_timing_synchronization, 48 .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset, 49 .update_info_frame = dce110_update_info_frame, 50 .send_immediate_sdp_message = dcn10_send_immediate_sdp_message, 51 .enable_stream = dcn20_enable_stream, 52 .disable_stream = dce110_disable_stream, 53 .unblank_stream = dcn20_unblank_stream, 54 .blank_stream = dce110_blank_stream, 55 .enable_audio_stream = dce110_enable_audio_stream, 56 .disable_audio_stream = dce110_disable_audio_stream, 57 .disable_plane = dcn20_disable_plane, 58 .pipe_control_lock = dcn20_pipe_control_lock, 59 .pipe_control_lock_global = dcn20_pipe_control_lock_global, 60 .prepare_bandwidth = dcn20_prepare_bandwidth, 61 .optimize_bandwidth = dcn20_optimize_bandwidth, 62 .update_bandwidth = dcn20_update_bandwidth, 63 .set_drr = dcn10_set_drr, 64 .get_position = dcn10_get_position, 65 .set_static_screen_control = dcn10_set_static_screen_control, 66 .setup_stereo = dcn10_setup_stereo, 67 .set_avmute = dce110_set_avmute, 68 .log_hw_state = dcn10_log_hw_state, 69 .get_hw_state = dcn10_get_hw_state, 70 .clear_status_bits = dcn10_clear_status_bits, 71 .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect, 72 .edp_power_control = dce110_edp_power_control, 73 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 74 .set_cursor_position = dcn10_set_cursor_position, 75 .set_cursor_attribute = dcn10_set_cursor_attribute, 76 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, 77 .setup_periodic_interrupt = dcn10_setup_periodic_interrupt, 78 .set_clock = dcn10_set_clock, 79 .get_clock = dcn10_get_clock, 80 .program_triplebuffer = dcn20_program_triple_buffer, 81 .enable_writeback = dcn20_enable_writeback, 82 .disable_writeback = dcn20_disable_writeback, 83 .dmdata_status_done = dcn20_dmdata_status_done, 84 .program_dmdata_engine = dcn20_program_dmdata_engine, 85 .set_dmdata_attributes = dcn20_set_dmdata_attributes, 86 .init_sys_ctx = dcn21_init_sys_ctx, 87 .init_vm_ctx = dcn20_init_vm_ctx, 88 .set_flip_control_gsl = dcn20_set_flip_control_gsl, 89 .optimize_pwr_state = dcn21_optimize_pwr_state, 90 .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, 91 .get_vupdate_offset_from_vsync = dcn10_get_vupdate_offset_from_vsync, 92 .set_cursor_position = dcn10_set_cursor_position, 93 .set_cursor_attribute = dcn10_set_cursor_attribute, 94 .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level, 95 .optimize_pwr_state = dcn21_optimize_pwr_state, 96 .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, 97 }; 98 99 static const struct hwseq_private_funcs dcn21_private_funcs = { 100 .init_pipes = dcn10_init_pipes, 101 .update_plane_addr = dcn20_update_plane_addr, 102 .plane_atomic_disconnect = dcn10_plane_atomic_disconnect, 103 .update_mpcc = dcn20_update_mpcc, 104 .set_input_transfer_func = dcn20_set_input_transfer_func, 105 .set_output_transfer_func = dcn20_set_output_transfer_func, 106 .power_down = dce110_power_down, 107 .enable_display_power_gating = dcn10_dummy_display_power_gating, 108 .blank_pixel_data = dcn20_blank_pixel_data, 109 .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap, 110 .enable_stream_timing = dcn20_enable_stream_timing, 111 .edp_backlight_control = dce110_edp_backlight_control, 112 .disable_stream_gating = dcn20_disable_stream_gating, 113 .enable_stream_gating = dcn20_enable_stream_gating, 114 .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, 115 .did_underflow_occur = dcn10_did_underflow_occur, 116 .init_blank = dcn20_init_blank, 117 .disable_vga = dcn20_disable_vga, 118 .bios_golden_init = dcn10_bios_golden_init, 119 .plane_atomic_disable = dcn20_plane_atomic_disable, 120 .plane_atomic_power_down = dcn10_plane_atomic_power_down, 121 .enable_power_gating_plane = dcn20_enable_power_gating_plane, 122 .dpp_pg_control = dcn20_dpp_pg_control, 123 .hubp_pg_control = dcn20_hubp_pg_control, 124 .dsc_pg_control = NULL, 125 .update_odm = dcn20_update_odm, 126 .dsc_pg_control = dcn20_dsc_pg_control, 127 .get_surface_visual_confirm_color = dcn10_get_surface_visual_confirm_color, 128 .get_hdr_visual_confirm_color = dcn10_get_hdr_visual_confirm_color, 129 .set_hdr_multiplier = dcn10_set_hdr_multiplier, 130 .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, 131 .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa, 132 .wait_for_blank_complete = dcn20_wait_for_blank_complete, 133 .dccg_init = dcn20_dccg_init, 134 .set_blend_lut = dcn20_set_blend_lut, 135 .set_shaper_3dlut = dcn20_set_shaper_3dlut, 136 }; 137 138 void dcn21_hw_sequencer_construct(struct dc *dc) 139 { 140 dc->hwss = dcn21_funcs; 141 dc->hwseq->funcs = dcn21_private_funcs; 142 143 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) { 144 dc->hwss.init_hw = dcn20_fpga_init_hw; 145 dc->hwseq->funcs.init_pipes = NULL; 146 } 147 } 148
Indexes created Tue Sep 23 02:09:52 GMT 2025