1 /* $NetBSD: amdgpu_dcn21_link_encoder.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn21_link_encoder.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $"); 30 31 #include "reg_helper.h" 32 33 #include <linux/delay.h> 34 #include "core_types.h" 35 #include "link_encoder.h" 36 #include "dcn21_link_encoder.h" 37 #include "stream_encoder.h" 38 39 #include "i2caux_interface.h" 40 #include "dc_bios_types.h" 41 42 #include "gpio_service_interface.h" 43 44 #define CTX \ 45 enc10->base.ctx 46 #define DC_LOGGER \ 47 enc10->base.ctx->logger 48 49 #define REG(reg)\ 50 (enc10->link_regs->reg) 51 52 #undef FN 53 #define FN(reg_name, field_name) \ 54 enc10->link_shift->field_name, enc10->link_mask->field_name 55 56 #define IND_REG(index) \ 57 (enc10->link_regs->index) 58 59 static struct mpll_cfg dcn21_mpll_cfg_ref[] = { 60 // RBR 61 { 62 .hdmimode_enable = 0, 63 .ref_range = 1, 64 .ref_clk_mpllb_div = 1, 65 .mpllb_ssc_en = 1, 66 .mpllb_div5_clk_en = 1, 67 .mpllb_multiplier = 238, 68 .mpllb_fracn_en = 0, 69 .mpllb_fracn_quot = 0, 70 .mpllb_fracn_rem = 0, 71 .mpllb_fracn_den = 1, 72 .mpllb_ssc_up_spread = 0, 73 .mpllb_ssc_peak = 44237, 74 .mpllb_ssc_stepsize = 59454, 75 .mpllb_div_clk_en = 0, 76 .mpllb_div_multiplier = 0, 77 .mpllb_hdmi_div = 0, 78 .mpllb_tx_clk_div = 2, 79 .tx_vboost_lvl = 5, 80 .mpllb_pmix_en = 1, 81 .mpllb_word_div2_en = 0, 82 .mpllb_ana_v2i = 2, 83 .mpllb_ana_freq_vco = 2, 84 .mpllb_ana_cp_int = 9, 85 .mpllb_ana_cp_prop = 15, 86 .hdmi_pixel_clk_div = 0, 87 }, 88 // HBR 89 { 90 .hdmimode_enable = 0, 91 .ref_range = 1, 92 .ref_clk_mpllb_div = 1, 93 .mpllb_ssc_en = 1, 94 .mpllb_div5_clk_en = 1, 95 .mpllb_multiplier = 192, 96 .mpllb_fracn_en = 1, 97 .mpllb_fracn_quot = 32768, 98 .mpllb_fracn_rem = 0, 99 .mpllb_fracn_den = 1, 100 .mpllb_ssc_up_spread = 0, 101 .mpllb_ssc_peak = 36864, 102 .mpllb_ssc_stepsize = 49545, 103 .mpllb_div_clk_en = 0, 104 .mpllb_div_multiplier = 0, 105 .mpllb_hdmi_div = 0, 106 .mpllb_tx_clk_div = 1, 107 .tx_vboost_lvl = 5, 108 .mpllb_pmix_en = 1, 109 .mpllb_word_div2_en = 0, 110 .mpllb_ana_v2i = 2, 111 .mpllb_ana_freq_vco = 3, 112 .mpllb_ana_cp_int = 9, 113 .mpllb_ana_cp_prop = 15, 114 .hdmi_pixel_clk_div = 0, 115 }, 116 //HBR2 117 { 118 .hdmimode_enable = 0, 119 .ref_range = 1, 120 .ref_clk_mpllb_div = 1, 121 .mpllb_ssc_en = 1, 122 .mpllb_div5_clk_en = 1, 123 .mpllb_multiplier = 192, 124 .mpllb_fracn_en = 1, 125 .mpllb_fracn_quot = 32768, 126 .mpllb_fracn_rem = 0, 127 .mpllb_fracn_den = 1, 128 .mpllb_ssc_up_spread = 0, 129 .mpllb_ssc_peak = 36864, 130 .mpllb_ssc_stepsize = 49545, 131 .mpllb_div_clk_en = 0, 132 .mpllb_div_multiplier = 0, 133 .mpllb_hdmi_div = 0, 134 .mpllb_tx_clk_div = 0, 135 .tx_vboost_lvl = 5, 136 .mpllb_pmix_en = 1, 137 .mpllb_word_div2_en = 0, 138 .mpllb_ana_v2i = 2, 139 .mpllb_ana_freq_vco = 3, 140 .mpllb_ana_cp_int = 9, 141 .mpllb_ana_cp_prop = 15, 142 .hdmi_pixel_clk_div = 0, 143 }, 144 //HBR3 145 { 146 .hdmimode_enable = 0, 147 .ref_range = 1, 148 .ref_clk_mpllb_div = 1, 149 .mpllb_ssc_en = 1, 150 .mpllb_div5_clk_en = 1, 151 .mpllb_multiplier = 304, 152 .mpllb_fracn_en = 1, 153 .mpllb_fracn_quot = 49152, 154 .mpllb_fracn_rem = 0, 155 .mpllb_fracn_den = 1, 156 .mpllb_ssc_up_spread = 0, 157 .mpllb_ssc_peak = 55296, 158 .mpllb_ssc_stepsize = 74318, 159 .mpllb_div_clk_en = 0, 160 .mpllb_div_multiplier = 0, 161 .mpllb_hdmi_div = 0, 162 .mpllb_tx_clk_div = 0, 163 .tx_vboost_lvl = 5, 164 .mpllb_pmix_en = 1, 165 .mpllb_word_div2_en = 0, 166 .mpllb_ana_v2i = 2, 167 .mpllb_ana_freq_vco = 1, 168 .mpllb_ana_cp_int = 7, 169 .mpllb_ana_cp_prop = 16, 170 .hdmi_pixel_clk_div = 0, 171 }, 172 }; 173 174 175 static bool update_cfg_data( 176 struct dcn10_link_encoder *enc10, 177 const struct dc_link_settings *link_settings, 178 struct dpcssys_phy_seq_cfg *cfg) 179 { 180 int i; 181 182 cfg->load_sram_fw = false; 183 cfg->use_calibration_setting = true; 184 185 //TODO: need to implement a proper lane mapping for Renoir. 186 for (i = 0; i < 4; i++) 187 cfg->lane_en[i] = true; 188 189 switch (link_settings->link_rate) { 190 case LINK_RATE_LOW: 191 cfg->mpll_cfg = dcn21_mpll_cfg_ref[0]; 192 break; 193 case LINK_RATE_HIGH: 194 cfg->mpll_cfg = dcn21_mpll_cfg_ref[1]; 195 break; 196 case LINK_RATE_HIGH2: 197 cfg->mpll_cfg = dcn21_mpll_cfg_ref[2]; 198 break; 199 case LINK_RATE_HIGH3: 200 cfg->mpll_cfg = dcn21_mpll_cfg_ref[3]; 201 break; 202 default: 203 DC_LOG_ERROR("%s: No supported link rate found %X!\n", 204 __func__, link_settings->link_rate); 205 return false; 206 } 207 208 return true; 209 } 210 211 void dcn21_link_encoder_get_max_link_cap(struct link_encoder *enc, 212 struct dc_link_settings *link_settings) 213 { 214 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 215 uint32_t value; 216 217 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &value); 218 219 if (!value && link_settings->lane_count > LANE_COUNT_TWO) 220 link_settings->lane_count = LANE_COUNT_TWO; 221 } 222 223 bool dcn21_link_encoder_is_in_alt_mode(struct link_encoder *enc) 224 { 225 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 226 uint32_t value; 227 228 REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &value); 229 230 // if value == 1 alt mode is disabled, otherwise it is enabled 231 return !value; 232 } 233 234 bool dcn21_link_encoder_acquire_phy(struct link_encoder *enc) 235 { 236 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 237 int value; 238 239 if (enc->features.flags.bits.DP_IS_USB_C) { 240 REG_GET(RDPCSTX_PHY_CNTL6, 241 RDPCS_PHY_DPALT_DISABLE, &value); 242 243 if (value == 1) { 244 ASSERT(0); 245 return false; 246 } 247 REG_UPDATE(RDPCSTX_PHY_CNTL6, 248 RDPCS_PHY_DPALT_DISABLE_ACK, 0); 249 250 udelay(40); 251 252 REG_GET(RDPCSTX_PHY_CNTL6, 253 RDPCS_PHY_DPALT_DISABLE, &value); 254 if (value == 1) { 255 ASSERT(0); 256 REG_UPDATE(RDPCSTX_PHY_CNTL6, 257 RDPCS_PHY_DPALT_DISABLE_ACK, 1); 258 return false; 259 } 260 } 261 262 REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 1); 263 264 return true; 265 } 266 267 268 269 static void dcn21_link_encoder_release_phy(struct link_encoder *enc) 270 { 271 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 272 273 if (enc->features.flags.bits.DP_IS_USB_C) { 274 REG_UPDATE(RDPCSTX_PHY_CNTL6, 275 RDPCS_PHY_DPALT_DISABLE_ACK, 1); 276 } 277 278 REG_UPDATE(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DP_REF_CLK_EN, 0); 279 280 } 281 282 void dcn21_link_encoder_enable_dp_output( 283 struct link_encoder *enc, 284 const struct dc_link_settings *link_settings, 285 enum clock_source_id clock_source) 286 { 287 struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); 288 struct dcn21_link_encoder *enc21 = (struct dcn21_link_encoder *) enc10; 289 struct dpcssys_phy_seq_cfg *cfg = &enc21->phy_seq_cfg; 290 291 if (!dcn21_link_encoder_acquire_phy(enc)) 292 return; 293 294 if (!enc->ctx->dc->debug.avoid_vbios_exec_table) { 295 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); 296 return; 297 } 298 299 if (!update_cfg_data(enc10, link_settings, cfg)) 300 return; 301 302 enc1_configure_encoder(enc10, link_settings); 303 304 dcn10_link_encoder_setup(enc, SIGNAL_TYPE_DISPLAY_PORT); 305 306 } 307 308 void dcn21_link_encoder_enable_dp_mst_output( 309 struct link_encoder *enc, 310 const struct dc_link_settings *link_settings, 311 enum clock_source_id clock_source) 312 { 313 if (!dcn21_link_encoder_acquire_phy(enc)) 314 return; 315 316 dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source); 317 } 318 319 void dcn21_link_encoder_disable_output( 320 struct link_encoder *enc, 321 enum signal_type signal) 322 { 323 dcn10_link_encoder_disable_output(enc, signal); 324 325 if (dc_is_dp_signal(signal)) 326 dcn21_link_encoder_release_phy(enc); 327 } 328 329 330 static const struct link_encoder_funcs dcn21_link_enc_funcs = { 331 .read_state = link_enc2_read_state, 332 .validate_output_with_stream = 333 dcn10_link_encoder_validate_output_with_stream, 334 .hw_init = enc2_hw_init, 335 .setup = dcn10_link_encoder_setup, 336 .enable_tmds_output = dcn10_link_encoder_enable_tmds_output, 337 .enable_dp_output = dcn21_link_encoder_enable_dp_output, 338 .enable_dp_mst_output = dcn21_link_encoder_enable_dp_mst_output, 339 .disable_output = dcn21_link_encoder_disable_output, 340 .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings, 341 .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern, 342 .update_mst_stream_allocation_table = 343 dcn10_link_encoder_update_mst_stream_allocation_table, 344 .psr_program_dp_dphy_fast_training = 345 dcn10_psr_program_dp_dphy_fast_training, 346 .psr_program_secondary_packet = dcn10_psr_program_secondary_packet, 347 .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe, 348 .enable_hpd = dcn10_link_encoder_enable_hpd, 349 .disable_hpd = dcn10_link_encoder_disable_hpd, 350 .is_dig_enabled = dcn10_is_dig_enabled, 351 .destroy = dcn10_link_encoder_destroy, 352 .fec_set_enable = enc2_fec_set_enable, 353 .fec_set_ready = enc2_fec_set_ready, 354 .fec_is_active = enc2_fec_is_active, 355 .get_dig_frontend = dcn10_get_dig_frontend, 356 .is_in_alt_mode = dcn21_link_encoder_is_in_alt_mode, 357 .get_max_link_cap = dcn21_link_encoder_get_max_link_cap, 358 }; 359 360 void dcn21_link_encoder_construct( 361 struct dcn21_link_encoder *enc21, 362 const struct encoder_init_data *init_data, 363 const struct encoder_feature_support *enc_features, 364 const struct dcn10_link_enc_registers *link_regs, 365 const struct dcn10_link_enc_aux_registers *aux_regs, 366 const struct dcn10_link_enc_hpd_registers *hpd_regs, 367 const struct dcn10_link_enc_shift *link_shift, 368 const struct dcn10_link_enc_mask *link_mask) 369 { 370 struct bp_encoder_cap_info bp_cap_info = {0}; 371 const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs; 372 enum bp_result result = BP_RESULT_OK; 373 struct dcn10_link_encoder *enc10 = &enc21->enc10; 374 375 enc10->base.funcs = &dcn21_link_enc_funcs; 376 enc10->base.ctx = init_data->ctx; 377 enc10->base.id = init_data->encoder; 378 379 enc10->base.hpd_source = init_data->hpd_source; 380 enc10->base.connector = init_data->connector; 381 382 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 383 384 enc10->base.features = *enc_features; 385 386 enc10->base.transmitter = init_data->transmitter; 387 388 /* set the flag to indicate whether driver poll the I2C data pin 389 * while doing the DP sink detect 390 */ 391 392 /* if (dal_adapter_service_is_feature_supported(as, 393 FEATURE_DP_SINK_DETECT_POLL_DATA_PIN)) 394 enc10->base.features.flags.bits. 395 DP_SINK_DETECT_POLL_DATA_PIN = true;*/ 396 397 enc10->base.output_signals = 398 SIGNAL_TYPE_DVI_SINGLE_LINK | 399 SIGNAL_TYPE_DVI_DUAL_LINK | 400 SIGNAL_TYPE_LVDS | 401 SIGNAL_TYPE_DISPLAY_PORT | 402 SIGNAL_TYPE_DISPLAY_PORT_MST | 403 SIGNAL_TYPE_EDP | 404 SIGNAL_TYPE_HDMI_TYPE_A; 405 406 /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE. 407 * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY. 408 * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer 409 * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS. 410 * Prefer DIG assignment is decided by board design. 411 * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design 412 * and VBIOS will filter out 7 UNIPHY for DCE 8.0. 413 * By this, adding DIGG should not hurt DCE 8.0. 414 * This will let DCE 8.1 share DCE 8.0 as much as possible 415 */ 416 417 enc10->link_regs = link_regs; 418 enc10->aux_regs = aux_regs; 419 enc10->hpd_regs = hpd_regs; 420 enc10->link_shift = link_shift; 421 enc10->link_mask = link_mask; 422 423 switch (enc10->base.transmitter) { 424 case TRANSMITTER_UNIPHY_A: 425 enc10->base.preferred_engine = ENGINE_ID_DIGA; 426 break; 427 case TRANSMITTER_UNIPHY_B: 428 enc10->base.preferred_engine = ENGINE_ID_DIGB; 429 break; 430 case TRANSMITTER_UNIPHY_C: 431 enc10->base.preferred_engine = ENGINE_ID_DIGC; 432 break; 433 case TRANSMITTER_UNIPHY_D: 434 enc10->base.preferred_engine = ENGINE_ID_DIGD; 435 break; 436 case TRANSMITTER_UNIPHY_E: 437 enc10->base.preferred_engine = ENGINE_ID_DIGE; 438 break; 439 case TRANSMITTER_UNIPHY_F: 440 enc10->base.preferred_engine = ENGINE_ID_DIGF; 441 break; 442 case TRANSMITTER_UNIPHY_G: 443 enc10->base.preferred_engine = ENGINE_ID_DIGG; 444 break; 445 default: 446 ASSERT_CRITICAL(false); 447 enc10->base.preferred_engine = ENGINE_ID_UNKNOWN; 448 } 449 450 /* default to one to mirror Windows behavior */ 451 enc10->base.features.flags.bits.HDMI_6GB_EN = 1; 452 453 result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios, 454 enc10->base.id, &bp_cap_info); 455 456 /* Override features with DCE-specific values */ 457 if (result == BP_RESULT_OK) { 458 enc10->base.features.flags.bits.IS_HBR2_CAPABLE = 459 bp_cap_info.DP_HBR2_EN; 460 enc10->base.features.flags.bits.IS_HBR3_CAPABLE = 461 bp_cap_info.DP_HBR3_EN; 462 enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN; 463 enc10->base.features.flags.bits.DP_IS_USB_C = 464 bp_cap_info.DP_IS_USB_C; 465 } else { 466 DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n", 467 __func__, 468 result); 469 } 470 if (enc10->base.ctx->dc->debug.hdmi20_disable) { 471 enc10->base.features.flags.bits.HDMI_6GB_EN = 0; 472 } 473 } 474
Indexes created Tue Sep 23 23:09:58 GMT 2025