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      1 /*	$NetBSD: amdgpu_dcn21_hwseq.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2016 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  * Authors: AMD
     25  *
     26  */
     27 
     28 #include <sys/cdefs.h>
     29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn21_hwseq.c,v 1.2 2021/12/18 23:45:03 riastradh Exp $");
     30 
     31 #include "dm_services.h"
     32 #include "dm_helpers.h"
     33 #include "core_types.h"
     34 #include "resource.h"
     35 #include "dce/dce_hwseq.h"
     36 #include "dcn21_hwseq.h"
     37 #include "vmid.h"
     38 #include "reg_helper.h"
     39 #include "hw/clk_mgr.h"
     40 
     41 
     42 #define DC_LOGGER_INIT(logger)
     43 
     44 #define CTX \
     45 	hws->ctx
     46 #define REG(reg)\
     47 	hws->regs->reg
     48 
     49 #undef FN
     50 #define FN(reg_name, field_name) \
     51 	hws->shifts->field_name, hws->masks->field_name
     52 
     53 /* Temporary read settings, future will get values from kmd directly */
     54 static void mmhub_update_page_table_config(struct dcn_hubbub_phys_addr_config *config,
     55 		struct dce_hwseq *hws)
     56 {
     57 	uint32_t page_table_base_hi;
     58 	uint32_t page_table_base_lo;
     59 
     60 	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
     61 			PAGE_DIRECTORY_ENTRY_HI32, &page_table_base_hi);
     62 	REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
     63 			PAGE_DIRECTORY_ENTRY_LO32, &page_table_base_lo);
     64 
     65 	config->gart_config.page_table_base_addr = ((uint64_t)page_table_base_hi << 32) | page_table_base_lo;
     66 
     67 }
     68 
     69 int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
     70 {
     71 	struct dcn_hubbub_phys_addr_config config;
     72 
     73 	config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
     74 	config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
     75 	config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
     76 	config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
     77 	config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
     78 	config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
     79 	config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
     80 	config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
     81 	config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
     82 
     83 	mmhub_update_page_table_config(&config, hws);
     84 
     85 	return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
     86 }
     87 
     88 // work around for Renoir s0i3, if register is programmed, bypass golden init.
     89 
     90 bool dcn21_s0i3_golden_init_wa(struct dc *dc)
     91 {
     92 	struct dce_hwseq *hws = dc->hwseq;
     93 	uint32_t value = 0;
     94 
     95 	value = REG_READ(MICROSECOND_TIME_BASE_DIV);
     96 
     97 	return value != 0x00120464;
     98 }
     99 
    100 void dcn21_exit_optimized_pwr_state(
    101 		const struct dc *dc,
    102 		struct dc_state *context)
    103 {
    104 	dc->clk_mgr->funcs->update_clocks(
    105 			dc->clk_mgr,
    106 			context,
    107 			false);
    108 }
    109 
    110 void dcn21_optimize_pwr_state(
    111 		const struct dc *dc,
    112 		struct dc_state *context)
    113 {
    114 	dc->clk_mgr->funcs->update_clocks(
    115 			dc->clk_mgr,
    116 			context,
    117 			true);
    118 }
    119 
    120