1 /* $NetBSD: dcn10_mpc.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* Copyright 2012-15 Advanced Micro Devices, Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: AMD 24 * 25 */ 26 27 #ifndef __DC_MPCC_DCN10_H__ 28 #define __DC_MPCC_DCN10_H__ 29 30 #include "mpc.h" 31 32 #define TO_DCN10_MPC(mpc_base) \ 33 container_of(mpc_base, struct dcn10_mpc, base) 34 35 #define MPC_COMMON_REG_LIST_DCN1_0(inst) \ 36 SRII(MPCC_TOP_SEL, MPCC, inst),\ 37 SRII(MPCC_BOT_SEL, MPCC, inst),\ 38 SRII(MPCC_CONTROL, MPCC, inst),\ 39 SRII(MPCC_STATUS, MPCC, inst),\ 40 SRII(MPCC_OPP_ID, MPCC, inst),\ 41 SRII(MPCC_BG_G_Y, MPCC, inst),\ 42 SRII(MPCC_BG_R_CR, MPCC, inst),\ 43 SRII(MPCC_BG_B_CB, MPCC, inst),\ 44 SRII(MPCC_BG_B_CB, MPCC, inst),\ 45 SRII(MPCC_SM_CONTROL, MPCC, inst) 46 47 #define MPC_OUT_MUX_COMMON_REG_LIST_DCN1_0(inst) \ 48 SRII(MUX, MPC_OUT, inst) 49 50 #define MPC_COMMON_REG_VARIABLE_LIST \ 51 uint32_t MPCC_TOP_SEL[MAX_MPCC]; \ 52 uint32_t MPCC_BOT_SEL[MAX_MPCC]; \ 53 uint32_t MPCC_CONTROL[MAX_MPCC]; \ 54 uint32_t MPCC_STATUS[MAX_MPCC]; \ 55 uint32_t MPCC_OPP_ID[MAX_MPCC]; \ 56 uint32_t MPCC_BG_G_Y[MAX_MPCC]; \ 57 uint32_t MPCC_BG_R_CR[MAX_MPCC]; \ 58 uint32_t MPCC_BG_B_CB[MAX_MPCC]; \ 59 uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \ 60 uint32_t MUX[MAX_OPP]; 61 62 #define MPC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 63 SF(MPCC0_MPCC_TOP_SEL, MPCC_TOP_SEL, mask_sh),\ 64 SF(MPCC0_MPCC_BOT_SEL, MPCC_BOT_SEL, mask_sh),\ 65 SF(MPCC0_MPCC_CONTROL, MPCC_MODE, mask_sh),\ 66 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_BLND_MODE, mask_sh),\ 67 SF(MPCC0_MPCC_CONTROL, MPCC_ALPHA_MULTIPLIED_MODE, mask_sh),\ 68 SF(MPCC0_MPCC_CONTROL, MPCC_BLND_ACTIVE_OVERLAP_ONLY, mask_sh),\ 69 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_ALPHA, mask_sh),\ 70 SF(MPCC0_MPCC_CONTROL, MPCC_GLOBAL_GAIN, mask_sh),\ 71 SF(MPCC0_MPCC_STATUS, MPCC_IDLE, mask_sh),\ 72 SF(MPCC0_MPCC_STATUS, MPCC_BUSY, mask_sh),\ 73 SF(MPCC0_MPCC_OPP_ID, MPCC_OPP_ID, mask_sh),\ 74 SF(MPCC0_MPCC_BG_G_Y, MPCC_BG_G_Y, mask_sh),\ 75 SF(MPCC0_MPCC_BG_R_CR, MPCC_BG_R_CR, mask_sh),\ 76 SF(MPCC0_MPCC_BG_B_CB, MPCC_BG_B_CB, mask_sh),\ 77 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_EN, mask_sh),\ 78 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_MODE, mask_sh),\ 79 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FRAME_ALT, mask_sh),\ 80 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FIELD_ALT, mask_sh),\ 81 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_FRAME_POL, mask_sh),\ 82 SF(MPCC0_MPCC_SM_CONTROL, MPCC_SM_FORCE_NEXT_TOP_POL, mask_sh),\ 83 SF(MPC_OUT0_MUX, MPC_OUT_MUX, mask_sh) 84 85 #define MPC_REG_FIELD_LIST(type) \ 86 type MPCC_TOP_SEL;\ 87 type MPCC_BOT_SEL;\ 88 type MPCC_MODE;\ 89 type MPCC_ALPHA_BLND_MODE;\ 90 type MPCC_ALPHA_MULTIPLIED_MODE;\ 91 type MPCC_BLND_ACTIVE_OVERLAP_ONLY;\ 92 type MPCC_GLOBAL_ALPHA;\ 93 type MPCC_GLOBAL_GAIN;\ 94 type MPCC_IDLE;\ 95 type MPCC_BUSY;\ 96 type MPCC_OPP_ID;\ 97 type MPCC_BG_G_Y;\ 98 type MPCC_BG_R_CR;\ 99 type MPCC_BG_B_CB;\ 100 type MPCC_SM_EN;\ 101 type MPCC_SM_MODE;\ 102 type MPCC_SM_FRAME_ALT;\ 103 type MPCC_SM_FIELD_ALT;\ 104 type MPCC_SM_FORCE_NEXT_FRAME_POL;\ 105 type MPCC_SM_FORCE_NEXT_TOP_POL;\ 106 type MPC_OUT_MUX; 107 108 struct dcn_mpc_registers { 109 MPC_COMMON_REG_VARIABLE_LIST 110 }; 111 112 struct dcn_mpc_shift { 113 MPC_REG_FIELD_LIST(uint8_t) 114 }; 115 116 struct dcn_mpc_mask { 117 MPC_REG_FIELD_LIST(uint32_t) 118 }; 119 120 struct dcn10_mpc { 121 struct mpc base; 122 123 int mpcc_in_use_mask; 124 int num_mpcc; 125 const struct dcn_mpc_registers *mpc_regs; 126 const struct dcn_mpc_shift *mpc_shift; 127 const struct dcn_mpc_mask *mpc_mask; 128 }; 129 130 void dcn10_mpc_construct(struct dcn10_mpc *mpcc10, 131 struct dc_context *ctx, 132 const struct dcn_mpc_registers *mpc_regs, 133 const struct dcn_mpc_shift *mpc_shift, 134 const struct dcn_mpc_mask *mpc_mask, 135 int num_mpcc); 136 137 struct mpcc *mpc1_insert_plane( 138 struct mpc *mpc, 139 struct mpc_tree *tree, 140 struct mpcc_blnd_cfg *blnd_cfg, 141 struct mpcc_sm_cfg *sm_cfg, 142 struct mpcc *insert_above_mpcc, 143 int dpp_id, 144 int mpcc_id); 145 146 void mpc1_remove_mpcc( 147 struct mpc *mpc, 148 struct mpc_tree *tree, 149 struct mpcc *mpcc); 150 151 void mpc1_mpc_init( 152 struct mpc *mpc); 153 154 void mpc1_mpc_init_single_inst( 155 struct mpc *mpc, 156 unsigned int mpcc_id); 157 158 void mpc1_assert_idle_mpcc( 159 struct mpc *mpc, 160 int id); 161 162 void mpc1_set_bg_color( 163 struct mpc *mpc, 164 struct tg_color *bg_color, 165 int id); 166 167 void mpc1_update_stereo_mix( 168 struct mpc *mpc, 169 struct mpcc_sm_cfg *sm_cfg, 170 int mpcc_id); 171 172 bool mpc1_is_mpcc_idle( 173 struct mpc *mpc, 174 int mpcc_id); 175 176 void mpc1_assert_mpcc_idle_before_connect( 177 struct mpc *mpc, 178 int mpcc_id); 179 180 void mpc1_init_mpcc_list_from_hw( 181 struct mpc *mpc, 182 struct mpc_tree *tree); 183 184 struct mpcc *mpc1_get_mpcc( 185 struct mpc *mpc, 186 int mpcc_id); 187 188 struct mpcc *mpc1_get_mpcc_for_dpp( 189 struct mpc_tree *tree, 190 int dpp_id); 191 192 void mpc1_read_mpcc_state( 193 struct mpc *mpc, 194 int mpcc_inst, 195 struct mpcc_state *s); 196 197 #endif 198
Indexes created Sun Sep 21 20:09:37 GMT 2025