1 /* $NetBSD: ddc_regs.h,v 1.2 2021/12/18 23:45:04 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-16 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ 29 #define DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ 30 31 #include "gpio_regs.h" 32 33 /****************************** new register headers */ 34 /*** following in header */ 35 36 #define DDC_GPIO_REG_LIST_ENTRY(type,cd,id) \ 37 .type ## _reg = REG(DC_GPIO_DDC ## id ## _ ## type),\ 38 .type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\ 39 .type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT 40 41 #define DDC_GPIO_REG_LIST(cd,id) \ 42 {\ 43 DDC_GPIO_REG_LIST_ENTRY(MASK,cd,id),\ 44 DDC_GPIO_REG_LIST_ENTRY(A,cd,id),\ 45 DDC_GPIO_REG_LIST_ENTRY(EN,cd,id),\ 46 DDC_GPIO_REG_LIST_ENTRY(Y,cd,id)\ 47 } 48 49 #define DDC_REG_LIST(cd,id) \ 50 DDC_GPIO_REG_LIST(cd,id),\ 51 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP) 52 53 #define DDC_REG_LIST_DCN2(cd, id) \ 54 DDC_GPIO_REG_LIST(cd, id),\ 55 .ddc_setup = REG(DC_I2C_DDC ## id ## _SETUP),\ 56 .phy_aux_cntl = REG(PHY_AUX_CNTL), \ 57 .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) 58 59 #define DDC_GPIO_VGA_REG_LIST_ENTRY(type,cd)\ 60 .type ## _reg = REG(DC_GPIO_DDCVGA_ ## type),\ 61 .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\ 62 .type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT 63 64 #define DDC_GPIO_VGA_REG_LIST(cd) \ 65 {\ 66 DDC_GPIO_VGA_REG_LIST_ENTRY(MASK,cd),\ 67 DDC_GPIO_VGA_REG_LIST_ENTRY(A,cd),\ 68 DDC_GPIO_VGA_REG_LIST_ENTRY(EN,cd),\ 69 DDC_GPIO_VGA_REG_LIST_ENTRY(Y,cd)\ 70 } 71 72 #define DDC_VGA_REG_LIST(cd) \ 73 DDC_GPIO_VGA_REG_LIST(cd),\ 74 .ddc_setup = mmDC_I2C_DDCVGA_SETUP 75 76 #define DDC_GPIO_I2C_REG_LIST_ENTRY(type,cd) \ 77 .type ## _reg = REG(DC_GPIO_I2CPAD_ ## type),\ 78 .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\ 79 .type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT 80 81 #define DDC_GPIO_I2C_REG_LIST(cd) \ 82 {\ 83 DDC_GPIO_I2C_REG_LIST_ENTRY(MASK,cd),\ 84 DDC_GPIO_I2C_REG_LIST_ENTRY(A,cd),\ 85 DDC_GPIO_I2C_REG_LIST_ENTRY(EN,cd),\ 86 DDC_GPIO_I2C_REG_LIST_ENTRY(Y,cd)\ 87 } 88 89 #define DDC_I2C_REG_LIST(cd) \ 90 DDC_GPIO_I2C_REG_LIST(cd),\ 91 .ddc_setup = 0 92 93 #define DDC_I2C_REG_LIST_DCN2(cd) \ 94 DDC_GPIO_I2C_REG_LIST(cd),\ 95 .ddc_setup = 0,\ 96 .phy_aux_cntl = REG(PHY_AUX_CNTL), \ 97 .dc_gpio_aux_ctrl_5 = REG(DC_GPIO_AUX_CTRL_5) 98 #define DDC_MASK_SH_LIST_COMMON(mask_sh) \ 99 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_ENABLE, mask_sh),\ 100 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_ENABLE, mask_sh),\ 101 SF_DDC(DC_I2C_DDC1_SETUP, DC_I2C_DDC1_EDID_DETECT_MODE, mask_sh),\ 102 SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1DATA_PD_EN, mask_sh),\ 103 SF_DDC(DC_GPIO_DDC1_MASK, DC_GPIO_DDC1CLK_PD_EN, mask_sh),\ 104 SF_DDC(DC_GPIO_DDC1_MASK, AUX_PAD1_MODE, mask_sh) 105 106 #define DDC_MASK_SH_LIST(mask_sh) \ 107 DDC_MASK_SH_LIST_COMMON(mask_sh),\ 108 SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SDA_PD_DIS, mask_sh),\ 109 SF_DDC(DC_GPIO_I2CPAD_MASK, DC_GPIO_SCL_PD_DIS, mask_sh) 110 111 #define DDC_MASK_SH_LIST_DCN2(mask_sh, cd) \ 112 {DDC_MASK_SH_LIST_COMMON(mask_sh),\ 113 0,\ 114 0,\ 115 (PHY_AUX_CNTL__AUX## cd ##_PAD_RXSEL## mask_sh),\ 116 (DC_GPIO_AUX_CTRL_5__DDC_PAD## cd ##_I2CMODE## mask_sh)} 117 118 struct ddc_registers { 119 struct gpio_registers gpio; 120 uint32_t ddc_setup; 121 uint32_t phy_aux_cntl; 122 uint32_t dc_gpio_aux_ctrl_5; 123 }; 124 125 struct ddc_sh_mask { 126 /* i2c_dd_setup */ 127 uint32_t DC_I2C_DDC1_ENABLE; 128 uint32_t DC_I2C_DDC1_EDID_DETECT_ENABLE; 129 uint32_t DC_I2C_DDC1_EDID_DETECT_MODE; 130 /* ddc1_mask */ 131 uint32_t DC_GPIO_DDC1DATA_PD_EN; 132 uint32_t DC_GPIO_DDC1CLK_PD_EN; 133 uint32_t AUX_PAD1_MODE; 134 /* i2cpad_mask */ 135 uint32_t DC_GPIO_SDA_PD_DIS; 136 uint32_t DC_GPIO_SCL_PD_DIS; 137 //phy_aux_cntl 138 uint32_t AUX_PAD_RXSEL; 139 uint32_t DDC_PAD_I2CMODE; 140 }; 141 142 143 144 /*** following in dc_resource */ 145 146 #define ddc_data_regs(id) \ 147 {\ 148 DDC_REG_LIST(DATA,id)\ 149 } 150 151 #define ddc_clk_regs(id) \ 152 {\ 153 DDC_REG_LIST(CLK,id)\ 154 } 155 156 #define ddc_vga_data_regs \ 157 {\ 158 DDC_VGA_REG_LIST(DATA)\ 159 } 160 161 #define ddc_vga_clk_regs \ 162 {\ 163 DDC_VGA_REG_LIST(CLK)\ 164 } 165 166 #define ddc_i2c_data_regs \ 167 {\ 168 DDC_I2C_REG_LIST(SDA)\ 169 } 170 171 #define ddc_i2c_clk_regs \ 172 {\ 173 DDC_I2C_REG_LIST(SCL)\ 174 } 175 #define ddc_data_regs_dcn2(id) \ 176 {\ 177 DDC_REG_LIST_DCN2(DATA, id)\ 178 } 179 180 #define ddc_clk_regs_dcn2(id) \ 181 {\ 182 DDC_REG_LIST_DCN2(CLK, id)\ 183 } 184 185 #define ddc_i2c_data_regs_dcn2 \ 186 {\ 187 DDC_I2C_REG_LIST_DCN2(SDA)\ 188 } 189 190 #define ddc_i2c_clk_regs_dcn2 \ 191 {\ 192 DDC_REG_LIST_DCN2(SCL)\ 193 } 194 195 196 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_GPIO_DDC_REGS_H_ */ 197
Indexes created Sun Sep 21 20:09:37 GMT 2025