1 /* $NetBSD: dcn_calcs.h,v 1.2 2021/12/18 23:45:05 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 /** 29 * Bandwidth and Watermark calculations interface. 30 * (Refer to "DCEx_mode_support.xlsm" from Perforce.) 31 */ 32 #ifndef __DCN_CALCS_H__ 33 #define __DCN_CALCS_H__ 34 35 #include "bw_fixed.h" 36 #include "../dml/display_mode_lib.h" 37 38 39 struct dc; 40 struct dc_state; 41 42 /******************************************************************************* 43 * DCN data structures. 44 ******************************************************************************/ 45 46 #define number_of_planes 6 47 #define number_of_planes_minus_one 5 48 #define number_of_states 4 49 #define number_of_states_plus_one 5 50 51 #define ddr4_dram_width 64 52 #define ddr4_dram_factor_single_Channel 16 53 enum dcn_bw_defs { 54 dcn_bw_v_min0p65, 55 dcn_bw_v_mid0p72, 56 dcn_bw_v_nom0p8, 57 dcn_bw_v_max0p9, 58 dcn_bw_v_max0p91, 59 dcn_bw_no_support = 5, 60 dcn_bw_yes, 61 dcn_bw_hor, 62 dcn_bw_vert, 63 dcn_bw_override, 64 dcn_bw_rgb_sub_64, 65 dcn_bw_rgb_sub_32, 66 dcn_bw_rgb_sub_16, 67 dcn_bw_no, 68 dcn_bw_sw_linear, 69 dcn_bw_sw_4_kb_d, 70 dcn_bw_sw_4_kb_d_x, 71 dcn_bw_sw_64_kb_d, 72 dcn_bw_sw_64_kb_d_t, 73 dcn_bw_sw_64_kb_d_x, 74 dcn_bw_sw_var_d, 75 dcn_bw_sw_var_d_x, 76 dcn_bw_yuv420_sub_8, 77 dcn_bw_sw_4_kb_s, 78 dcn_bw_sw_4_kb_s_x, 79 dcn_bw_sw_64_kb_s, 80 dcn_bw_sw_64_kb_s_t, 81 dcn_bw_sw_64_kb_s_x, 82 dcn_bw_writeback, 83 dcn_bw_444, 84 dcn_bw_dp, 85 dcn_bw_420, 86 dcn_bw_hdmi, 87 dcn_bw_sw_var_s, 88 dcn_bw_sw_var_s_x, 89 dcn_bw_yuv420_sub_10, 90 dcn_bw_supported_in_v_active, 91 dcn_bw_supported_in_v_blank, 92 dcn_bw_not_supported, 93 dcn_bw_na, 94 dcn_bw_encoder_8bpc, 95 dcn_bw_encoder_10bpc, 96 dcn_bw_encoder_12bpc, 97 dcn_bw_encoder_16bpc, 98 }; 99 100 /*bounding box parameters*/ 101 /*mode parameters*/ 102 /*system configuration*/ 103 /* display configuration*/ 104 struct dcn_bw_internal_vars { 105 float voltage[number_of_states_plus_one + 1]; 106 float max_dispclk[number_of_states_plus_one + 1]; 107 float max_dppclk[number_of_states_plus_one + 1]; 108 float dcfclk_per_state[number_of_states_plus_one + 1]; 109 float phyclk_per_state[number_of_states_plus_one + 1]; 110 float fabric_and_dram_bandwidth_per_state[number_of_states_plus_one + 1]; 111 float sr_exit_time; 112 float sr_enter_plus_exit_time; 113 float dram_clock_change_latency; 114 float urgent_latency; 115 float write_back_latency; 116 float percent_of_ideal_drambw_received_after_urg_latency; 117 float dcfclkv_max0p9; 118 float dcfclkv_nom0p8; 119 float dcfclkv_mid0p72; 120 float dcfclkv_min0p65; 121 float max_dispclk_vmax0p9; 122 float max_dppclk_vmax0p9; 123 float max_dispclk_vnom0p8; 124 float max_dppclk_vnom0p8; 125 float max_dispclk_vmid0p72; 126 float max_dppclk_vmid0p72; 127 float max_dispclk_vmin0p65; 128 float max_dppclk_vmin0p65; 129 float socclk; 130 float fabric_and_dram_bandwidth_vmax0p9; 131 float fabric_and_dram_bandwidth_vnom0p8; 132 float fabric_and_dram_bandwidth_vmid0p72; 133 float fabric_and_dram_bandwidth_vmin0p65; 134 float round_trip_ping_latency_cycles; 135 float urgent_out_of_order_return_per_channel; 136 float number_of_channels; 137 float vmm_page_size; 138 float return_bus_width; 139 float rob_buffer_size_in_kbyte; 140 float det_buffer_size_in_kbyte; 141 float dpp_output_buffer_pixels; 142 float opp_output_buffer_lines; 143 float pixel_chunk_size_in_kbyte; 144 float pte_chunk_size; 145 float meta_chunk_size; 146 float writeback_chunk_size; 147 enum dcn_bw_defs odm_capability; 148 enum dcn_bw_defs dsc_capability; 149 float line_buffer_size; 150 enum dcn_bw_defs is_line_buffer_bpp_fixed; 151 float line_buffer_fixed_bpp; 152 float max_line_buffer_lines; 153 float writeback_luma_buffer_size; 154 float writeback_chroma_buffer_size; 155 float max_num_dpp; 156 float max_num_writeback; 157 float max_dchub_topscl_throughput; 158 float max_pscl_tolb_throughput; 159 float max_lb_tovscl_throughput; 160 float max_vscl_tohscl_throughput; 161 float max_hscl_ratio; 162 float max_vscl_ratio; 163 float max_hscl_taps; 164 float max_vscl_taps; 165 float under_scan_factor; 166 float phyclkv_max0p9; 167 float phyclkv_nom0p8; 168 float phyclkv_mid0p72; 169 float phyclkv_min0p65; 170 float pte_buffer_size_in_requests; 171 float dispclk_ramping_margin; 172 float downspreading; 173 float max_inter_dcn_tile_repeaters; 174 enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 175 enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed; 176 int mode; 177 float viewport_width[number_of_planes_minus_one + 1]; 178 float htotal[number_of_planes_minus_one + 1]; 179 float vtotal[number_of_planes_minus_one + 1]; 180 float v_sync_plus_back_porch[number_of_planes_minus_one + 1]; 181 float vactive[number_of_planes_minus_one + 1]; 182 float pixel_clock[number_of_planes_minus_one + 1]; /*MHz*/ 183 float viewport_height[number_of_planes_minus_one + 1]; 184 enum dcn_bw_defs dcc_enable[number_of_planes_minus_one + 1]; 185 float dcc_rate[number_of_planes_minus_one + 1]; 186 enum dcn_bw_defs source_scan[number_of_planes_minus_one + 1]; 187 float lb_bit_per_pixel[number_of_planes_minus_one + 1]; 188 enum dcn_bw_defs source_pixel_format[number_of_planes_minus_one + 1]; 189 enum dcn_bw_defs source_surface_mode[number_of_planes_minus_one + 1]; 190 enum dcn_bw_defs output_format[number_of_planes_minus_one + 1]; 191 enum dcn_bw_defs output_deep_color[number_of_planes_minus_one + 1]; 192 enum dcn_bw_defs output[number_of_planes_minus_one + 1]; 193 float scaler_rec_out_width[number_of_planes_minus_one + 1]; 194 float scaler_recout_height[number_of_planes_minus_one + 1]; 195 float underscan_output[number_of_planes_minus_one + 1]; 196 float interlace_output[number_of_planes_minus_one + 1]; 197 float override_hta_ps[number_of_planes_minus_one + 1]; 198 float override_vta_ps[number_of_planes_minus_one + 1]; 199 float override_hta_pschroma[number_of_planes_minus_one + 1]; 200 float override_vta_pschroma[number_of_planes_minus_one + 1]; 201 float urgent_latency_support_us[number_of_planes_minus_one + 1]; 202 float h_ratio[number_of_planes_minus_one + 1]; 203 float v_ratio[number_of_planes_minus_one + 1]; 204 float htaps[number_of_planes_minus_one + 1]; 205 float vtaps[number_of_planes_minus_one + 1]; 206 float hta_pschroma[number_of_planes_minus_one + 1]; 207 float vta_pschroma[number_of_planes_minus_one + 1]; 208 enum dcn_bw_defs pte_enable; 209 enum dcn_bw_defs synchronized_vblank; 210 enum dcn_bw_defs ta_pscalculation; 211 int voltage_override_level; 212 int number_of_active_planes; 213 int voltage_level; 214 enum dcn_bw_defs immediate_flip_supported; 215 float dcfclk; 216 float max_phyclk; 217 float fabric_and_dram_bandwidth; 218 float dpp_per_plane_per_ratio[1 + 1][number_of_planes_minus_one + 1]; 219 enum dcn_bw_defs dispclk_dppclk_support_per_ratio[1 + 1]; 220 float required_dispclk_per_ratio[1 + 1]; 221 enum dcn_bw_defs error_message[1 + 1]; 222 int dispclk_dppclk_ratio; 223 float dpp_per_plane[number_of_planes_minus_one + 1]; 224 float det_buffer_size_y[number_of_planes_minus_one + 1]; 225 float det_buffer_size_c[number_of_planes_minus_one + 1]; 226 float swath_height_y[number_of_planes_minus_one + 1]; 227 float swath_height_c[number_of_planes_minus_one + 1]; 228 enum dcn_bw_defs final_error_message; 229 float frequency; 230 float header_line; 231 float header; 232 enum dcn_bw_defs voltage_override; 233 enum dcn_bw_defs allow_different_hratio_vratio; 234 float acceptable_quality_hta_ps; 235 float acceptable_quality_vta_ps; 236 float no_of_dpp[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 237 float swath_width_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 238 float swath_height_yper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 239 float swath_height_cper_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 240 float urgent_latency_support_us_per_state[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 241 float v_ratio_pre_ywith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 242 float v_ratio_pre_cwith_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 243 float required_prefetch_pixel_data_bw_with_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 244 float v_ratio_pre_ywithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 245 float v_ratio_pre_cwithout_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 246 float required_prefetch_pixel_data_bw_without_immediate_flip[number_of_states_plus_one + 1][1 + 1][number_of_planes_minus_one + 1]; 247 enum dcn_bw_defs prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 248 enum dcn_bw_defs prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 249 enum dcn_bw_defs v_ratio_in_prefetch_supported_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 250 enum dcn_bw_defs v_ratio_in_prefetch_supported_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 251 float required_dispclk[number_of_states_plus_one + 1][1 + 1]; 252 enum dcn_bw_defs dispclk_dppclk_support[number_of_states_plus_one + 1][1 + 1]; 253 enum dcn_bw_defs total_available_pipes_support[number_of_states_plus_one + 1][1 + 1]; 254 float total_number_of_active_dpp[number_of_states_plus_one + 1][1 + 1]; 255 float total_number_of_dcc_active_dpp[number_of_states_plus_one + 1][1 + 1]; 256 enum dcn_bw_defs urgent_latency_support[number_of_states_plus_one + 1][1 + 1]; 257 enum dcn_bw_defs mode_support_with_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 258 enum dcn_bw_defs mode_support_without_immediate_flip[number_of_states_plus_one + 1][1 + 1]; 259 float return_bw_per_state[number_of_states_plus_one + 1]; 260 enum dcn_bw_defs dio_support[number_of_states_plus_one + 1]; 261 float urgent_round_trip_and_out_of_order_latency_per_state[number_of_states_plus_one + 1]; 262 enum dcn_bw_defs rob_support[number_of_states_plus_one + 1]; 263 enum dcn_bw_defs bandwidth_support[number_of_states_plus_one + 1]; 264 float prefetch_bw[number_of_planes_minus_one + 1]; 265 float meta_pte_bytes_per_frame[number_of_planes_minus_one + 1]; 266 float meta_row_bytes[number_of_planes_minus_one + 1]; 267 float dpte_bytes_per_row[number_of_planes_minus_one + 1]; 268 float prefetch_lines_y[number_of_planes_minus_one + 1]; 269 float prefetch_lines_c[number_of_planes_minus_one + 1]; 270 float max_num_sw_y[number_of_planes_minus_one + 1]; 271 float max_num_sw_c[number_of_planes_minus_one + 1]; 272 float line_times_for_prefetch[number_of_planes_minus_one + 1]; 273 float lines_for_meta_pte_with_immediate_flip[number_of_planes_minus_one + 1]; 274 float lines_for_meta_pte_without_immediate_flip[number_of_planes_minus_one + 1]; 275 float lines_for_meta_and_dpte_row_with_immediate_flip[number_of_planes_minus_one + 1]; 276 float lines_for_meta_and_dpte_row_without_immediate_flip[number_of_planes_minus_one + 1]; 277 float min_dppclk_using_single_dpp[number_of_planes_minus_one + 1]; 278 float swath_width_ysingle_dpp[number_of_planes_minus_one + 1]; 279 float byte_per_pixel_in_dety[number_of_planes_minus_one + 1]; 280 float byte_per_pixel_in_detc[number_of_planes_minus_one + 1]; 281 float number_of_dpp_required_for_det_and_lb_size[number_of_planes_minus_one + 1]; 282 float required_phyclk[number_of_planes_minus_one + 1]; 283 float read256_block_height_y[number_of_planes_minus_one + 1]; 284 float read256_block_width_y[number_of_planes_minus_one + 1]; 285 float read256_block_height_c[number_of_planes_minus_one + 1]; 286 float read256_block_width_c[number_of_planes_minus_one + 1]; 287 float max_swath_height_y[number_of_planes_minus_one + 1]; 288 float max_swath_height_c[number_of_planes_minus_one + 1]; 289 float min_swath_height_y[number_of_planes_minus_one + 1]; 290 float min_swath_height_c[number_of_planes_minus_one + 1]; 291 float read_bandwidth[number_of_planes_minus_one + 1]; 292 float write_bandwidth[number_of_planes_minus_one + 1]; 293 float pscl_factor[number_of_planes_minus_one + 1]; 294 float pscl_factor_chroma[number_of_planes_minus_one + 1]; 295 enum dcn_bw_defs scale_ratio_support; 296 enum dcn_bw_defs source_format_pixel_and_scan_support; 297 float total_read_bandwidth_consumed_gbyte_per_second; 298 float total_write_bandwidth_consumed_gbyte_per_second; 299 float total_bandwidth_consumed_gbyte_per_second; 300 enum dcn_bw_defs dcc_enabled_in_any_plane; 301 float return_bw_todcn_per_state; 302 float critical_point; 303 enum dcn_bw_defs writeback_latency_support; 304 float required_output_bw; 305 float total_number_of_active_writeback; 306 enum dcn_bw_defs total_available_writeback_support; 307 float maximum_swath_width; 308 float number_of_dpp_required_for_det_size; 309 float number_of_dpp_required_for_lb_size; 310 float min_dispclk_using_single_dpp; 311 float min_dispclk_using_dual_dpp; 312 enum dcn_bw_defs viewport_size_support; 313 float swath_width_granularity_y; 314 float rounded_up_max_swath_size_bytes_y; 315 float swath_width_granularity_c; 316 float rounded_up_max_swath_size_bytes_c; 317 float lines_in_det_luma; 318 float lines_in_det_chroma; 319 float effective_lb_latency_hiding_source_lines_luma; 320 float effective_lb_latency_hiding_source_lines_chroma; 321 float effective_detlb_lines_luma; 322 float effective_detlb_lines_chroma; 323 float projected_dcfclk_deep_sleep; 324 float meta_req_height_y; 325 float meta_req_width_y; 326 float meta_surface_width_y; 327 float meta_surface_height_y; 328 float meta_pte_bytes_per_frame_y; 329 float meta_row_bytes_y; 330 float macro_tile_block_size_bytes_y; 331 float macro_tile_block_height_y; 332 float data_pte_req_height_y; 333 float data_pte_req_width_y; 334 float dpte_bytes_per_row_y; 335 float meta_req_height_c; 336 float meta_req_width_c; 337 float meta_surface_width_c; 338 float meta_surface_height_c; 339 float meta_pte_bytes_per_frame_c; 340 float meta_row_bytes_c; 341 float macro_tile_block_size_bytes_c; 342 float macro_tile_block_height_c; 343 float macro_tile_block_width_c; 344 float data_pte_req_height_c; 345 float data_pte_req_width_c; 346 float dpte_bytes_per_row_c; 347 float v_init_y; 348 float max_partial_sw_y; 349 float v_init_c; 350 float max_partial_sw_c; 351 float dst_x_after_scaler; 352 float dst_y_after_scaler; 353 float time_calc; 354 float v_update_offset[number_of_planes_minus_one + 1][2]; 355 float total_repeater_delay; 356 float v_update_width[number_of_planes_minus_one + 1][2]; 357 float v_ready_offset[number_of_planes_minus_one + 1][2]; 358 float time_setup; 359 float extra_latency; 360 float maximum_vstartup; 361 float bw_available_for_immediate_flip; 362 float total_immediate_flip_bytes[number_of_planes_minus_one + 1]; 363 float time_for_meta_pte_with_immediate_flip; 364 float time_for_meta_pte_without_immediate_flip; 365 float time_for_meta_and_dpte_row_with_immediate_flip; 366 float time_for_meta_and_dpte_row_without_immediate_flip; 367 float line_times_to_request_prefetch_pixel_data_with_immediate_flip; 368 float line_times_to_request_prefetch_pixel_data_without_immediate_flip; 369 float maximum_read_bandwidth_with_prefetch_with_immediate_flip; 370 float maximum_read_bandwidth_with_prefetch_without_immediate_flip; 371 float voltage_level_with_immediate_flip; 372 float voltage_level_without_immediate_flip; 373 float total_number_of_active_dpp_per_ratio[1 + 1]; 374 float byte_per_pix_dety; 375 float byte_per_pix_detc; 376 float read256_bytes_block_height_y; 377 float read256_bytes_block_width_y; 378 float read256_bytes_block_height_c; 379 float read256_bytes_block_width_c; 380 float maximum_swath_height_y; 381 float maximum_swath_height_c; 382 float minimum_swath_height_y; 383 float minimum_swath_height_c; 384 float swath_width; 385 float prefetch_bandwidth[number_of_planes_minus_one + 1]; 386 float v_init_pre_fill_y[number_of_planes_minus_one + 1]; 387 float v_init_pre_fill_c[number_of_planes_minus_one + 1]; 388 float max_num_swath_y[number_of_planes_minus_one + 1]; 389 float max_num_swath_c[number_of_planes_minus_one + 1]; 390 float prefill_y[number_of_planes_minus_one + 1]; 391 float prefill_c[number_of_planes_minus_one + 1]; 392 float v_startup[number_of_planes_minus_one + 1]; 393 enum dcn_bw_defs allow_dram_clock_change_during_vblank[number_of_planes_minus_one + 1]; 394 float allow_dram_self_refresh_during_vblank[number_of_planes_minus_one + 1]; 395 float v_ratio_prefetch_y[number_of_planes_minus_one + 1]; 396 float v_ratio_prefetch_c[number_of_planes_minus_one + 1]; 397 float destination_lines_for_prefetch[number_of_planes_minus_one + 1]; 398 float destination_lines_to_request_vm_inv_blank[number_of_planes_minus_one + 1]; 399 float destination_lines_to_request_row_in_vblank[number_of_planes_minus_one + 1]; 400 float min_ttuv_blank[number_of_planes_minus_one + 1]; 401 float byte_per_pixel_dety[number_of_planes_minus_one + 1]; 402 float byte_per_pixel_detc[number_of_planes_minus_one + 1]; 403 float swath_width_y[number_of_planes_minus_one + 1]; 404 float lines_in_dety[number_of_planes_minus_one + 1]; 405 float lines_in_dety_rounded_down_to_swath[number_of_planes_minus_one + 1]; 406 float lines_in_detc[number_of_planes_minus_one + 1]; 407 float lines_in_detc_rounded_down_to_swath[number_of_planes_minus_one + 1]; 408 float full_det_buffering_time_y[number_of_planes_minus_one + 1]; 409 float full_det_buffering_time_c[number_of_planes_minus_one + 1]; 410 float active_dram_clock_change_latency_margin[number_of_planes_minus_one + 1]; 411 float v_blank_dram_clock_change_latency_margin[number_of_planes_minus_one + 1]; 412 float dcfclk_deep_sleep_per_plane[number_of_planes_minus_one + 1]; 413 float read_bandwidth_plane_luma[number_of_planes_minus_one + 1]; 414 float read_bandwidth_plane_chroma[number_of_planes_minus_one + 1]; 415 float display_pipe_line_delivery_time_luma[number_of_planes_minus_one + 1]; 416 float display_pipe_line_delivery_time_chroma[number_of_planes_minus_one + 1]; 417 float display_pipe_line_delivery_time_luma_prefetch[number_of_planes_minus_one + 1]; 418 float display_pipe_line_delivery_time_chroma_prefetch[number_of_planes_minus_one + 1]; 419 float pixel_pte_bytes_per_row[number_of_planes_minus_one + 1]; 420 float meta_pte_bytes_frame[number_of_planes_minus_one + 1]; 421 float meta_row_byte[number_of_planes_minus_one + 1]; 422 float prefetch_source_lines_y[number_of_planes_minus_one + 1]; 423 float prefetch_source_lines_c[number_of_planes_minus_one + 1]; 424 float pscl_throughput[number_of_planes_minus_one + 1]; 425 float pscl_throughput_chroma[number_of_planes_minus_one + 1]; 426 float output_bpphdmi[number_of_planes_minus_one + 1]; 427 float output_bppdp4_lane_hbr[number_of_planes_minus_one + 1]; 428 float output_bppdp4_lane_hbr2[number_of_planes_minus_one + 1]; 429 float output_bppdp4_lane_hbr3[number_of_planes_minus_one + 1]; 430 float max_vstartup_lines[number_of_planes_minus_one + 1]; 431 float dispclk_with_ramping; 432 float dispclk_without_ramping; 433 float dppclk_using_single_dpp_luma; 434 float dppclk_using_single_dpp; 435 float dppclk_using_single_dpp_chroma; 436 enum dcn_bw_defs odm_capable; 437 float dispclk; 438 float dppclk; 439 float return_bandwidth_to_dcn; 440 enum dcn_bw_defs dcc_enabled_any_plane; 441 float return_bw; 442 float critical_compression; 443 float total_data_read_bandwidth; 444 float total_active_dpp; 445 float total_dcc_active_dpp; 446 float urgent_round_trip_and_out_of_order_latency; 447 float last_pixel_of_line_extra_watermark; 448 float data_fabric_line_delivery_time_luma; 449 float data_fabric_line_delivery_time_chroma; 450 float urgent_extra_latency; 451 float urgent_watermark; 452 float ptemeta_urgent_watermark; 453 float dram_clock_change_watermark; 454 float total_active_writeback; 455 float writeback_dram_clock_change_watermark; 456 float min_full_det_buffering_time; 457 float frame_time_for_min_full_det_buffering_time; 458 float average_read_bandwidth_gbyte_per_second; 459 float part_of_burst_that_fits_in_rob; 460 float stutter_burst_time; 461 float stutter_efficiency_not_including_vblank; 462 float smallest_vblank; 463 float v_blank_time; 464 float stutter_efficiency; 465 float dcf_clk_deep_sleep; 466 float stutter_exit_watermark; 467 float stutter_enter_plus_exit_watermark; 468 float effective_det_plus_lb_lines_luma; 469 float urgent_latency_support_us_luma; 470 float effective_det_plus_lb_lines_chroma; 471 float urgent_latency_support_us_chroma; 472 float min_urgent_latency_support_us; 473 float non_urgent_latency_tolerance; 474 float block_height256_bytes_y; 475 float block_height256_bytes_c; 476 float meta_request_width_y; 477 float meta_surf_width_y; 478 float meta_surf_height_y; 479 float meta_pte_bytes_frame_y; 480 float meta_row_byte_y; 481 float macro_tile_size_byte_y; 482 float macro_tile_height_y; 483 float pixel_pte_req_height_y; 484 float pixel_pte_req_width_y; 485 float pixel_pte_bytes_per_row_y; 486 float meta_request_width_c; 487 float meta_surf_width_c; 488 float meta_surf_height_c; 489 float meta_pte_bytes_frame_c; 490 float meta_row_byte_c; 491 float macro_tile_size_bytes_c; 492 float macro_tile_height_c; 493 float pixel_pte_req_height_c; 494 float pixel_pte_req_width_c; 495 float pixel_pte_bytes_per_row_c; 496 float max_partial_swath_y; 497 float max_partial_swath_c; 498 float t_calc; 499 float next_prefetch_mode; 500 float v_startup_lines; 501 enum dcn_bw_defs planes_with_room_to_increase_vstartup_prefetch_bw_less_than_active_bw; 502 enum dcn_bw_defs planes_with_room_to_increase_vstartup_vratio_prefetch_more_than4; 503 enum dcn_bw_defs planes_with_room_to_increase_vstartup_destination_line_times_for_prefetch_less_than2; 504 enum dcn_bw_defs v_ratio_prefetch_more_than4; 505 enum dcn_bw_defs destination_line_times_for_prefetch_less_than2; 506 float prefetch_mode; 507 float dstx_after_scaler; 508 float dsty_after_scaler; 509 float v_update_offset_pix[number_of_planes_minus_one + 1]; 510 float total_repeater_delay_time; 511 float v_update_width_pix[number_of_planes_minus_one + 1]; 512 float v_ready_offset_pix[number_of_planes_minus_one + 1]; 513 float t_setup; 514 float t_wait; 515 float bandwidth_available_for_immediate_flip; 516 float tot_immediate_flip_bytes; 517 float max_rd_bandwidth; 518 float time_for_fetching_meta_pte; 519 float time_for_fetching_row_in_vblank; 520 float lines_to_request_prefetch_pixel_data; 521 float required_prefetch_pix_data_bw; 522 enum dcn_bw_defs prefetch_mode_supported; 523 float active_dp_ps; 524 float lb_latency_hiding_source_lines_y; 525 float lb_latency_hiding_source_lines_c; 526 float effective_lb_latency_hiding_y; 527 float effective_lb_latency_hiding_c; 528 float dpp_output_buffer_lines_y; 529 float dpp_output_buffer_lines_c; 530 float dppopp_buffering_y; 531 float max_det_buffering_time_y; 532 float active_dram_clock_change_latency_margin_y; 533 float dppopp_buffering_c; 534 float max_det_buffering_time_c; 535 float active_dram_clock_change_latency_margin_c; 536 float writeback_dram_clock_change_latency_margin; 537 float min_active_dram_clock_change_margin; 538 float v_blank_of_min_active_dram_clock_change_margin; 539 float second_min_active_dram_clock_change_margin; 540 float min_vblank_dram_clock_change_margin; 541 float dram_clock_change_margin; 542 float dram_clock_change_support; 543 float wr_bandwidth; 544 float max_used_bw; 545 }; 546 547 struct dcn_soc_bounding_box { 548 float sr_exit_time; /*us*/ 549 float sr_enter_plus_exit_time; /*us*/ 550 float urgent_latency; /*us*/ 551 float write_back_latency; /*us*/ 552 float percent_of_ideal_drambw_received_after_urg_latency; /*%*/ 553 int max_request_size; /*bytes*/ 554 float dcfclkv_max0p9; /*MHz*/ 555 float dcfclkv_nom0p8; /*MHz*/ 556 float dcfclkv_mid0p72; /*MHz*/ 557 float dcfclkv_min0p65; /*MHz*/ 558 float max_dispclk_vmax0p9; /*MHz*/ 559 float max_dispclk_vmid0p72; /*MHz*/ 560 float max_dispclk_vnom0p8; /*MHz*/ 561 float max_dispclk_vmin0p65; /*MHz*/ 562 float max_dppclk_vmax0p9; /*MHz*/ 563 float max_dppclk_vnom0p8; /*MHz*/ 564 float max_dppclk_vmid0p72; /*MHz*/ 565 float max_dppclk_vmin0p65; /*MHz*/ 566 float socclk; /*MHz*/ 567 float fabric_and_dram_bandwidth_vmax0p9; /*GB/s*/ 568 float fabric_and_dram_bandwidth_vnom0p8; /*GB/s*/ 569 float fabric_and_dram_bandwidth_vmid0p72; /*GB/s*/ 570 float fabric_and_dram_bandwidth_vmin0p65; /*GB/s*/ 571 float phyclkv_max0p9; /*MHz*/ 572 float phyclkv_nom0p8; /*MHz*/ 573 float phyclkv_mid0p72; /*MHz*/ 574 float phyclkv_min0p65; /*MHz*/ 575 float downspreading; /*%*/ 576 int round_trip_ping_latency_cycles; /*DCFCLK Cycles*/ 577 int urgent_out_of_order_return_per_channel; /*bytes*/ 578 int number_of_channels; 579 int vmm_page_size; /*bytes*/ 580 float dram_clock_change_latency; /*us*/ 581 int return_bus_width; /*bytes*/ 582 float percent_disp_bw_limit; /*%*/ 583 }; 584 extern const struct dcn_soc_bounding_box dcn10_soc_defaults; 585 586 struct dcn_ip_params { 587 float rob_buffer_size_in_kbyte; 588 float det_buffer_size_in_kbyte; 589 float dpp_output_buffer_pixels; 590 float opp_output_buffer_lines; 591 float pixel_chunk_size_in_kbyte; 592 enum dcn_bw_defs pte_enable; 593 int pte_chunk_size; /*kbytes*/ 594 int meta_chunk_size; /*kbytes*/ 595 int writeback_chunk_size; /*kbytes*/ 596 enum dcn_bw_defs odm_capability; 597 enum dcn_bw_defs dsc_capability; 598 int line_buffer_size; /*bit*/ 599 int max_line_buffer_lines; 600 enum dcn_bw_defs is_line_buffer_bpp_fixed; 601 int line_buffer_fixed_bpp; 602 int writeback_luma_buffer_size; /*kbytes*/ 603 int writeback_chroma_buffer_size; /*kbytes*/ 604 int max_num_dpp; 605 int max_num_writeback; 606 int max_dchub_topscl_throughput; /*pixels/dppclk*/ 607 int max_pscl_tolb_throughput; /*pixels/dppclk*/ 608 int max_lb_tovscl_throughput; /*pixels/dppclk*/ 609 int max_vscl_tohscl_throughput; /*pixels/dppclk*/ 610 float max_hscl_ratio; 611 float max_vscl_ratio; 612 int max_hscl_taps; 613 int max_vscl_taps; 614 int pte_buffer_size_in_requests; 615 float dispclk_ramping_margin; /*%*/ 616 float under_scan_factor; 617 int max_inter_dcn_tile_repeaters; 618 enum dcn_bw_defs can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 619 enum dcn_bw_defs bug_forcing_luma_and_chroma_request_to_same_size_fixed; 620 int dcfclk_cstate_latency; 621 }; 622 extern const struct dcn_ip_params dcn10_ip_defaults; 623 624 bool dcn_validate_bandwidth( 625 struct dc *dc, 626 struct dc_state *context, 627 bool fast_validate); 628 629 unsigned int dcn_find_dcfclk_suits_all( 630 const struct dc *dc, 631 struct dc_clocks *clocks); 632 633 void dcn_bw_update_from_pplib(struct dc *dc); 634 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc); 635 void dcn_bw_sync_calcs_and_dml(struct dc *dc); 636 637 enum source_macro_tile_size swizzle_mode_to_macro_tile_size(enum swizzle_mode_values sw_mode); 638 639 #endif /* __DCN_CALCS_H__ */ 640 641
Indexes created Sun Sep 21 15:09:59 GMT 2025