1 /* $NetBSD: drm_edid.h,v 1.4 2021/12/19 00:46:15 riastradh Exp $ */ 2 3 /* 4 * Copyright 2007-2008 Intel Corporation 5 * Jesse Barnes <jesse.barnes (at) intel.com> 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 23 * OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 #ifndef __DRM_EDID_H__ 26 #define __DRM_EDID_H__ 27 28 #include <linux/types.h> 29 #include <linux/hdmi.h> 30 #include <drm/drm_mode.h> 31 32 struct drm_device; 33 struct i2c_adapter; 34 35 #define EDID_LENGTH 128 36 #define DDC_ADDR 0x50 37 #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ 38 39 #define CEA_EXT 0x02 40 #define VTB_EXT 0x10 41 #define DI_EXT 0x40 42 #define LS_EXT 0x50 43 #define MI_EXT 0x60 44 #define DISPLAYID_EXT 0x70 45 46 struct est_timings { 47 u8 t1; 48 u8 t2; 49 u8 mfg_rsvd; 50 } __attribute__((packed)); 51 52 /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ 53 #define EDID_TIMING_ASPECT_SHIFT 6 54 #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) 55 56 /* need to add 60 */ 57 #define EDID_TIMING_VFREQ_SHIFT 0 58 #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) 59 60 struct std_timing { 61 u8 hsize; /* need to multiply by 8 then add 248 */ 62 u8 vfreq_aspect; 63 } __attribute__((packed)); 64 65 #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) 66 #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) 67 #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) 68 #define DRM_EDID_PT_STEREO (1 << 5) 69 #define DRM_EDID_PT_INTERLACED (1 << 7) 70 71 /* If detailed data is pixel timing */ 72 struct detailed_pixel_timing { 73 u8 hactive_lo; 74 u8 hblank_lo; 75 u8 hactive_hblank_hi; 76 u8 vactive_lo; 77 u8 vblank_lo; 78 u8 vactive_vblank_hi; 79 u8 hsync_offset_lo; 80 u8 hsync_pulse_width_lo; 81 u8 vsync_offset_pulse_width_lo; 82 u8 hsync_vsync_offset_pulse_width_hi; 83 u8 width_mm_lo; 84 u8 height_mm_lo; 85 u8 width_height_mm_hi; 86 u8 hborder; 87 u8 vborder; 88 u8 misc; 89 } __attribute__((packed)); 90 91 /* If it's not pixel timing, it'll be one of the below */ 92 struct detailed_data_string { 93 u8 str[13]; 94 } __attribute__((packed)); 95 96 struct detailed_data_monitor_range { 97 u8 min_vfreq; 98 u8 max_vfreq; 99 u8 min_hfreq_khz; 100 u8 max_hfreq_khz; 101 u8 pixel_clock_mhz; /* need to multiply by 10 */ 102 u8 flags; 103 union { 104 struct { 105 u8 reserved; 106 u8 hfreq_start_khz; /* need to multiply by 2 */ 107 u8 c; /* need to divide by 2 */ 108 __le16 m; 109 u8 k; 110 u8 j; /* need to divide by 2 */ 111 } __attribute__((packed)) gtf2; 112 struct { 113 u8 version; 114 u8 data1; /* high 6 bits: extra clock resolution */ 115 u8 data2; /* plus low 2 of above: max hactive */ 116 u8 supported_aspects; 117 u8 flags; /* preferred aspect and blanking support */ 118 u8 supported_scalings; 119 u8 preferred_refresh; 120 } __attribute__((packed)) cvt; 121 } formula; 122 } __attribute__((packed)); 123 124 struct detailed_data_wpindex { 125 u8 white_yx_lo; /* Lower 2 bits each */ 126 u8 white_x_hi; 127 u8 white_y_hi; 128 u8 gamma; /* need to divide by 100 then add 1 */ 129 } __attribute__((packed)); 130 131 struct detailed_data_color_point { 132 u8 windex1; 133 u8 wpindex1[3]; 134 u8 windex2; 135 u8 wpindex2[3]; 136 } __attribute__((packed)); 137 138 struct cvt_timing { 139 u8 code[3]; 140 } __attribute__((packed)); 141 142 struct detailed_non_pixel { 143 u8 pad1; 144 u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name 145 fb=color point data, fa=standard timing data, 146 f9=undefined, f8=mfg. reserved */ 147 u8 pad2; 148 union { 149 struct detailed_data_string str; 150 struct detailed_data_monitor_range range; 151 struct detailed_data_wpindex color; 152 struct std_timing timings[6]; 153 struct cvt_timing cvt[4]; 154 } data; 155 } __attribute__((packed)); 156 157 #define EDID_DETAIL_EST_TIMINGS 0xf7 158 #define EDID_DETAIL_CVT_3BYTE 0xf8 159 #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 160 #define EDID_DETAIL_STD_MODES 0xfa 161 #define EDID_DETAIL_MONITOR_CPDATA 0xfb 162 #define EDID_DETAIL_MONITOR_NAME 0xfc 163 #define EDID_DETAIL_MONITOR_RANGE 0xfd 164 #define EDID_DETAIL_MONITOR_STRING 0xfe 165 #define EDID_DETAIL_MONITOR_SERIAL 0xff 166 167 struct detailed_timing { 168 __le16 pixel_clock; /* need to multiply by 10 KHz */ 169 union { 170 struct detailed_pixel_timing pixel_data; 171 struct detailed_non_pixel other_data; 172 } data; 173 } __attribute__((packed)); 174 175 #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) 176 #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) 177 #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) 178 #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) 179 #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) 180 #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) 181 #define DRM_EDID_INPUT_DIGITAL (1 << 7) 182 #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) /* 1.4 */ 183 #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) /* 1.4 */ 184 #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) /* 1.4 */ 185 #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) /* 1.4 */ 186 #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) /* 1.4 */ 187 #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) /* 1.4 */ 188 #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) /* 1.4 */ 189 #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) /* 1.4 */ 190 #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) /* 1.4 */ 191 #define DRM_EDID_DIGITAL_TYPE_MASK (7 << 0) /* 1.4 */ 192 #define DRM_EDID_DIGITAL_TYPE_UNDEF (0 << 0) /* 1.4 */ 193 #define DRM_EDID_DIGITAL_TYPE_DVI (1 << 0) /* 1.4 */ 194 #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2 << 0) /* 1.4 */ 195 #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3 << 0) /* 1.4 */ 196 #define DRM_EDID_DIGITAL_TYPE_MDDI (4 << 0) /* 1.4 */ 197 #define DRM_EDID_DIGITAL_TYPE_DP (5 << 0) /* 1.4 */ 198 #define DRM_EDID_DIGITAL_DFP_1_X (1 << 0) /* 1.3 */ 199 200 #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) 201 #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) 202 #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) 203 /* If analog */ 204 #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ 205 /* If digital */ 206 #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) 207 #define DRM_EDID_FEATURE_RGB (0 << 3) 208 #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) 209 #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) 210 #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ 211 212 #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) 213 #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) 214 #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) 215 216 #define DRM_EDID_HDMI_DC_48 (1 << 6) 217 #define DRM_EDID_HDMI_DC_36 (1 << 5) 218 #define DRM_EDID_HDMI_DC_30 (1 << 4) 219 #define DRM_EDID_HDMI_DC_Y444 (1 << 3) 220 221 /* YCBCR 420 deep color modes */ 222 #define DRM_EDID_YCBCR420_DC_48 (1 << 2) 223 #define DRM_EDID_YCBCR420_DC_36 (1 << 1) 224 #define DRM_EDID_YCBCR420_DC_30 (1 << 0) 225 #define DRM_EDID_YCBCR420_DC_MASK (DRM_EDID_YCBCR420_DC_48 | \ 226 DRM_EDID_YCBCR420_DC_36 | \ 227 DRM_EDID_YCBCR420_DC_30) 228 229 /* ELD Header Block */ 230 #define DRM_ELD_HEADER_BLOCK_SIZE 4 231 232 #define DRM_ELD_VER 0 233 # define DRM_ELD_VER_SHIFT 3 234 # define DRM_ELD_VER_MASK (0x1f << 3) 235 # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ 236 # define DRM_ELD_VER_CANNED (0x1f << 3) 237 238 #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ 239 240 /* ELD Baseline Block for ELD_Ver == 2 */ 241 #define DRM_ELD_CEA_EDID_VER_MNL 4 242 # define DRM_ELD_CEA_EDID_VER_SHIFT 5 243 # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) 244 # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) 245 # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) 246 # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) 247 # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) 248 # define DRM_ELD_MNL_SHIFT 0 249 # define DRM_ELD_MNL_MASK (0x1f << 0) 250 251 #define DRM_ELD_SAD_COUNT_CONN_TYPE 5 252 # define DRM_ELD_SAD_COUNT_SHIFT 4 253 # define DRM_ELD_SAD_COUNT_MASK (0xf << 4) 254 # define DRM_ELD_CONN_TYPE_SHIFT 2 255 # define DRM_ELD_CONN_TYPE_MASK (3 << 2) 256 # define DRM_ELD_CONN_TYPE_HDMI (0 << 2) 257 # define DRM_ELD_CONN_TYPE_DP (1 << 2) 258 # define DRM_ELD_SUPPORTS_AI (1 << 1) 259 # define DRM_ELD_SUPPORTS_HDCP (1 << 0) 260 261 #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ 262 # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ 263 264 #define DRM_ELD_SPEAKER 7 265 # define DRM_ELD_SPEAKER_MASK 0x7f 266 # define DRM_ELD_SPEAKER_RLRC (1 << 6) 267 # define DRM_ELD_SPEAKER_FLRC (1 << 5) 268 # define DRM_ELD_SPEAKER_RC (1 << 4) 269 # define DRM_ELD_SPEAKER_RLR (1 << 3) 270 # define DRM_ELD_SPEAKER_FC (1 << 2) 271 # define DRM_ELD_SPEAKER_LFE (1 << 1) 272 # define DRM_ELD_SPEAKER_FLR (1 << 0) 273 274 #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ 275 # define DRM_ELD_PORT_ID_LEN 8 276 277 #define DRM_ELD_MANUFACTURER_NAME0 16 278 #define DRM_ELD_MANUFACTURER_NAME1 17 279 280 #define DRM_ELD_PRODUCT_CODE0 18 281 #define DRM_ELD_PRODUCT_CODE1 19 282 283 #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ 284 285 #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) 286 287 struct edid { 288 u8 header[8]; 289 /* Vendor & product info */ 290 u8 mfg_id[2]; 291 u8 prod_code[2]; 292 u32 serial; /* FIXME: byte order */ 293 u8 mfg_week; 294 u8 mfg_year; 295 /* EDID version */ 296 u8 version; 297 u8 revision; 298 /* Display info: */ 299 u8 input; 300 u8 width_cm; 301 u8 height_cm; 302 u8 gamma; 303 u8 features; 304 /* Color characteristics */ 305 u8 red_green_lo; 306 u8 black_white_lo; 307 u8 red_x; 308 u8 red_y; 309 u8 green_x; 310 u8 green_y; 311 u8 blue_x; 312 u8 blue_y; 313 u8 white_x; 314 u8 white_y; 315 /* Est. timings and mfg rsvd timings*/ 316 struct est_timings established_timings; 317 /* Standard timings 1-8*/ 318 struct std_timing standard_timings[8]; 319 /* Detailing timings 1-4 */ 320 struct detailed_timing detailed_timings[4]; 321 /* Number of 128 byte ext. blocks */ 322 u8 extensions; 323 /* Checksum */ 324 u8 checksum; 325 } __attribute__((packed)); 326 327 #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) 328 329 /* Short Audio Descriptor */ 330 struct cea_sad { 331 u8 format; 332 u8 channels; /* max number of channels - 1 */ 333 u8 freq; 334 u8 byte2; /* meaning depends on format */ 335 }; 336 337 struct drm_encoder; 338 struct drm_connector; 339 struct drm_connector_state; 340 struct drm_display_mode; 341 342 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); 343 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); 344 int drm_av_sync_delay(struct drm_connector *connector, 345 const struct drm_display_mode *mode); 346 347 #ifdef CONFIG_DRM_LOAD_EDID_FIRMWARE 348 struct edid *drm_load_edid_firmware(struct drm_connector *connector); 349 int __drm_set_edid_firmware_path(const char *path); 350 int __drm_get_edid_firmware_path(char *buf, size_t bufsize); 351 #else 352 #include <linux/err.h> 353 static inline struct edid * 354 drm_load_edid_firmware(struct drm_connector *connector) 355 { 356 return ERR_PTR(-ENOENT); 357 } 358 #endif 359 360 int 361 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 362 struct drm_connector *connector, 363 const struct drm_display_mode *mode); 364 int 365 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 366 struct drm_connector *connector, 367 const struct drm_display_mode *mode); 368 369 void 370 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 371 const struct drm_connector_state *conn_state); 372 373 void 374 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 375 const struct drm_connector_state *conn_state); 376 377 void 378 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 379 struct drm_connector *connector, 380 const struct drm_display_mode *mode, 381 enum hdmi_quantization_range rgb_quant_range); 382 383 int 384 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 385 const struct drm_connector_state *conn_state); 386 387 /** 388 * drm_eld_mnl - Get ELD monitor name length in bytes. 389 * @eld: pointer to an eld memory structure with mnl set 390 */ 391 static inline int drm_eld_mnl(const uint8_t *eld) 392 { 393 return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; 394 } 395 396 /** 397 * drm_eld_sad - Get ELD SAD structures. 398 * @eld: pointer to an eld memory structure with sad_count set 399 */ 400 static inline const uint8_t *drm_eld_sad(const uint8_t *eld) 401 { 402 unsigned int ver, mnl; 403 404 ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; 405 if (ver != 2 && ver != 31) 406 return NULL; 407 408 mnl = drm_eld_mnl(eld); 409 if (mnl > 16) 410 return NULL; 411 412 return eld + DRM_ELD_CEA_SAD(mnl, 0); 413 } 414 415 /** 416 * drm_eld_sad_count - Get ELD SAD count. 417 * @eld: pointer to an eld memory structure with sad_count set 418 */ 419 static inline int drm_eld_sad_count(const uint8_t *eld) 420 { 421 return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> 422 DRM_ELD_SAD_COUNT_SHIFT; 423 } 424 425 /** 426 * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes 427 * @eld: pointer to an eld memory structure with mnl and sad_count set 428 * 429 * This is a helper for determining the payload size of the baseline block, in 430 * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. 431 */ 432 static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) 433 { 434 return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + 435 drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; 436 } 437 438 /** 439 * drm_eld_size - Get ELD size in bytes 440 * @eld: pointer to a complete eld memory structure 441 * 442 * The returned value does not include the vendor block. It's vendor specific, 443 * and comprises of the remaining bytes in the ELD memory buffer after 444 * drm_eld_size() bytes of header and baseline block. 445 * 446 * The returned value is guaranteed to be a multiple of 4. 447 */ 448 static inline int drm_eld_size(const uint8_t *eld) 449 { 450 return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; 451 } 452 453 /** 454 * drm_eld_get_spk_alloc - Get speaker allocation 455 * @eld: pointer to an ELD memory structure 456 * 457 * The returned value is the speakers mask. User has to use %DRM_ELD_SPEAKER 458 * field definitions to identify speakers. 459 */ 460 static inline u8 drm_eld_get_spk_alloc(const uint8_t *eld) 461 { 462 return eld[DRM_ELD_SPEAKER] & DRM_ELD_SPEAKER_MASK; 463 } 464 465 /** 466 * drm_eld_get_conn_type - Get device type hdmi/dp connected 467 * @eld: pointer to an ELD memory structure 468 * 469 * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to 470 * identify the display type connected. 471 */ 472 static inline u8 drm_eld_get_conn_type(const uint8_t *eld) 473 { 474 return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; 475 } 476 477 bool drm_probe_ddc(struct i2c_adapter *adapter); 478 struct edid *drm_do_get_edid(struct drm_connector *connector, 479 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 480 size_t len), 481 void *data); 482 struct edid *drm_get_edid(struct drm_connector *connector, 483 struct i2c_adapter *adapter); 484 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 485 struct i2c_adapter *adapter); 486 struct edid *drm_edid_duplicate(const struct edid *edid); 487 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid); 488 int drm_add_override_edid_modes(struct drm_connector *connector); 489 490 u8 drm_match_cea_mode(const struct drm_display_mode *to_match); 491 bool drm_detect_hdmi_monitor(struct edid *edid); 492 bool drm_detect_monitor_audio(struct edid *edid); 493 enum hdmi_quantization_range 494 drm_default_rgb_quant_range(const struct drm_display_mode *mode); 495 int drm_add_modes_noedid(struct drm_connector *connector, 496 int hdisplay, int vdisplay); 497 void drm_set_preferred_mode(struct drm_connector *connector, 498 int hpref, int vpref); 499 500 int drm_edid_header_is_valid(const u8 *raw_edid); 501 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 502 bool *edid_corrupt); 503 bool drm_edid_is_valid(struct edid *edid); 504 void drm_edid_get_monitor_name(struct edid *edid, char *name, 505 int buflen); 506 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 507 int hsize, int vsize, int fresh, 508 bool rb); 509 #endif /* __DRM_EDID_H__ */ 510
Indexes created Sat Sep 20 22:09:52 GMT 2025