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      1 /*	$NetBSD: kfd_device_queue_manager_v9.c,v 1.2 2021/12/18 23:44:59 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2016-2018 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 
     26 #include <sys/cdefs.h>
     27 __KERNEL_RCSID(0, "$NetBSD: kfd_device_queue_manager_v9.c,v 1.2 2021/12/18 23:44:59 riastradh Exp $");
     28 
     29 #include "kfd_device_queue_manager.h"
     30 #include "vega10_enum.h"
     31 #include "gc/gc_9_0_offset.h"
     32 #include "gc/gc_9_0_sh_mask.h"
     33 #include "sdma0/sdma0_4_0_sh_mask.h"
     34 
     35 static int update_qpd_v9(struct device_queue_manager *dqm,
     36 			 struct qcm_process_device *qpd);
     37 static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
     38 			    struct qcm_process_device *qpd);
     39 
     40 void device_queue_manager_init_v9(
     41 	struct device_queue_manager_asic_ops *asic_ops)
     42 {
     43 	asic_ops->update_qpd = update_qpd_v9;
     44 	asic_ops->init_sdma_vm = init_sdma_vm_v9;
     45 	asic_ops->mqd_manager_init = mqd_manager_init_v9;
     46 }
     47 
     48 static uint32_t compute_sh_mem_bases_64bit(struct kfd_process_device *pdd)
     49 {
     50 	uint32_t shared_base = pdd->lds_base >> 48;
     51 	uint32_t private_base = pdd->scratch_base >> 48;
     52 
     53 	return (shared_base << SH_MEM_BASES__SHARED_BASE__SHIFT) |
     54 		private_base;
     55 }
     56 
     57 static int update_qpd_v9(struct device_queue_manager *dqm,
     58 			 struct qcm_process_device *qpd)
     59 {
     60 	struct kfd_process_device *pdd;
     61 
     62 	pdd = qpd_to_pdd(qpd);
     63 
     64 	/* check if sh_mem_config register already configured */
     65 	if (qpd->sh_mem_config == 0) {
     66 		qpd->sh_mem_config =
     67 				SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
     68 					SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
     69 		if (amdgpu_noretry &&
     70 		    !dqm->dev->device_info->needs_iommu_device)
     71 			qpd->sh_mem_config |=
     72 				1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
     73 
     74 		qpd->sh_mem_ape1_limit = 0;
     75 		qpd->sh_mem_ape1_base = 0;
     76 	}
     77 
     78 	qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
     79 
     80 	pr_debug("sh_mem_bases 0x%X\n", qpd->sh_mem_bases);
     81 
     82 	return 0;
     83 }
     84 
     85 static void init_sdma_vm_v9(struct device_queue_manager *dqm, struct queue *q,
     86 			    struct qcm_process_device *qpd)
     87 {
     88 	/* Not needed on SDMAv4 any more */
     89 	q->properties.sdma_vm_addr = 0;
     90 }
     91