Home | History | Annotate | Line # | Download | only in amdgpu 
      1 /*	$NetBSD: amdgpu_df_v1_7.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $	*/
      2 
      3 /*
      4  * Copyright 2018 Advanced Micro Devices, Inc.
      5  *
      6  * Permission is hereby granted, free of charge, to any person obtaining a
      7  * copy of this software and associated documentation files (the "Software"),
      8  * to deal in the Software without restriction, including without limitation
      9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
     10  * and/or sell copies of the Software, and to permit persons to whom the
     11  * Software is furnished to do so, subject to the following conditions:
     12  *
     13  * The above copyright notice and this permission notice shall be included in
     14  * all copies or substantial portions of the Software.
     15  *
     16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
     17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
     18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
     19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
     20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
     21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
     22  * OTHER DEALINGS IN THE SOFTWARE.
     23  *
     24  */
     25 #include <sys/cdefs.h>
     26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_df_v1_7.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
     27 
     28 #include "amdgpu.h"
     29 #include "df_v1_7.h"
     30 
     31 #include "df/df_1_7_default.h"
     32 #include "df/df_1_7_offset.h"
     33 #include "df/df_1_7_sh_mask.h"
     34 
     35 static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
     36 
     37 static void df_v1_7_sw_init(struct amdgpu_device *adev)
     38 {
     39 	adev->df.hash_status.hash_64k = false;
     40 	adev->df.hash_status.hash_2m = false;
     41 	adev->df.hash_status.hash_1g = false;
     42 }
     43 
     44 static void df_v1_7_sw_fini(struct amdgpu_device *adev)
     45 {
     46 }
     47 
     48 static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
     49                                           bool enable)
     50 {
     51 	u32 tmp;
     52 
     53 	if (enable) {
     54 		tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
     55 		tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
     56 		WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
     57 	} else
     58 		WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
     59 			     mmFabricConfigAccessControl_DEFAULT);
     60 }
     61 
     62 static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)
     63 {
     64 	u32 tmp;
     65 
     66 	tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
     67 	tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
     68 	tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
     69 
     70 	return tmp;
     71 }
     72 
     73 static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
     74 {
     75 	int fb_channel_number;
     76 
     77 	fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
     78 
     79 	return df_v1_7_channel_number[fb_channel_number];
     80 }
     81 
     82 static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
     83 						     bool enable)
     84 {
     85 	u32 tmp;
     86 
     87 	/* Put DF on broadcast mode */
     88 	adev->df.funcs->enable_broadcast_mode(adev, true);
     89 
     90 	if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
     91 		tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
     92 		tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
     93 		tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
     94 		WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
     95 	} else {
     96 		tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
     97 		tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
     98 		tmp |= DF_V1_7_MGCG_DISABLE;
     99 		WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
    100 	}
    101 
    102 	/* Exit boradcast mode */
    103 	adev->df.funcs->enable_broadcast_mode(adev, false);
    104 }
    105 
    106 static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
    107 					  u32 *flags)
    108 {
    109 	u32 tmp;
    110 
    111 	/* AMD_CG_SUPPORT_DF_MGCG */
    112 	tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
    113 	if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
    114 		*flags |= AMD_CG_SUPPORT_DF_MGCG;
    115 }
    116 
    117 static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
    118 						bool enable)
    119 {
    120 	WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,
    121 		       ForceParWrRMW, enable);
    122 }
    123 
    124 const struct amdgpu_df_funcs df_v1_7_funcs = {
    125 	.sw_init = df_v1_7_sw_init,
    126 	.sw_fini = df_v1_7_sw_fini,
    127 	.enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
    128 	.get_fb_channel_number = df_v1_7_get_fb_channel_number,
    129 	.get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
    130 	.update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
    131 	.get_clockgating_state = df_v1_7_get_clockgating_state,
    132 	.enable_ecc_force_par_wr_rmw = df_v1_7_enable_ecc_force_par_wr_rmw,
    133 };
    134