1 /* $NetBSD: kgd_pp_interface.h,v 1.2 2021/12/18 23:45:08 riastradh Exp $ */ 2 3 /* 4 * Copyright 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 */ 25 26 #ifndef __KGD_PP_INTERFACE_H__ 27 #define __KGD_PP_INTERFACE_H__ 28 29 extern const struct amdgpu_ip_block_version pp_smu_ip_block; 30 31 struct amd_vce_state { 32 /* vce clocks */ 33 u32 evclk; 34 u32 ecclk; 35 /* gpu clocks */ 36 u32 sclk; 37 u32 mclk; 38 u8 clk_idx; 39 u8 pstate; 40 }; 41 42 43 enum amd_dpm_forced_level { 44 AMD_DPM_FORCED_LEVEL_AUTO = 0x1, 45 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2, 46 AMD_DPM_FORCED_LEVEL_LOW = 0x4, 47 AMD_DPM_FORCED_LEVEL_HIGH = 0x8, 48 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10, 49 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20, 50 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40, 51 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80, 52 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100, 53 }; 54 55 enum amd_pm_state_type { 56 /* not used for dpm */ 57 POWER_STATE_TYPE_DEFAULT, 58 POWER_STATE_TYPE_POWERSAVE, 59 /* user selectable states */ 60 POWER_STATE_TYPE_BATTERY, 61 POWER_STATE_TYPE_BALANCED, 62 POWER_STATE_TYPE_PERFORMANCE, 63 /* internal states */ 64 POWER_STATE_TYPE_INTERNAL_UVD, 65 POWER_STATE_TYPE_INTERNAL_UVD_SD, 66 POWER_STATE_TYPE_INTERNAL_UVD_HD, 67 POWER_STATE_TYPE_INTERNAL_UVD_HD2, 68 POWER_STATE_TYPE_INTERNAL_UVD_MVC, 69 POWER_STATE_TYPE_INTERNAL_BOOT, 70 POWER_STATE_TYPE_INTERNAL_THERMAL, 71 POWER_STATE_TYPE_INTERNAL_ACPI, 72 POWER_STATE_TYPE_INTERNAL_ULV, 73 POWER_STATE_TYPE_INTERNAL_3DPERF, 74 }; 75 76 #define AMD_MAX_VCE_LEVELS 6 77 78 enum amd_vce_level { 79 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */ 80 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */ 81 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */ 82 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */ 83 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */ 84 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */ 85 }; 86 87 enum amd_fan_ctrl_mode { 88 AMD_FAN_CTRL_NONE = 0, 89 AMD_FAN_CTRL_MANUAL = 1, 90 AMD_FAN_CTRL_AUTO = 2, 91 }; 92 93 enum pp_clock_type { 94 PP_SCLK, 95 PP_MCLK, 96 PP_PCIE, 97 PP_SOCCLK, 98 PP_FCLK, 99 PP_DCEFCLK, 100 OD_SCLK, 101 OD_MCLK, 102 OD_VDDC_CURVE, 103 OD_RANGE, 104 }; 105 106 enum amd_pp_sensors { 107 AMDGPU_PP_SENSOR_GFX_SCLK = 0, 108 AMDGPU_PP_SENSOR_VDDNB, 109 AMDGPU_PP_SENSOR_VDDGFX, 110 AMDGPU_PP_SENSOR_UVD_VCLK, 111 AMDGPU_PP_SENSOR_UVD_DCLK, 112 AMDGPU_PP_SENSOR_VCE_ECCLK, 113 AMDGPU_PP_SENSOR_GPU_LOAD, 114 AMDGPU_PP_SENSOR_MEM_LOAD, 115 AMDGPU_PP_SENSOR_GFX_MCLK, 116 AMDGPU_PP_SENSOR_GPU_TEMP, 117 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP, 118 AMDGPU_PP_SENSOR_HOTSPOT_TEMP, 119 AMDGPU_PP_SENSOR_MEM_TEMP, 120 AMDGPU_PP_SENSOR_VCE_POWER, 121 AMDGPU_PP_SENSOR_UVD_POWER, 122 AMDGPU_PP_SENSOR_GPU_POWER, 123 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, 124 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, 125 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, 126 AMDGPU_PP_SENSOR_MIN_FAN_RPM, 127 AMDGPU_PP_SENSOR_MAX_FAN_RPM, 128 AMDGPU_PP_SENSOR_VCN_POWER_STATE, 129 }; 130 131 enum amd_pp_task { 132 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE, 133 AMD_PP_TASK_ENABLE_USER_STATE, 134 AMD_PP_TASK_READJUST_POWER_STATE, 135 AMD_PP_TASK_COMPLETE_INIT, 136 AMD_PP_TASK_MAX 137 }; 138 139 enum PP_SMC_POWER_PROFILE { 140 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0, 141 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1, 142 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2, 143 PP_SMC_POWER_PROFILE_VIDEO = 0x3, 144 PP_SMC_POWER_PROFILE_VR = 0x4, 145 PP_SMC_POWER_PROFILE_COMPUTE = 0x5, 146 PP_SMC_POWER_PROFILE_CUSTOM = 0x6, 147 PP_SMC_POWER_PROFILE_COUNT, 148 }; 149 150 enum { 151 PP_GROUP_UNKNOWN = 0, 152 PP_GROUP_GFX = 1, 153 PP_GROUP_SYS, 154 PP_GROUP_MAX 155 }; 156 157 enum PP_OD_DPM_TABLE_COMMAND { 158 PP_OD_EDIT_SCLK_VDDC_TABLE, 159 PP_OD_EDIT_MCLK_VDDC_TABLE, 160 PP_OD_EDIT_VDDC_CURVE, 161 PP_OD_RESTORE_DEFAULT_TABLE, 162 PP_OD_COMMIT_DPM_TABLE 163 }; 164 165 struct pp_states_info { 166 uint32_t nums; 167 uint32_t states[16]; 168 }; 169 170 enum PP_HWMON_TEMP { 171 PP_TEMP_EDGE = 0, 172 PP_TEMP_JUNCTION, 173 PP_TEMP_MEM, 174 PP_TEMP_MAX 175 }; 176 177 enum pp_mp1_state { 178 PP_MP1_STATE_NONE, 179 PP_MP1_STATE_SHUTDOWN, 180 PP_MP1_STATE_UNLOAD, 181 PP_MP1_STATE_RESET, 182 }; 183 184 enum pp_df_cstate { 185 DF_CSTATE_DISALLOW = 0, 186 DF_CSTATE_ALLOW, 187 }; 188 189 #define PP_GROUP_MASK 0xF0000000 190 #define PP_GROUP_SHIFT 28 191 192 #define PP_BLOCK_MASK 0x0FFFFF00 193 #define PP_BLOCK_SHIFT 8 194 195 #define PP_BLOCK_GFX_CG 0x01 196 #define PP_BLOCK_GFX_MG 0x02 197 #define PP_BLOCK_GFX_3D 0x04 198 #define PP_BLOCK_GFX_RLC 0x08 199 #define PP_BLOCK_GFX_CP 0x10 200 #define PP_BLOCK_SYS_BIF 0x01 201 #define PP_BLOCK_SYS_MC 0x02 202 #define PP_BLOCK_SYS_ROM 0x04 203 #define PP_BLOCK_SYS_DRM 0x08 204 #define PP_BLOCK_SYS_HDP 0x10 205 #define PP_BLOCK_SYS_SDMA 0x20 206 207 #define PP_STATE_MASK 0x0000000F 208 #define PP_STATE_SHIFT 0 209 #define PP_STATE_SUPPORT_MASK 0x000000F0 210 #define PP_STATE_SUPPORT_SHIFT 0 211 212 #define PP_STATE_CG 0x01 213 #define PP_STATE_LS 0x02 214 #define PP_STATE_DS 0x04 215 #define PP_STATE_SD 0x08 216 #define PP_STATE_SUPPORT_CG 0x10 217 #define PP_STATE_SUPPORT_LS 0x20 218 #define PP_STATE_SUPPORT_DS 0x40 219 #define PP_STATE_SUPPORT_SD 0x80 220 221 #define PP_CG_MSG_ID(group, block, support, state) \ 222 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \ 223 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT) 224 225 #define XGMI_MODE_PSTATE_D3 0 226 #define XGMI_MODE_PSTATE_D0 1 227 228 struct seq_file; 229 enum amd_pp_clock_type; 230 struct amd_pp_simple_clock_info; 231 struct amd_pp_display_configuration; 232 struct amd_pp_clock_info; 233 struct pp_display_clock_request; 234 struct pp_clock_levels_with_voltage; 235 struct pp_clock_levels_with_latency; 236 struct amd_pp_clocks; 237 238 struct amd_pm_funcs { 239 /* export for dpm on ci and si */ 240 int (*pre_set_power_state)(void *handle); 241 int (*set_power_state)(void *handle); 242 void (*post_set_power_state)(void *handle); 243 void (*display_configuration_changed)(void *handle); 244 void (*print_power_state)(void *handle, void *ps); 245 bool (*vblank_too_short)(void *handle); 246 void (*enable_bapm)(void *handle, bool enable); 247 int (*check_state_equal)(void *handle, 248 void *cps, 249 void *rps, 250 bool *equal); 251 /* export for sysfs */ 252 void (*set_fan_control_mode)(void *handle, u32 mode); 253 u32 (*get_fan_control_mode)(void *handle); 254 int (*set_fan_speed_percent)(void *handle, u32 speed); 255 int (*get_fan_speed_percent)(void *handle, u32 *speed); 256 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask); 257 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf); 258 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level); 259 int (*get_sclk_od)(void *handle); 260 int (*set_sclk_od)(void *handle, uint32_t value); 261 int (*get_mclk_od)(void *handle); 262 int (*set_mclk_od)(void *handle, uint32_t value); 263 int (*read_sensor)(void *handle, int idx, void *value, int *size); 264 enum amd_dpm_forced_level (*get_performance_level)(void *handle); 265 enum amd_pm_state_type (*get_current_power_state)(void *handle); 266 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm); 267 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm); 268 int (*get_pp_num_states)(void *handle, struct pp_states_info *data); 269 int (*get_pp_table)(void *handle, char **table); 270 int (*set_pp_table)(void *handle, const char *buf, size_t size); 271 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m); 272 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en); 273 /* export to amdgpu */ 274 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx); 275 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id, 276 enum amd_pm_state_type *user_state); 277 int (*load_firmware)(void *handle); 278 int (*wait_for_fw_loading_complete)(void *handle); 279 int (*set_powergating_by_smu)(void *handle, 280 uint32_t block_type, bool gate); 281 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id); 282 int (*set_power_limit)(void *handle, uint32_t n); 283 int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit); 284 int (*get_power_profile_mode)(void *handle, char *buf); 285 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size); 286 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size); 287 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state); 288 int (*smu_i2c_bus_access)(void *handle, bool acquire); 289 /* export to DC */ 290 u32 (*get_sclk)(void *handle, bool low); 291 u32 (*get_mclk)(void *handle, bool low); 292 int (*display_configuration_change)(void *handle, 293 const struct amd_pp_display_configuration *input); 294 int (*get_display_power_level)(void *handle, 295 struct amd_pp_simple_clock_info *output); 296 int (*get_current_clocks)(void *handle, 297 struct amd_pp_clock_info *clocks); 298 int (*get_clock_by_type)(void *handle, 299 enum amd_pp_clock_type type, 300 struct amd_pp_clocks *clocks); 301 int (*get_clock_by_type_with_latency)(void *handle, 302 enum amd_pp_clock_type type, 303 struct pp_clock_levels_with_latency *clocks); 304 int (*get_clock_by_type_with_voltage)(void *handle, 305 enum amd_pp_clock_type type, 306 struct pp_clock_levels_with_voltage *clocks); 307 int (*set_watermarks_for_clocks_ranges)(void *handle, 308 void *clock_ranges); 309 int (*display_clock_voltage_request)(void *handle, 310 struct pp_display_clock_request *clock); 311 int (*get_display_mode_validation_clocks)(void *handle, 312 struct amd_pp_simple_clock_info *clocks); 313 int (*notify_smu_enable_pwe)(void *handle); 314 int (*enable_mgpu_fan_boost)(void *handle); 315 int (*set_active_display_count)(void *handle, uint32_t count); 316 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock); 317 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock); 318 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock); 319 int (*get_asic_baco_capability)(void *handle, bool *cap); 320 int (*get_asic_baco_state)(void *handle, int *state); 321 int (*set_asic_baco_state)(void *handle, int state); 322 int (*get_ppfeature_status)(void *handle, char *buf); 323 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks); 324 int (*asic_reset_mode_2)(void *handle); 325 int (*set_df_cstate)(void *handle, enum pp_df_cstate state); 326 int (*set_xgmi_pstate)(void *handle, uint32_t pstate); 327 }; 328 329 #endif 330
Indexes created Sun Sep 21 14:09:52 GMT 2025