1 /* $NetBSD: siireg.h,v 1.3 2021/08/17 22:00:30 andvar Exp $ */ 2 3 /* 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)siireg.h 8.1 (Berkeley) 6/10/93 35 * 36 * sii.h -- 37 * 38 * SII registers. 39 * 40 * Copyright (C) 1989 Digital Equipment Corporation. 41 * Permission to use, copy, modify, and distribute this software and 42 * its documentation for any purpose and without fee is hereby granted, 43 * provided that the above copyright notice appears in all copies. 44 * Digital Equipment Corporation makes no representations about the 45 * suitability of this software for any purpose. It is provided "as is" 46 * without express or implied warranty. 47 * 48 * from: Header: /sprite/src/kernel/dev/ds3100.md/RCS/sii.h, 49 * v 1.2 89/08/15 19:53:04 rab Exp SPRITE (DECWRL) 50 */ 51 52 #ifndef _SII 53 #define _SII 54 55 /* 56 * SII hardware registers 57 */ 58 typedef volatile struct { 59 u_short sdb; /* SCSI Data Bus and Parity */ 60 u_short pad0; 61 u_short sc1; /* SCSI Control Signals One */ 62 u_short pad1; 63 u_short sc2; /* SCSI Control Signals Two */ 64 u_short pad2; 65 u_short csr; /* Control/Status register */ 66 u_short pad3; 67 u_short id; /* Bus ID register */ 68 u_short pad4; 69 u_short slcsr; /* Select Control and Status Register */ 70 u_short pad5; 71 u_short destat; /* Selection Detector Status Register */ 72 u_short pad6; 73 u_short dstmo; /* DSSI Timeout Register */ 74 u_short pad7; 75 u_short data; /* Data Register */ 76 u_short pad8; 77 u_short dmctrl; /* DMA Control Register */ 78 u_short pad9; 79 u_short dmlotc; /* DMA Length of Transfer Counter */ 80 u_short pad10; 81 u_short dmaddrl; /* DMA Address Register Low */ 82 u_short pad11; 83 u_short dmaddrh; /* DMA Address Register High */ 84 u_short pad12; 85 u_short dmabyte; /* DMA Initial Byte Register */ 86 u_short pad13; 87 u_short stlp; /* DSSI Short Target List Pointer */ 88 u_short pad14; 89 u_short ltlp; /* DSSI Long Target List Pointer */ 90 u_short pad15; 91 u_short ilp; /* DSSI Initiator List Pointer */ 92 u_short pad16; 93 u_short dsctrl; /* DSSI Control Register */ 94 u_short pad17; 95 u_short cstat; /* Connection Status Register */ 96 u_short pad18; 97 u_short dstat; /* Data Transfer Status Register */ 98 u_short pad19; 99 u_short comm; /* Command Register */ 100 u_short pad20; 101 u_short dictrl; /* Diagnostic Control Register */ 102 u_short pad21; 103 u_short clock; /* Diagnostic Clock Register */ 104 u_short pad22; 105 u_short bhdiag; /* Bus Handler Diagnostic Register */ 106 u_short pad23; 107 u_short sidiag; /* SCSI IO Diagnostic Register */ 108 u_short pad24; 109 u_short dmdiag; /* Data Mover Diagnostic Register */ 110 u_short pad25; 111 u_short mcdiag; /* Main Control Diagnostic Register */ 112 u_short pad26; 113 } SIIRegs; 114 115 /* 116 * SC1 - SCSI Control Signals One 117 */ 118 #define SII_SC1_MSK 0x1ff /* All possible signals on the bus */ 119 #define SII_SC1_SEL 0x80 /* SCSI SEL signal active on bus */ 120 #define SII_SC1_ATN 0x08 /* SCSI ATN signal active on bus */ 121 122 /* 123 * SC2 - SCSI Control Signals Two 124 */ 125 #define SII_SC2_IGS 0x8 /* SCSI drivers for initiator mode */ 126 127 /* 128 * CSR - Control/Status Register 129 */ 130 #define SII_HPM 0x10 /* SII in on an arbitrated SCSI bus */ 131 #define SII_RSE 0x08 /* 1 = respond to reselections */ 132 #define SII_SLE 0x04 /* 1 = respond to selections */ 133 #define SII_PCE 0x02 /* 1 = report parity errors */ 134 #define SII_IE 0x01 /* 1 = enable interrupts */ 135 136 /* 137 * ID - Bus ID Register 138 */ 139 #define SII_ID_IO 0x8000 /* I/O */ 140 141 /* 142 * DESTAT - Selection Detector Status Register 143 */ 144 #define SII_IDMSK 0x7 /* ID of target reselected the SII */ 145 146 /* 147 * DMCTRL - DMA Control Register 148 */ 149 #define SII_ASYNC 0x00 /* REQ/ACK Offset for async mode */ 150 #define SII_SYNC 0x03 /* REQ/ACK Offset for sync mode */ 151 152 /* 153 * DMLOTC - DMA Length Of Transfer Counter 154 */ 155 #define SII_TCMSK 0x1fff /* transfer count mask */ 156 157 /* 158 * CSTAT - Connection Status Register 159 */ 160 #define SII_CI 0x8000 /* composite interrupt bit for CSTAT */ 161 #define SII_DI 0x4000 /* composite interrupt bit for DSTAT */ 162 #define SII_RST 0x2000 /* 1 if reset is asserted on SCSI bus */ 163 #define SII_BER 0x1000 /* Bus error */ 164 #define SII_OBC 0x0800 /* Out_en Bit Cleared (DSSI mode) */ 165 #define SII_TZ 0x0400 /* Target pointer Zero (STLP or LTLP is zero) */ 166 #define SII_BUF 0x0200 /* Buffer service - outbound pkt to non-DSSI */ 167 #define SII_LDN 0x0100 /* List element Done */ 168 #define SII_SCH 0x0080 /* State Change */ 169 #define SII_CON 0x0040 /* SII is Connected to another device */ 170 #define SII_DST 0x0020 /* SII was Destination of current transfer */ 171 #define SII_TGT 0x0010 /* SII is operating as a Target */ 172 #define SII_STATE_MSK 0x0070 /* State Mask */ 173 #define SII_SWA 0x0008 /* Selected With Attention */ 174 #define SII_SIP 0x0004 /* Selection In Progress */ 175 #define SII_LST 0x0002 /* Lost arbitration */ 176 177 /* 178 * DSTAT - Data Transfer Status Register 179 */ 180 #define SII_DNE 0x2000 /* DMA transfer Done */ 181 #define SII_TCZ 0x1000 /* Transfer Count register is Zero */ 182 #define SII_TBE 0x0800 /* Transmit Buffer Empty */ 183 #define SII_IBF 0x0400 /* Input Buffer Full */ 184 #define SII_IPE 0x0200 /* Incoming Parity Error */ 185 #define SII_OBB 0x0100 /* Odd Byte Boundary */ 186 #define SII_MIS 0x0010 /* Phase Mismatch */ 187 #define SII_ATN 0x0008 /* ATN set by initiator if in Target mode */ 188 #define SII_MSG 0x0004 /* current bus state of MSG */ 189 #define SII_CD 0x0002 /* current bus state of C/D */ 190 #define SII_IO 0x0001 /* current bus state of I/O */ 191 #define SII_PHASE_MSK 0x0007 /* Phase Mask */ 192 193 /* 194 * The different phases. 195 */ 196 #define SII_MSG_IN_PHASE 0x7 197 #define SII_MSG_OUT_PHASE 0x6 198 #define SII_STATUS_PHASE 0x3 199 #define SII_CMD_PHASE 0x2 200 #define SII_DATA_IN_PHASE 0x1 201 #define SII_DATA_OUT_PHASE 0x0 202 203 /* 204 * COMM - Command Register 205 */ 206 #define SII_DMA 0x8000 /* DMA mode */ 207 #define SII_DO_RST 0x4000 /* Assert reset on SCSI bus for 25 usecs */ 208 #define SII_RSL 0x1000 /* 0 = select, 1 = reselect desired device */ 209 210 /* Commands: I - Initiator, T - Target, D - Disconnected */ 211 #define SII_INXFER 0x0800 /* Information Transfer command (I,T) */ 212 #define SII_SELECT 0x0400 /* Select command (D) */ 213 #define SII_REQDATA 0x0200 /* Request Data command (T) */ 214 #define SII_DISCON 0x0100 /* Disconnect command (I,T,D) */ 215 #define SII_CHRESET 0x0080 /* Chip Reset command (I,T,D) */ 216 217 /* Command state bits same as connection status register */ 218 /* Command phase bits same as data transfer status register */ 219 220 /* 221 * DICTRL - Diagnostic Control Register 222 */ 223 #define SII_PRE 0x4 /* Enable the SII to drive the SCSI bus */ 224 225 #define SII_WAIT_COUNT 10000 /* Delay count used for the SII chip */ 226 /* 227 * Max DMA transfer length for SII 228 * The SII chip only has a 13 bit counter. If 8192 is used as the max count, 229 * you can't tell the difference between a count of zero and 8192. 230 * 8190 is used instead of 8191 so the count is even. 231 */ 232 #define SII_MAX_DMA_XFER_LENGTH 8192 233 234 #endif /* _SII */ 235
Indexes created Sat Sep 20 22:09:52 GMT 2025