1 /* $NetBSD: amdgpu_dm.h,v 1.2 2021/12/18 23:45:00 riastradh Exp $ */ 2 3 /* 4 * Copyright 2015 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __AMDGPU_DM_H__ 29 #define __AMDGPU_DM_H__ 30 31 #include <drm/drm_atomic.h> 32 #include <drm/drm_connector.h> 33 #include <drm/drm_crtc.h> 34 #include <drm/drm_dp_mst_helper.h> 35 #include <drm/drm_plane.h> 36 37 /* 38 * This file contains the definition for amdgpu_display_manager 39 * and its API for amdgpu driver's use. 40 * This component provides all the display related functionality 41 * and this is the only component that calls DAL API. 42 * The API contained here intended for amdgpu driver use. 43 * The API that is called directly from KMS framework is located 44 * in amdgpu_dm_kms.h file 45 */ 46 47 #define AMDGPU_DM_MAX_DISPLAY_INDEX 31 48 /* 49 #include "include/amdgpu_dal_power_if.h" 50 #include "amdgpu_dm_irq.h" 51 */ 52 53 #include "irq_types.h" 54 #include "signal_types.h" 55 #include "amdgpu_dm_crc.h" 56 57 /* Forward declarations */ 58 struct amdgpu_device; 59 struct drm_device; 60 struct amdgpu_dm_irq_handler_data; 61 struct dc; 62 struct amdgpu_bo; 63 struct dmub_srv; 64 65 struct common_irq_params { 66 struct amdgpu_device *adev; 67 enum dc_irq_source irq_src; 68 }; 69 70 /** 71 * struct irq_list_head - Linked-list for low context IRQ handlers. 72 * 73 * @head: The list_head within &struct handler_data 74 * @work: A work_struct containing the deferred handler work 75 */ 76 struct irq_list_head { 77 struct list_head head; 78 /* In case this interrupt needs post-processing, 'work' will be queued*/ 79 struct work_struct work; 80 }; 81 82 /** 83 * struct dm_compressor_info - Buffer info used by frame buffer compression 84 * @cpu_addr: MMIO cpu addr 85 * @bo_ptr: Pointer to the buffer object 86 * @gpu_addr: MMIO gpu addr 87 */ 88 struct dm_comressor_info { 89 void *cpu_addr; 90 struct amdgpu_bo *bo_ptr; 91 uint64_t gpu_addr; 92 }; 93 94 /** 95 * struct amdgpu_dm_backlight_caps - Usable range of backlight values from ACPI 96 * @min_input_signal: minimum possible input in range 0-255 97 * @max_input_signal: maximum possible input in range 0-255 98 * @caps_valid: true if these values are from the ACPI interface 99 */ 100 struct amdgpu_dm_backlight_caps { 101 int min_input_signal; 102 int max_input_signal; 103 bool caps_valid; 104 }; 105 106 /** 107 * struct amdgpu_display_manager - Central amdgpu display manager device 108 * 109 * @dc: Display Core control structure 110 * @adev: AMDGPU base driver structure 111 * @ddev: DRM base driver structure 112 * @display_indexes_num: Max number of display streams supported 113 * @irq_handler_list_table_lock: Synchronizes access to IRQ tables 114 * @backlight_dev: Backlight control device 115 * @backlight_link: Link on which to control backlight 116 * @backlight_caps: Capabilities of the backlight device 117 * @freesync_module: Module handling freesync calculations 118 * @fw_dmcu: Reference to DMCU firmware 119 * @dmcu_fw_version: Version of the DMCU firmware 120 * @soc_bounding_box: SOC bounding box values provided by gpu_info FW 121 * @cached_state: Caches device atomic state for suspend/resume 122 * @compressor: Frame buffer compression buffer. See &struct dm_comressor_info 123 */ 124 struct amdgpu_display_manager { 125 126 struct dc *dc; 127 128 /** 129 * @dmub_srv: 130 * 131 * DMUB service, used for controlling the DMUB on hardware 132 * that supports it. The pointer to the dmub_srv will be 133 * NULL on hardware that does not support it. 134 */ 135 struct dmub_srv *dmub_srv; 136 137 /** 138 * @dmub_fb_info: 139 * 140 * Framebuffer regions for the DMUB. 141 */ 142 struct dmub_srv_fb_info *dmub_fb_info; 143 144 /** 145 * @dmub_fw: 146 * 147 * DMUB firmware, required on hardware that has DMUB support. 148 */ 149 const struct firmware *dmub_fw; 150 151 /** 152 * @dmub_bo: 153 * 154 * Buffer object for the DMUB. 155 */ 156 struct amdgpu_bo *dmub_bo; 157 158 /** 159 * @dmub_bo_gpu_addr: 160 * 161 * GPU virtual address for the DMUB buffer object. 162 */ 163 u64 dmub_bo_gpu_addr; 164 165 /** 166 * @dmub_bo_cpu_addr: 167 * 168 * CPU address for the DMUB buffer object. 169 */ 170 void *dmub_bo_cpu_addr; 171 172 /** 173 * @dmcub_fw_version: 174 * 175 * DMCUB firmware version. 176 */ 177 uint32_t dmcub_fw_version; 178 179 /** 180 * @cgs_device: 181 * 182 * The Common Graphics Services device. It provides an interface for 183 * accessing registers. 184 */ 185 struct cgs_device *cgs_device; 186 187 struct amdgpu_device *adev; 188 struct drm_device *ddev; 189 u16 display_indexes_num; 190 191 /** 192 * @atomic_obj: 193 * 194 * In combination with &dm_atomic_state it helps manage 195 * global atomic state that doesn't map cleanly into existing 196 * drm resources, like &dc_context. 197 */ 198 struct drm_private_obj atomic_obj; 199 200 /** 201 * @dc_lock: 202 * 203 * Guards access to DC functions that can issue register write 204 * sequences. 205 */ 206 struct mutex dc_lock; 207 208 /** 209 * @audio_lock: 210 * 211 * Guards access to audio instance changes. 212 */ 213 struct mutex audio_lock; 214 215 /** 216 * @audio_component: 217 * 218 * Used to notify ELD changes to sound driver. 219 */ 220 struct drm_audio_component *audio_component; 221 222 /** 223 * @audio_registered: 224 * 225 * True if the audio component has been registered 226 * successfully, false otherwise. 227 */ 228 bool audio_registered; 229 230 /** 231 * @irq_handler_list_low_tab: 232 * 233 * Low priority IRQ handler table. 234 * 235 * It is a n*m table consisting of n IRQ sources, and m handlers per IRQ 236 * source. Low priority IRQ handlers are deferred to a workqueue to be 237 * processed. Hence, they can sleep. 238 * 239 * Note that handlers are called in the same order as they were 240 * registered (FIFO). 241 */ 242 struct irq_list_head irq_handler_list_low_tab[DAL_IRQ_SOURCES_NUMBER]; 243 244 /** 245 * @irq_handler_list_high_tab: 246 * 247 * High priority IRQ handler table. 248 * 249 * It is a n*m table, same as &irq_handler_list_low_tab. However, 250 * handlers in this table are not deferred and are called immediately. 251 */ 252 struct list_head irq_handler_list_high_tab[DAL_IRQ_SOURCES_NUMBER]; 253 254 /** 255 * @pflip_params: 256 * 257 * Page flip IRQ parameters, passed to registered handlers when 258 * triggered. 259 */ 260 struct common_irq_params 261 pflip_params[DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1]; 262 263 /** 264 * @vblank_params: 265 * 266 * Vertical blanking IRQ parameters, passed to registered handlers when 267 * triggered. 268 */ 269 struct common_irq_params 270 vblank_params[DC_IRQ_SOURCE_VBLANK6 - DC_IRQ_SOURCE_VBLANK1 + 1]; 271 272 /** 273 * @vupdate_params: 274 * 275 * Vertical update IRQ parameters, passed to registered handlers when 276 * triggered. 277 */ 278 struct common_irq_params 279 vupdate_params[DC_IRQ_SOURCE_VUPDATE6 - DC_IRQ_SOURCE_VUPDATE1 + 1]; 280 281 spinlock_t irq_handler_list_table_lock; 282 283 struct backlight_device *backlight_dev; 284 285 const struct dc_link *backlight_link; 286 struct amdgpu_dm_backlight_caps backlight_caps; 287 288 struct mod_freesync *freesync_module; 289 #ifdef CONFIG_DRM_AMD_DC_HDCP 290 struct hdcp_workqueue *hdcp_workqueue; 291 #endif 292 293 struct drm_atomic_state *cached_state; 294 295 struct dm_comressor_info compressor; 296 297 const struct firmware *fw_dmcu; 298 uint32_t dmcu_fw_version; 299 /** 300 * @soc_bounding_box: 301 * 302 * gpu_info FW provided soc bounding box struct or 0 if not 303 * available in FW 304 */ 305 const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; 306 }; 307 308 struct amdgpu_dm_connector { 309 310 struct drm_connector base; 311 uint32_t connector_id; 312 313 /* we need to mind the EDID between detect 314 and get modes due to analog/digital/tvencoder */ 315 struct edid *edid; 316 317 /* shared with amdgpu */ 318 struct amdgpu_hpd hpd; 319 320 /* number of modes generated from EDID at 'dc_sink' */ 321 int num_modes; 322 323 /* The 'old' sink - before an HPD. 324 * The 'current' sink is in dc_link->sink. */ 325 struct dc_sink *dc_sink; 326 struct dc_link *dc_link; 327 struct dc_sink *dc_em_sink; 328 329 /* DM only */ 330 struct drm_dp_mst_topology_mgr mst_mgr; 331 struct amdgpu_dm_dp_aux dm_dp_aux; 332 struct drm_dp_mst_port *port; 333 struct amdgpu_dm_connector *mst_port; 334 struct amdgpu_encoder *mst_encoder; 335 struct drm_dp_aux *dsc_aux; 336 337 /* TODO see if we can merge with ddc_bus or make a dm_connector */ 338 struct amdgpu_i2c_adapter *i2c; 339 340 /* Monitor range limits */ 341 int min_vfreq ; 342 int max_vfreq ; 343 int pixel_clock_mhz; 344 345 /* Audio instance - protected by audio_lock. */ 346 int audio_inst; 347 348 struct mutex hpd_lock; 349 350 bool fake_enable; 351 #ifdef CONFIG_DEBUG_FS 352 uint32_t debugfs_dpcd_address; 353 uint32_t debugfs_dpcd_size; 354 #endif 355 bool force_yuv420_output; 356 }; 357 358 #define to_amdgpu_dm_connector(x) container_of(x, struct amdgpu_dm_connector, base) 359 360 extern const struct amdgpu_ip_block_version dm_ip_block; 361 362 struct amdgpu_framebuffer; 363 struct amdgpu_display_manager; 364 struct dc_validation_set; 365 struct dc_plane_state; 366 367 struct dm_plane_state { 368 struct drm_plane_state base; 369 struct dc_plane_state *dc_state; 370 }; 371 372 struct dm_crtc_state { 373 struct drm_crtc_state base; 374 struct dc_stream_state *stream; 375 376 bool cm_has_degamma; 377 bool cm_is_degamma_srgb; 378 379 int update_type; 380 int active_planes; 381 bool interrupts_enabled; 382 383 int crc_skip_count; 384 enum amdgpu_dm_pipe_crc_source crc_src; 385 386 bool freesync_timing_changed; 387 bool freesync_vrr_info_changed; 388 389 bool vrr_supported; 390 struct mod_freesync_config freesync_config; 391 struct mod_vrr_params vrr_params; 392 struct dc_info_packet vrr_infopacket; 393 394 int abm_level; 395 }; 396 397 #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) 398 399 struct dm_atomic_state { 400 struct drm_private_state base; 401 402 struct dc_state *context; 403 }; 404 405 #define to_dm_atomic_state(x) container_of(x, struct dm_atomic_state, base) 406 407 struct dm_connector_state { 408 struct drm_connector_state base; 409 410 enum amdgpu_rmx_type scaling; 411 uint8_t underscan_vborder; 412 uint8_t underscan_hborder; 413 bool underscan_enable; 414 bool freesync_capable; 415 uint8_t abm_level; 416 int vcpi_slots; 417 uint64_t pbn; 418 }; 419 420 #define to_dm_connector_state(x)\ 421 container_of((x), struct dm_connector_state, base) 422 423 void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector); 424 struct drm_connector_state * 425 amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector); 426 int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, 427 struct drm_connector_state *state, 428 struct drm_property *property, 429 uint64_t val); 430 431 int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, 432 const struct drm_connector_state *state, 433 struct drm_property *property, 434 uint64_t *val); 435 436 int amdgpu_dm_get_encoder_crtc_mask(struct amdgpu_device *adev); 437 438 void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, 439 struct amdgpu_dm_connector *aconnector, 440 int connector_type, 441 struct dc_link *link, 442 int link_index); 443 444 enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector, 445 struct drm_display_mode *mode); 446 447 void dm_restore_drm_connector_state(struct drm_device *dev, 448 struct drm_connector *connector); 449 450 void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, 451 struct edid *edid); 452 453 #define MAX_COLOR_LUT_ENTRIES 4096 454 /* Legacy gamm LUT users such as X doesn't like large LUT sizes */ 455 #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 456 457 void amdgpu_dm_init_color_mod(void); 458 int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); 459 int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, 460 struct dc_plane_state *dc_plane_state); 461 462 extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; 463 464 #endif /* __AMDGPU_DM_H__ */ 465
Indexes created Sat Sep 20 22:09:52 GMT 2025