| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| Makefile | 53 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_lib.o := $(dml_ccflags)
56 CFLAGS_$(AMDDALPATH)/dc/dml/display_mode_vba.o := $(dml_ccflags)
57 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20.o := $(dml_ccflags)
58 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20.o := $(dml_ccflags)
59 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_mode_vba_20v2.o := $(dml_ccflags)
60 CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
61 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
62 CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
64 CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
65 CFLAGS_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_ccflags
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/ |
| amdgpu_dcn_calcs.c | 40 #include "dml/dml1_display_rq_dlg_calc.h"
449 struct display_mode_lib *dml = (struct display_mode_lib *)__UNCONST(&dc->dml); local in function:dcn_bw_calc_rq_dlg_ttu
488 // dc->dml.logger = pool->base.logger;
496 dml1_rq_dlg_get_rq_params(dml, &rq_param, input.pipe.src);
497 dml1_extract_rq_regs(dml, rq_regs, rq_param);
499 dml,
1052 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
1053 context->bw_ctx.dml.soc.sr_exit_time_us = v->sr_exit_time;
1268 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/ |
| amdgpu_dc.c | 733 /* Creation of current_state must occur after dc->dml
735 * on creation it copies the contents of dc->dml
1363 * initialize and obtain IP and SOC the base DML instance from DC is
1367 memcpy(&context->bw_ctx.dml, &dc->dml, sizeof(struct display_mode_lib));
1549 * and DML calculation
1572 * thus need to run DML to calculate RQ settings
2470 struct display_mode_lib *dml; local in function:dc_set_power_state
2493 dml = kzalloc(sizeof(struct display_mode_lib),
2496 ASSERT(dml);
[all...] |
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/ |
| amdgpu_dcn10_resource.c | 1428 dml_init_instance(&dc->dml, &dcn1_0_soc, &dcn1_0_ip, DML_PROJECT_RAVEN1);
1435 struct display_mode_lib *dml = &dc->dml; local in function:dcn10_resource_construct
1437 dml->ip.max_num_dpp = 3;
1565 /* within dml lib, it is hard code to 4. If ASIC pipe is fused,
1568 dc->dml.ip.max_num_dpp = pool->base.pipe_count;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| core_types.h | 350 struct display_mode_lib dml; member in struct:bw_context
358 * @bw_ctx: The output from bandwidth and watermark calculations and the DML
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| dc.h | 42 #include "dml/display_mode_lib.h"
476 * for DML. Unlike the debug option for forcing
514 struct display_mode_lib dml; member in struct:dc
|
