1 /* $NetBSD: amdgpu_display_rq_dlg_calc_20v2.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $ */ 2 3 /* 4 * Copyright 2018 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_display_rq_dlg_calc_20v2.c,v 1.2 2021/12/18 23:45:04 riastradh Exp $"); 30 31 #include "../display_mode_lib.h" 32 #include "../display_mode_vba.h" 33 #include "display_rq_dlg_calc_20v2.h" 34 35 // Function: dml20v2_rq_dlg_get_rq_params 36 // Calculate requestor related parameters that register definition agnostic 37 // (i.e. this layer does try to separate real values from register definition) 38 // Input: 39 // pipe_src_param - pipe source configuration (e.g. vp, pitch, etc.) 40 // Output: 41 // rq_param - values that can be used to setup RQ (e.g. swath_height, plane1_addr, etc.) 42 // 43 static void dml20v2_rq_dlg_get_rq_params( 44 struct display_mode_lib *mode_lib, 45 display_rq_params_st * rq_param, 46 const display_pipe_source_params_st pipe_src_param); 47 48 // Function: dml20v2_rq_dlg_get_dlg_params 49 // Calculate deadline related parameters 50 // 51 static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 52 const display_e2e_pipe_params_st *e2e_pipe_param, 53 const unsigned int num_pipes, 54 const unsigned int pipe_idx, 55 display_dlg_regs_st *disp_dlg_regs, 56 display_ttu_regs_st *disp_ttu_regs, 57 const display_rq_dlg_params_st rq_dlg_param, 58 const display_dlg_sys_params_st dlg_sys_param, 59 const bool cstate_en, 60 const bool pstate_en); 61 /* 62 * NOTE: 63 * This file is gcc-parseable HW gospel, coming straight from HW engineers. 64 * 65 * It doesn't adhere to Linux kernel style and sometimes will do things in odd 66 * ways. Unless there is something clearly wrong with it the code should 67 * remain as-is as it provides us with a guarantee from HW that it is correct. 68 */ 69 70 static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, 71 double *refcyc_per_req_delivery_pre_cur, 72 double *refcyc_per_req_delivery_cur, 73 double refclk_freq_in_mhz, 74 double ref_freq_to_pix_freq, 75 double hscale_pixel_rate_l, 76 double hscl_ratio, 77 double vratio_pre_l, 78 double vratio_l, 79 unsigned int cur_width, 80 enum cursor_bpp cur_bpp); 81 82 #include "../dml_inline_defs.h" 83 84 static unsigned int get_bytes_per_element(enum source_format_class source_format, bool is_chroma) 85 { 86 unsigned int ret_val = 0; 87 88 if (source_format == dm_444_16) { 89 if (!is_chroma) 90 ret_val = 2; 91 } else if (source_format == dm_444_32) { 92 if (!is_chroma) 93 ret_val = 4; 94 } else if (source_format == dm_444_64) { 95 if (!is_chroma) 96 ret_val = 8; 97 } else if (source_format == dm_420_8) { 98 if (is_chroma) 99 ret_val = 2; 100 else 101 ret_val = 1; 102 } else if (source_format == dm_420_10) { 103 if (is_chroma) 104 ret_val = 4; 105 else 106 ret_val = 2; 107 } else if (source_format == dm_444_8) { 108 ret_val = 1; 109 } 110 return ret_val; 111 } 112 113 static bool is_dual_plane(enum source_format_class source_format) 114 { 115 bool ret_val = false; 116 117 if ((source_format == dm_420_8) || (source_format == dm_420_10)) 118 ret_val = true; 119 120 return ret_val; 121 } 122 123 static double get_refcyc_per_delivery(struct display_mode_lib *mode_lib, 124 double refclk_freq_in_mhz, 125 double pclk_freq_in_mhz, 126 bool odm_combine, 127 unsigned int recout_width, 128 unsigned int hactive, 129 double vratio, 130 double hscale_pixel_rate, 131 unsigned int delivery_width, 132 unsigned int req_per_swath_ub) 133 { 134 double refcyc_per_delivery = 0.0; 135 136 if (vratio <= 1.0) { 137 if (odm_combine) 138 refcyc_per_delivery = (double) refclk_freq_in_mhz 139 * dml_min((double) recout_width, (double) hactive / 2.0) 140 / pclk_freq_in_mhz / (double) req_per_swath_ub; 141 else 142 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) recout_width 143 / pclk_freq_in_mhz / (double) req_per_swath_ub; 144 } else { 145 refcyc_per_delivery = (double) refclk_freq_in_mhz * (double) delivery_width 146 / (double) hscale_pixel_rate / (double) req_per_swath_ub; 147 } 148 149 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 150 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 151 dml_print("DML_DLG: %s: recout_width = %d\n", __func__, recout_width); 152 dml_print("DML_DLG: %s: vratio = %3.2f\n", __func__, vratio); 153 dml_print("DML_DLG: %s: req_per_swath_ub = %d\n", __func__, req_per_swath_ub); 154 dml_print("DML_DLG: %s: refcyc_per_delivery= %3.2f\n", __func__, refcyc_per_delivery); 155 156 return refcyc_per_delivery; 157 158 } 159 160 static unsigned int get_blk_size_bytes(const enum source_macro_tile_size tile_size) 161 { 162 if (tile_size == dm_256k_tile) 163 return (256 * 1024); 164 else if (tile_size == dm_64k_tile) 165 return (64 * 1024); 166 else 167 return (4 * 1024); 168 } 169 170 static void extract_rq_sizing_regs(struct display_mode_lib *mode_lib, 171 display_data_rq_regs_st *rq_regs, 172 const display_data_rq_sizing_params_st rq_sizing) 173 { 174 dml_print("DML_DLG: %s: rq_sizing param\n", __func__); 175 print__data_rq_sizing_params_st(mode_lib, rq_sizing); 176 177 rq_regs->chunk_size = dml_log2(rq_sizing.chunk_bytes) - 10; 178 179 if (rq_sizing.min_chunk_bytes == 0) 180 rq_regs->min_chunk_size = 0; 181 else 182 rq_regs->min_chunk_size = dml_log2(rq_sizing.min_chunk_bytes) - 8 + 1; 183 184 rq_regs->meta_chunk_size = dml_log2(rq_sizing.meta_chunk_bytes) - 10; 185 if (rq_sizing.min_meta_chunk_bytes == 0) 186 rq_regs->min_meta_chunk_size = 0; 187 else 188 rq_regs->min_meta_chunk_size = dml_log2(rq_sizing.min_meta_chunk_bytes) - 6 + 1; 189 190 rq_regs->dpte_group_size = dml_log2(rq_sizing.dpte_group_bytes) - 6; 191 rq_regs->mpte_group_size = dml_log2(rq_sizing.mpte_group_bytes) - 6; 192 } 193 194 static void extract_rq_regs(struct display_mode_lib *mode_lib, 195 display_rq_regs_st *rq_regs, 196 const display_rq_params_st rq_param) 197 { 198 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 199 unsigned int detile_buf_plane1_addr = 0; 200 201 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_l), rq_param.sizing.rq_l); 202 203 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height), 204 1) - 3; 205 206 if (rq_param.yuv420) { 207 extract_rq_sizing_regs(mode_lib, &(rq_regs->rq_regs_c), rq_param.sizing.rq_c); 208 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height), 209 1) - 3; 210 } 211 212 rq_regs->rq_regs_l.swath_height = dml_log2(rq_param.dlg.rq_l.swath_height); 213 rq_regs->rq_regs_c.swath_height = dml_log2(rq_param.dlg.rq_c.swath_height); 214 215 // TODO: take the max between luma, chroma chunk size? 216 // okay for now, as we are setting chunk_bytes to 8kb anyways 217 if (rq_param.sizing.rq_l.chunk_bytes >= 32 * 1024) { //32kb 218 rq_regs->drq_expansion_mode = 0; 219 } else { 220 rq_regs->drq_expansion_mode = 2; 221 } 222 rq_regs->prq_expansion_mode = 1; 223 rq_regs->mrq_expansion_mode = 1; 224 rq_regs->crq_expansion_mode = 1; 225 226 if (rq_param.yuv420) { 227 if ((double) rq_param.misc.rq_l.stored_swath_bytes 228 / (double) rq_param.misc.rq_c.stored_swath_bytes <= 1.5) { 229 detile_buf_plane1_addr = (detile_buf_size_in_bytes / 2.0 / 64.0); // half to chroma 230 } else { 231 detile_buf_plane1_addr = dml_round_to_multiple((unsigned int) ((2.0 * detile_buf_size_in_bytes) / 3.0), 232 256, 233 0) / 64.0; // 2/3 to chroma 234 } 235 } 236 rq_regs->plane1_base_address = detile_buf_plane1_addr; 237 } 238 239 static void handle_det_buf_split(struct display_mode_lib *mode_lib, 240 display_rq_params_st *rq_param, 241 const display_pipe_source_params_st pipe_src_param) 242 { 243 unsigned int total_swath_bytes = 0; 244 unsigned int swath_bytes_l = 0; 245 unsigned int swath_bytes_c = 0; 246 unsigned int full_swath_bytes_packed_l = 0; 247 unsigned int full_swath_bytes_packed_c = 0; 248 bool req128_l = false; 249 bool req128_c = false; 250 bool surf_linear = (pipe_src_param.sw_mode == dm_sw_linear); 251 bool surf_vert = (pipe_src_param.source_scan == dm_vert); 252 unsigned int log2_swath_height_l = 0; 253 unsigned int log2_swath_height_c = 0; 254 unsigned int detile_buf_size_in_bytes = mode_lib->ip.det_buffer_size_kbytes * 1024; 255 256 full_swath_bytes_packed_l = rq_param->misc.rq_l.full_swath_bytes; 257 full_swath_bytes_packed_c = rq_param->misc.rq_c.full_swath_bytes; 258 259 if (rq_param->yuv420_10bpc) { 260 full_swath_bytes_packed_l = dml_round_to_multiple(rq_param->misc.rq_l.full_swath_bytes * 2 / 3, 261 256, 262 1) + 256; 263 full_swath_bytes_packed_c = dml_round_to_multiple(rq_param->misc.rq_c.full_swath_bytes * 2 / 3, 264 256, 265 1) + 256; 266 } 267 268 if (rq_param->yuv420) { 269 total_swath_bytes = 2 * full_swath_bytes_packed_l + 2 * full_swath_bytes_packed_c; 270 271 if (total_swath_bytes <= detile_buf_size_in_bytes) { //full 256b request 272 req128_l = false; 273 req128_c = false; 274 swath_bytes_l = full_swath_bytes_packed_l; 275 swath_bytes_c = full_swath_bytes_packed_c; 276 } else { //128b request (for luma only for yuv420 8bpc) 277 req128_l = true; 278 req128_c = false; 279 swath_bytes_l = full_swath_bytes_packed_l / 2; 280 swath_bytes_c = full_swath_bytes_packed_c; 281 } 282 // Note: assumption, the config that pass in will fit into 283 // the detiled buffer. 284 } else { 285 total_swath_bytes = 2 * full_swath_bytes_packed_l; 286 287 if (total_swath_bytes <= detile_buf_size_in_bytes) 288 req128_l = false; 289 else 290 req128_l = true; 291 292 swath_bytes_l = total_swath_bytes; 293 swath_bytes_c = 0; 294 } 295 rq_param->misc.rq_l.stored_swath_bytes = swath_bytes_l; 296 rq_param->misc.rq_c.stored_swath_bytes = swath_bytes_c; 297 298 if (surf_linear) { 299 log2_swath_height_l = 0; 300 log2_swath_height_c = 0; 301 } else if (!surf_vert) { 302 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_height) - req128_l; 303 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_height) - req128_c; 304 } else { 305 log2_swath_height_l = dml_log2(rq_param->misc.rq_l.blk256_width) - req128_l; 306 log2_swath_height_c = dml_log2(rq_param->misc.rq_c.blk256_width) - req128_c; 307 } 308 rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; 309 rq_param->dlg.rq_c.swath_height = 1 << log2_swath_height_c; 310 311 dml_print("DML_DLG: %s: req128_l = %0d\n", __func__, req128_l); 312 dml_print("DML_DLG: %s: req128_c = %0d\n", __func__, req128_c); 313 dml_print("DML_DLG: %s: full_swath_bytes_packed_l = %0d\n", 314 __func__, 315 full_swath_bytes_packed_l); 316 dml_print("DML_DLG: %s: full_swath_bytes_packed_c = %0d\n", 317 __func__, 318 full_swath_bytes_packed_c); 319 } 320 321 static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, 322 display_data_rq_dlg_params_st *rq_dlg_param, 323 display_data_rq_misc_params_st *rq_misc_param, 324 display_data_rq_sizing_params_st *rq_sizing_param, 325 unsigned int vp_width, 326 unsigned int vp_height, 327 unsigned int data_pitch, 328 unsigned int meta_pitch, 329 unsigned int source_format, 330 unsigned int tiling, 331 unsigned int macro_tile_size, 332 unsigned int source_scan, 333 unsigned int is_chroma) 334 { 335 bool surf_linear = (tiling == dm_sw_linear); 336 bool surf_vert = (source_scan == dm_vert); 337 338 unsigned int bytes_per_element; 339 unsigned int bytes_per_element_y = get_bytes_per_element((enum source_format_class)(source_format), 340 false); 341 unsigned int bytes_per_element_c = get_bytes_per_element((enum source_format_class)(source_format), 342 true); 343 344 unsigned int blk256_width = 0; 345 unsigned int blk256_height = 0; 346 347 unsigned int blk256_width_y = 0; 348 unsigned int blk256_height_y = 0; 349 unsigned int blk256_width_c = 0; 350 unsigned int blk256_height_c = 0; 351 unsigned int log2_bytes_per_element; 352 unsigned int log2_blk256_width; 353 unsigned int log2_blk256_height; 354 unsigned int blk_bytes; 355 unsigned int log2_blk_bytes; 356 unsigned int log2_blk_height; 357 unsigned int log2_blk_width; 358 unsigned int log2_meta_req_bytes; 359 unsigned int log2_meta_req_height; 360 unsigned int log2_meta_req_width; 361 unsigned int meta_req_width; 362 unsigned int meta_req_height; 363 unsigned int log2_meta_row_height; 364 unsigned int meta_row_width_ub; 365 unsigned int log2_meta_chunk_bytes; 366 unsigned int log2_meta_chunk_height; 367 368 //full sized meta chunk width in unit of data elements 369 unsigned int log2_meta_chunk_width; 370 unsigned int log2_min_meta_chunk_bytes; 371 unsigned int min_meta_chunk_width; 372 unsigned int meta_chunk_width; 373 unsigned int meta_chunk_per_row_int; 374 unsigned int meta_row_remainder; 375 unsigned int meta_chunk_threshold; 376 unsigned int meta_blk_bytes; 377 unsigned int meta_blk_height; 378 unsigned int meta_blk_width; 379 unsigned int meta_surface_bytes; 380 unsigned int vmpg_bytes; 381 unsigned int meta_pte_req_per_frame_ub; 382 unsigned int meta_pte_bytes_per_frame_ub; 383 const unsigned int log2_vmpg_bytes = dml_log2(mode_lib->soc.vmm_page_size_bytes); 384 const unsigned int dpte_buf_in_pte_reqs = mode_lib->ip.dpte_buffer_size_in_pte_reqs_luma; 385 const unsigned int pde_proc_buffer_size_64k_reqs = 386 mode_lib->ip.pde_proc_buffer_size_64k_reqs; 387 388 unsigned int log2_vmpg_height = 0; 389 unsigned int log2_vmpg_width = 0; 390 unsigned int log2_dpte_req_height_ptes = 0; 391 unsigned int log2_dpte_req_height = 0; 392 unsigned int log2_dpte_req_width = 0; 393 unsigned int log2_dpte_row_height_linear = 0; 394 unsigned int log2_dpte_row_height = 0; 395 unsigned int log2_dpte_group_width = 0; 396 unsigned int dpte_row_width_ub = 0; 397 unsigned int dpte_req_height = 0; 398 unsigned int dpte_req_width = 0; 399 unsigned int dpte_group_width = 0; 400 unsigned int log2_dpte_group_bytes = 0; 401 unsigned int log2_dpte_group_length = 0; 402 unsigned int pde_buf_entries; 403 bool yuv420 = (source_format == dm_420_8 || source_format == dm_420_10); 404 405 Calculate256BBlockSizes((enum source_format_class)(source_format), 406 (enum dm_swizzle_mode)(tiling), 407 bytes_per_element_y, 408 bytes_per_element_c, 409 &blk256_height_y, 410 &blk256_height_c, 411 &blk256_width_y, 412 &blk256_width_c); 413 414 if (!is_chroma) { 415 blk256_width = blk256_width_y; 416 blk256_height = blk256_height_y; 417 bytes_per_element = bytes_per_element_y; 418 } else { 419 blk256_width = blk256_width_c; 420 blk256_height = blk256_height_c; 421 bytes_per_element = bytes_per_element_c; 422 } 423 424 log2_bytes_per_element = dml_log2(bytes_per_element); 425 426 dml_print("DML_DLG: %s: surf_linear = %d\n", __func__, surf_linear); 427 dml_print("DML_DLG: %s: surf_vert = %d\n", __func__, surf_vert); 428 dml_print("DML_DLG: %s: blk256_width = %d\n", __func__, blk256_width); 429 dml_print("DML_DLG: %s: blk256_height = %d\n", __func__, blk256_height); 430 431 log2_blk256_width = dml_log2((double) blk256_width); 432 log2_blk256_height = dml_log2((double) blk256_height); 433 blk_bytes = surf_linear ? 434 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); 435 log2_blk_bytes = dml_log2((double) blk_bytes); 436 log2_blk_height = 0; 437 log2_blk_width = 0; 438 439 // remember log rule 440 // "+" in log is multiply 441 // "-" in log is divide 442 // "/2" is like square root 443 // blk is vertical biased 444 if (tiling != dm_sw_linear) 445 log2_blk_height = log2_blk256_height 446 + dml_ceil((double) (log2_blk_bytes - 8) / 2.0, 1); 447 else 448 log2_blk_height = 0; // blk height of 1 449 450 log2_blk_width = log2_blk_bytes - log2_bytes_per_element - log2_blk_height; 451 452 if (!surf_vert) { 453 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_width - 1, blk256_width, 1) 454 + blk256_width; 455 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_width; 456 } else { 457 rq_dlg_param->swath_width_ub = dml_round_to_multiple(vp_height - 1, blk256_height, 1) 458 + blk256_height; 459 rq_dlg_param->req_per_swath_ub = rq_dlg_param->swath_width_ub >> log2_blk256_height; 460 } 461 462 if (!surf_vert) 463 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_height 464 * bytes_per_element; 465 else 466 rq_misc_param->full_swath_bytes = rq_dlg_param->swath_width_ub * blk256_width 467 * bytes_per_element; 468 469 rq_misc_param->blk256_height = blk256_height; 470 rq_misc_param->blk256_width = blk256_width; 471 472 // ------- 473 // meta 474 // ------- 475 log2_meta_req_bytes = 6; // meta request is 64b and is 8x8byte meta element 476 477 // each 64b meta request for dcn is 8x8 meta elements and 478 // a meta element covers one 256b block of the the data surface. 479 log2_meta_req_height = log2_blk256_height + 3; // meta req is 8x8 byte, each byte represent 1 blk256 480 log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element 481 - log2_meta_req_height; 482 meta_req_width = 1 << log2_meta_req_width; 483 meta_req_height = 1 << log2_meta_req_height; 484 log2_meta_row_height = 0; 485 meta_row_width_ub = 0; 486 487 // the dimensions of a meta row are meta_row_width x meta_row_height in elements. 488 // calculate upper bound of the meta_row_width 489 if (!surf_vert) { 490 log2_meta_row_height = log2_meta_req_height; 491 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) 492 + meta_req_width; 493 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; 494 } else { 495 log2_meta_row_height = log2_meta_req_width; 496 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) 497 + meta_req_height; 498 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; 499 } 500 rq_dlg_param->meta_bytes_per_row_ub = rq_dlg_param->meta_req_per_row_ub * 64; 501 502 rq_dlg_param->meta_row_height = 1 << log2_meta_row_height; 503 504 log2_meta_chunk_bytes = dml_log2(rq_sizing_param->meta_chunk_bytes); 505 log2_meta_chunk_height = log2_meta_row_height; 506 507 //full sized meta chunk width in unit of data elements 508 log2_meta_chunk_width = log2_meta_chunk_bytes + 8 - log2_bytes_per_element 509 - log2_meta_chunk_height; 510 log2_min_meta_chunk_bytes = dml_log2(rq_sizing_param->min_meta_chunk_bytes); 511 min_meta_chunk_width = 1 512 << (log2_min_meta_chunk_bytes + 8 - log2_bytes_per_element 513 - log2_meta_chunk_height); 514 meta_chunk_width = 1 << log2_meta_chunk_width; 515 meta_chunk_per_row_int = (unsigned int) (meta_row_width_ub / meta_chunk_width); 516 meta_row_remainder = meta_row_width_ub % meta_chunk_width; 517 meta_chunk_threshold = 0; 518 meta_blk_bytes = 4096; 519 meta_blk_height = blk256_height * 64; 520 meta_blk_width = meta_blk_bytes * 256 / bytes_per_element / meta_blk_height; 521 meta_surface_bytes = meta_pitch 522 * (dml_round_to_multiple(vp_height - 1, meta_blk_height, 1) + meta_blk_height) 523 * bytes_per_element / 256; 524 vmpg_bytes = mode_lib->soc.vmm_page_size_bytes; 525 meta_pte_req_per_frame_ub = (dml_round_to_multiple(meta_surface_bytes - vmpg_bytes, 526 8 * vmpg_bytes, 527 1) + 8 * vmpg_bytes) / (8 * vmpg_bytes); 528 meta_pte_bytes_per_frame_ub = meta_pte_req_per_frame_ub * 64; //64B mpte request 529 rq_dlg_param->meta_pte_bytes_per_frame_ub = meta_pte_bytes_per_frame_ub; 530 531 dml_print("DML_DLG: %s: meta_blk_height = %d\n", __func__, meta_blk_height); 532 dml_print("DML_DLG: %s: meta_blk_width = %d\n", __func__, meta_blk_width); 533 dml_print("DML_DLG: %s: meta_surface_bytes = %d\n", __func__, meta_surface_bytes); 534 dml_print("DML_DLG: %s: meta_pte_req_per_frame_ub = %d\n", 535 __func__, 536 meta_pte_req_per_frame_ub); 537 dml_print("DML_DLG: %s: meta_pte_bytes_per_frame_ub = %d\n", 538 __func__, 539 meta_pte_bytes_per_frame_ub); 540 541 if (!surf_vert) 542 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; 543 else 544 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; 545 546 if (meta_row_remainder <= meta_chunk_threshold) 547 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 1; 548 else 549 rq_dlg_param->meta_chunks_per_row_ub = meta_chunk_per_row_int + 2; 550 551 // ------ 552 // dpte 553 // ------ 554 if (surf_linear) { 555 log2_vmpg_height = 0; // one line high 556 } else { 557 log2_vmpg_height = (log2_vmpg_bytes - 8) / 2 + log2_blk256_height; 558 } 559 log2_vmpg_width = log2_vmpg_bytes - log2_bytes_per_element - log2_vmpg_height; 560 561 // only 3 possible shapes for dpte request in dimensions of ptes: 8x1, 4x2, 2x4. 562 if (surf_linear) { //one 64B PTE request returns 8 PTEs 563 log2_dpte_req_height_ptes = 0; 564 log2_dpte_req_width = log2_vmpg_width + 3; 565 log2_dpte_req_height = 0; 566 } else if (log2_blk_bytes == 12) { //4KB tile means 4kB page size 567 //one 64B req gives 8x1 PTEs for 4KB tile 568 log2_dpte_req_height_ptes = 0; 569 log2_dpte_req_width = log2_blk_width + 3; 570 log2_dpte_req_height = log2_blk_height + 0; 571 } else if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) { // tile block >= 64KB 572 //two 64B reqs of 2x4 PTEs give 16 PTEs to cover 64KB 573 log2_dpte_req_height_ptes = 4; 574 log2_dpte_req_width = log2_blk256_width + 4; // log2_64KB_width 575 log2_dpte_req_height = log2_blk256_height + 4; // log2_64KB_height 576 } else { //64KB page size and must 64KB tile block 577 //one 64B req gives 8x1 PTEs for 64KB tile 578 log2_dpte_req_height_ptes = 0; 579 log2_dpte_req_width = log2_blk_width + 3; 580 log2_dpte_req_height = log2_blk_height + 0; 581 } 582 583 // The dpte request dimensions in data elements is dpte_req_width x dpte_req_height 584 // log2_vmpg_width is how much 1 pte represent, now calculating how much a 64b pte req represent 585 // That depends on the pte shape (i.e. 8x1, 4x2, 2x4) 586 //log2_dpte_req_height = log2_vmpg_height + log2_dpte_req_height_ptes; 587 //log2_dpte_req_width = log2_vmpg_width + log2_dpte_req_width_ptes; 588 dpte_req_height = 1 << log2_dpte_req_height; 589 dpte_req_width = 1 << log2_dpte_req_width; 590 591 // calculate pitch dpte row buffer can hold 592 // round the result down to a power of two. 593 pde_buf_entries = yuv420 ? (pde_proc_buffer_size_64k_reqs >> 1) : pde_proc_buffer_size_64k_reqs; 594 if (surf_linear) { 595 unsigned int dpte_row_height; 596 597 log2_dpte_row_height_linear = dml_floor(dml_log2(dml_min(64 * 1024 * pde_buf_entries 598 / bytes_per_element, 599 dpte_buf_in_pte_reqs 600 * dpte_req_width) 601 / data_pitch), 602 1); 603 604 ASSERT(log2_dpte_row_height_linear >= 3); 605 606 if (log2_dpte_row_height_linear > 7) 607 log2_dpte_row_height_linear = 7; 608 609 log2_dpte_row_height = log2_dpte_row_height_linear; 610 // For linear, the dpte row is pitch dependent and the pte requests wrap at the pitch boundary. 611 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering. 612 dpte_row_height = 1 << log2_dpte_row_height; 613 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1, 614 dpte_req_width, 615 1) + dpte_req_width; 616 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 617 } else { 618 // the upper bound of the dpte_row_width without dependency on viewport position follows. 619 // for tiled mode, row height is the same as req height and row store up to vp size upper bound 620 if (!surf_vert) { 621 log2_dpte_row_height = log2_dpte_req_height; 622 dpte_row_width_ub = dml_round_to_multiple(vp_width - 1, dpte_req_width, 1) 623 + dpte_req_width; 624 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_width; 625 } else { 626 log2_dpte_row_height = 627 (log2_blk_width < log2_dpte_req_width) ? 628 log2_blk_width : log2_dpte_req_width; 629 dpte_row_width_ub = dml_round_to_multiple(vp_height - 1, dpte_req_height, 1) 630 + dpte_req_height; 631 rq_dlg_param->dpte_req_per_row_ub = dpte_row_width_ub / dpte_req_height; 632 } 633 } 634 if (log2_blk_bytes >= 16 && log2_vmpg_bytes == 12) // tile block >= 64KB 635 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 128; //2*64B dpte request 636 else 637 rq_dlg_param->dpte_bytes_per_row_ub = rq_dlg_param->dpte_req_per_row_ub * 64; //64B dpte request 638 639 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height; 640 641 // the dpte_group_bytes is reduced for the specific case of vertical 642 // access of a tile surface that has dpte request of 8x1 ptes. 643 if (!surf_linear & (log2_dpte_req_height_ptes == 0) & surf_vert) //reduced, in this case, will have page fault within a group 644 rq_sizing_param->dpte_group_bytes = 512; 645 else 646 //full size 647 rq_sizing_param->dpte_group_bytes = 2048; 648 649 //since pte request size is 64byte, the number of data pte requests per full sized group is as follows. 650 log2_dpte_group_bytes = dml_log2(rq_sizing_param->dpte_group_bytes); 651 log2_dpte_group_length = log2_dpte_group_bytes - 6; //length in 64b requests 652 653 // full sized data pte group width in elements 654 if (!surf_vert) 655 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_width; 656 else 657 log2_dpte_group_width = log2_dpte_group_length + log2_dpte_req_height; 658 659 //But if the tile block >=64KB and the page size is 4KB, then each dPTE request is 2*64B 660 if ((log2_blk_bytes >= 16) && (log2_vmpg_bytes == 12)) // tile block >= 64KB 661 log2_dpte_group_width = log2_dpte_group_width - 1; 662 663 dpte_group_width = 1 << log2_dpte_group_width; 664 665 // since dpte groups are only aligned to dpte_req_width and not dpte_group_width, 666 // the upper bound for the dpte groups per row is as follows. 667 rq_dlg_param->dpte_groups_per_row_ub = dml_ceil((double) dpte_row_width_ub / dpte_group_width, 668 1); 669 } 670 671 static void get_surf_rq_param(struct display_mode_lib *mode_lib, 672 display_data_rq_sizing_params_st *rq_sizing_param, 673 display_data_rq_dlg_params_st *rq_dlg_param, 674 display_data_rq_misc_params_st *rq_misc_param, 675 const display_pipe_source_params_st pipe_src_param, 676 bool is_chroma) 677 { 678 bool mode_422 = false; 679 unsigned int vp_width = 0; 680 unsigned int vp_height = 0; 681 unsigned int data_pitch = 0; 682 unsigned int meta_pitch = 0; 683 unsigned int ppe = mode_422 ? 2 : 1; 684 685 // TODO check if ppe apply for both luma and chroma in 422 case 686 if (is_chroma) { 687 vp_width = pipe_src_param.viewport_width_c / ppe; 688 vp_height = pipe_src_param.viewport_height_c; 689 data_pitch = pipe_src_param.data_pitch_c; 690 meta_pitch = pipe_src_param.meta_pitch_c; 691 } else { 692 vp_width = pipe_src_param.viewport_width / ppe; 693 vp_height = pipe_src_param.viewport_height; 694 data_pitch = pipe_src_param.data_pitch; 695 meta_pitch = pipe_src_param.meta_pitch; 696 } 697 698 rq_sizing_param->chunk_bytes = 8192; 699 700 if (rq_sizing_param->chunk_bytes == 64 * 1024) 701 rq_sizing_param->min_chunk_bytes = 0; 702 else 703 rq_sizing_param->min_chunk_bytes = 1024; 704 705 rq_sizing_param->meta_chunk_bytes = 2048; 706 rq_sizing_param->min_meta_chunk_bytes = 256; 707 708 rq_sizing_param->mpte_group_bytes = 2048; 709 710 get_meta_and_pte_attr(mode_lib, 711 rq_dlg_param, 712 rq_misc_param, 713 rq_sizing_param, 714 vp_width, 715 vp_height, 716 data_pitch, 717 meta_pitch, 718 pipe_src_param.source_format, 719 pipe_src_param.sw_mode, 720 pipe_src_param.macro_tile_size, 721 pipe_src_param.source_scan, 722 is_chroma); 723 } 724 725 static void dml20v2_rq_dlg_get_rq_params(struct display_mode_lib *mode_lib, 726 display_rq_params_st *rq_param, 727 const display_pipe_source_params_st pipe_src_param) 728 { 729 // get param for luma surface 730 rq_param->yuv420 = pipe_src_param.source_format == dm_420_8 731 || pipe_src_param.source_format == dm_420_10; 732 rq_param->yuv420_10bpc = pipe_src_param.source_format == dm_420_10; 733 734 get_surf_rq_param(mode_lib, 735 &(rq_param->sizing.rq_l), 736 &(rq_param->dlg.rq_l), 737 &(rq_param->misc.rq_l), 738 pipe_src_param, 739 0); 740 741 if (is_dual_plane((enum source_format_class)(pipe_src_param.source_format))) { 742 // get param for chroma surface 743 get_surf_rq_param(mode_lib, 744 &(rq_param->sizing.rq_c), 745 &(rq_param->dlg.rq_c), 746 &(rq_param->misc.rq_c), 747 pipe_src_param, 748 1); 749 } 750 751 // calculate how to split the det buffer space between luma and chroma 752 handle_det_buf_split(mode_lib, rq_param, pipe_src_param); 753 print__rq_params_st(mode_lib, *rq_param); 754 } 755 756 void dml20v2_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib, 757 display_rq_regs_st *rq_regs, 758 const display_pipe_params_st pipe_param) 759 { 760 display_rq_params_st rq_param = {0}; 761 762 memset(rq_regs, 0, sizeof(*rq_regs)); 763 dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, pipe_param.src); 764 extract_rq_regs(mode_lib, rq_regs, rq_param); 765 766 print__rq_regs_st(mode_lib, *rq_regs); 767 } 768 769 // Note: currently taken in as is. 770 // Nice to decouple code from hw register implement and extract code that are repeated for luma and chroma. 771 static void dml20v2_rq_dlg_get_dlg_params(struct display_mode_lib *mode_lib, 772 const display_e2e_pipe_params_st *e2e_pipe_param, 773 const unsigned int num_pipes, 774 const unsigned int pipe_idx, 775 display_dlg_regs_st *disp_dlg_regs, 776 display_ttu_regs_st *disp_ttu_regs, 777 const display_rq_dlg_params_st rq_dlg_param, 778 const display_dlg_sys_params_st dlg_sys_param, 779 const bool cstate_en, 780 const bool pstate_en) 781 { 782 const display_pipe_source_params_st *src = &e2e_pipe_param[pipe_idx].pipe.src; 783 const display_pipe_dest_params_st *dst = &e2e_pipe_param[pipe_idx].pipe.dest; 784 const display_output_params_st *dout = &e2e_pipe_param[pipe_idx].dout; 785 const display_clocks_and_cfg_st *clks = &e2e_pipe_param[pipe_idx].clks_cfg; 786 const scaler_ratio_depth_st *scl = &e2e_pipe_param[pipe_idx].pipe.scale_ratio_depth; 787 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; 788 789 // ------------------------- 790 // Section 1.15.2.1: OTG dependent Params 791 // ------------------------- 792 // Timing 793 unsigned int htotal = dst->htotal; 794 // unsigned int hblank_start = dst.hblank_start; // TODO: Remove 795 unsigned int hblank_end = dst->hblank_end; 796 unsigned int vblank_start = dst->vblank_start; 797 unsigned int vblank_end = dst->vblank_end; 798 unsigned int min_vblank = mode_lib->ip.min_vblank_lines; 799 800 double dppclk_freq_in_mhz = clks->dppclk_mhz; 801 double dispclk_freq_in_mhz = clks->dispclk_mhz; 802 double refclk_freq_in_mhz = clks->refclk_mhz; 803 double pclk_freq_in_mhz = dst->pixel_rate_mhz; 804 bool interlaced = dst->interlaced; 805 806 double ref_freq_to_pix_freq = refclk_freq_in_mhz / pclk_freq_in_mhz; 807 808 double min_dcfclk_mhz; 809 double t_calc_us; 810 double min_ttu_vblank; 811 812 double min_dst_y_ttu_vblank; 813 unsigned int dlg_vblank_start; 814 bool dual_plane; 815 bool mode_422; 816 unsigned int access_dir; 817 unsigned int vp_height_l; 818 unsigned int vp_width_l; 819 unsigned int vp_height_c; 820 unsigned int vp_width_c; 821 822 // Scaling 823 unsigned int htaps_l; 824 unsigned int htaps_c; 825 double hratio_l; 826 double hratio_c; 827 double vratio_l; 828 double vratio_c; 829 bool scl_enable; 830 831 double line_time_in_us; 832 // double vinit_l; 833 // double vinit_c; 834 // double vinit_bot_l; 835 // double vinit_bot_c; 836 837 // unsigned int swath_height_l; 838 unsigned int swath_width_ub_l; 839 // unsigned int dpte_bytes_per_row_ub_l; 840 unsigned int dpte_groups_per_row_ub_l; 841 // unsigned int meta_pte_bytes_per_frame_ub_l; 842 // unsigned int meta_bytes_per_row_ub_l; 843 844 // unsigned int swath_height_c; 845 unsigned int swath_width_ub_c; 846 // unsigned int dpte_bytes_per_row_ub_c; 847 unsigned int dpte_groups_per_row_ub_c; 848 849 unsigned int meta_chunks_per_row_ub_l; 850 unsigned int meta_chunks_per_row_ub_c; 851 unsigned int vupdate_offset; 852 unsigned int vupdate_width; 853 unsigned int vready_offset; 854 855 unsigned int dppclk_delay_subtotal; 856 unsigned int dispclk_delay_subtotal; 857 unsigned int pixel_rate_delay_subtotal; 858 859 unsigned int vstartup_start; 860 unsigned int dst_x_after_scaler; 861 unsigned int dst_y_after_scaler; 862 double line_wait; 863 double dst_y_prefetch; 864 double dst_y_per_vm_vblank; 865 double dst_y_per_row_vblank; 866 double dst_y_per_vm_flip; 867 double dst_y_per_row_flip; 868 double min_dst_y_per_vm_vblank; 869 double min_dst_y_per_row_vblank; 870 double lsw; 871 double vratio_pre_l; 872 double vratio_pre_c; 873 unsigned int req_per_swath_ub_l; 874 unsigned int req_per_swath_ub_c; 875 unsigned int meta_row_height_l; 876 unsigned int meta_row_height_c; 877 unsigned int swath_width_pixels_ub_l; 878 unsigned int swath_width_pixels_ub_c; 879 unsigned int scaler_rec_in_width_l; 880 unsigned int scaler_rec_in_width_c; 881 unsigned int dpte_row_height_l; 882 unsigned int dpte_row_height_c; 883 double hscale_pixel_rate_l; 884 double hscale_pixel_rate_c; 885 double min_hratio_fact_l; 886 double min_hratio_fact_c; 887 double refcyc_per_line_delivery_pre_l; 888 double refcyc_per_line_delivery_pre_c; 889 double refcyc_per_line_delivery_l; 890 double refcyc_per_line_delivery_c; 891 892 double refcyc_per_req_delivery_pre_l; 893 double refcyc_per_req_delivery_pre_c; 894 double refcyc_per_req_delivery_l; 895 double refcyc_per_req_delivery_c; 896 897 unsigned int full_recout_width; 898 double xfc_transfer_delay; 899 double xfc_precharge_delay; 900 double xfc_remote_surface_flip_latency; 901 double xfc_dst_y_delta_drq_limit; 902 double xfc_prefetch_margin; 903 double refcyc_per_req_delivery_pre_cur0; 904 double refcyc_per_req_delivery_cur0; 905 double refcyc_per_req_delivery_pre_cur1; 906 double refcyc_per_req_delivery_cur1; 907 908 memset(disp_dlg_regs, 0, sizeof(*disp_dlg_regs)); 909 memset(disp_ttu_regs, 0, sizeof(*disp_ttu_regs)); 910 911 dml_print("DML_DLG: %s: cstate_en = %d\n", __func__, cstate_en); 912 dml_print("DML_DLG: %s: pstate_en = %d\n", __func__, pstate_en); 913 914 dml_print("DML_DLG: %s: dppclk_freq_in_mhz = %3.2f\n", __func__, dppclk_freq_in_mhz); 915 dml_print("DML_DLG: %s: dispclk_freq_in_mhz = %3.2f\n", __func__, dispclk_freq_in_mhz); 916 dml_print("DML_DLG: %s: refclk_freq_in_mhz = %3.2f\n", __func__, refclk_freq_in_mhz); 917 dml_print("DML_DLG: %s: pclk_freq_in_mhz = %3.2f\n", __func__, pclk_freq_in_mhz); 918 dml_print("DML_DLG: %s: interlaced = %d\n", __func__, interlaced); 919 ASSERT(ref_freq_to_pix_freq < 4.0); 920 921 disp_dlg_regs->ref_freq_to_pix_freq = 922 (unsigned int) (ref_freq_to_pix_freq * dml_pow(2, 19)); 923 disp_dlg_regs->refcyc_per_htotal = (unsigned int) (ref_freq_to_pix_freq * (double) htotal 924 * dml_pow(2, 8)); 925 disp_dlg_regs->dlg_vblank_end = interlaced ? (vblank_end / 2) : vblank_end; // 15 bits 926 disp_dlg_regs->refcyc_h_blank_end = (unsigned int) ((double) hblank_end 927 * (double) ref_freq_to_pix_freq); 928 ASSERT(disp_dlg_regs->refcyc_h_blank_end < (unsigned int) dml_pow(2, 13)); 929 930 min_dcfclk_mhz = dlg_sys_param.deepsleep_dcfclk_mhz; 931 t_calc_us = get_tcalc(mode_lib, e2e_pipe_param, num_pipes); 932 min_ttu_vblank = get_min_ttu_vblank(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 933 934 min_dst_y_ttu_vblank = min_ttu_vblank * pclk_freq_in_mhz / (double) htotal; 935 dlg_vblank_start = interlaced ? (vblank_start / 2) : vblank_start; 936 937 disp_dlg_regs->min_dst_y_next_start = (unsigned int) (((double) dlg_vblank_start 938 + min_dst_y_ttu_vblank) * dml_pow(2, 2)); 939 ASSERT(disp_dlg_regs->min_dst_y_next_start < (unsigned int) dml_pow(2, 18)); 940 941 dml_print("DML_DLG: %s: min_dcfclk_mhz = %3.2f\n", 942 __func__, 943 min_dcfclk_mhz); 944 dml_print("DML_DLG: %s: min_ttu_vblank = %3.2f\n", 945 __func__, 946 min_ttu_vblank); 947 dml_print("DML_DLG: %s: min_dst_y_ttu_vblank = %3.2f\n", 948 __func__, 949 min_dst_y_ttu_vblank); 950 dml_print("DML_DLG: %s: t_calc_us = %3.2f\n", 951 __func__, 952 t_calc_us); 953 dml_print("DML_DLG: %s: disp_dlg_regs->min_dst_y_next_start = 0x%0x\n", 954 __func__, 955 disp_dlg_regs->min_dst_y_next_start); 956 dml_print("DML_DLG: %s: ref_freq_to_pix_freq = %3.2f\n", 957 __func__, 958 ref_freq_to_pix_freq); 959 960 // ------------------------- 961 // Section 1.15.2.2: Prefetch, Active and TTU 962 // ------------------------- 963 // Prefetch Calc 964 // Source 965 // dcc_en = src.dcc; 966 dual_plane = is_dual_plane((enum source_format_class)(src->source_format)); 967 mode_422 = false; // TODO 968 access_dir = (src->source_scan == dm_vert); // vp access direction: horizontal or vertical accessed 969 // bytes_per_element_l = get_bytes_per_element(source_format_class(src.source_format), 0); 970 // bytes_per_element_c = get_bytes_per_element(source_format_class(src.source_format), 1); 971 vp_height_l = src->viewport_height; 972 vp_width_l = src->viewport_width; 973 vp_height_c = src->viewport_height_c; 974 vp_width_c = src->viewport_width_c; 975 976 // Scaling 977 htaps_l = taps->htaps; 978 htaps_c = taps->htaps_c; 979 hratio_l = scl->hscl_ratio; 980 hratio_c = scl->hscl_ratio_c; 981 vratio_l = scl->vscl_ratio; 982 vratio_c = scl->vscl_ratio_c; 983 scl_enable = scl->scl_enable; 984 985 line_time_in_us = (htotal / pclk_freq_in_mhz); 986 // vinit_l = scl.vinit; 987 // vinit_c = scl.vinit_c; 988 // vinit_bot_l = scl.vinit_bot; 989 // vinit_bot_c = scl.vinit_bot_c; 990 991 // unsigned int swath_height_l = rq_dlg_param.rq_l.swath_height; 992 swath_width_ub_l = rq_dlg_param.rq_l.swath_width_ub; 993 // unsigned int dpte_bytes_per_row_ub_l = rq_dlg_param.rq_l.dpte_bytes_per_row_ub; 994 dpte_groups_per_row_ub_l = rq_dlg_param.rq_l.dpte_groups_per_row_ub; 995 // unsigned int meta_pte_bytes_per_frame_ub_l = rq_dlg_param.rq_l.meta_pte_bytes_per_frame_ub; 996 // unsigned int meta_bytes_per_row_ub_l = rq_dlg_param.rq_l.meta_bytes_per_row_ub; 997 998 // unsigned int swath_height_c = rq_dlg_param.rq_c.swath_height; 999 swath_width_ub_c = rq_dlg_param.rq_c.swath_width_ub; 1000 // dpte_bytes_per_row_ub_c = rq_dlg_param.rq_c.dpte_bytes_per_row_ub; 1001 dpte_groups_per_row_ub_c = rq_dlg_param.rq_c.dpte_groups_per_row_ub; 1002 1003 meta_chunks_per_row_ub_l = rq_dlg_param.rq_l.meta_chunks_per_row_ub; 1004 meta_chunks_per_row_ub_c = rq_dlg_param.rq_c.meta_chunks_per_row_ub; 1005 vupdate_offset = dst->vupdate_offset; 1006 vupdate_width = dst->vupdate_width; 1007 vready_offset = dst->vready_offset; 1008 1009 dppclk_delay_subtotal = mode_lib->ip.dppclk_delay_subtotal; 1010 dispclk_delay_subtotal = mode_lib->ip.dispclk_delay_subtotal; 1011 1012 if (scl_enable) 1013 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl; 1014 else 1015 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_scl_lb_only; 1016 1017 dppclk_delay_subtotal += mode_lib->ip.dppclk_delay_cnvc_formatter 1018 + src->num_cursors * mode_lib->ip.dppclk_delay_cnvc_cursor; 1019 1020 if (dout->dsc_enable) { 1021 double dsc_delay = get_dsc_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1022 1023 dispclk_delay_subtotal += dsc_delay; 1024 } 1025 1026 pixel_rate_delay_subtotal = dppclk_delay_subtotal * pclk_freq_in_mhz / dppclk_freq_in_mhz 1027 + dispclk_delay_subtotal * pclk_freq_in_mhz / dispclk_freq_in_mhz; 1028 1029 vstartup_start = dst->vstartup_start; 1030 if (interlaced) { 1031 if (vstartup_start / 2.0 1032 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal 1033 <= vblank_end / 2.0) 1034 disp_dlg_regs->vready_after_vcount0 = 1; 1035 else 1036 disp_dlg_regs->vready_after_vcount0 = 0; 1037 } else { 1038 if (vstartup_start 1039 - (double) (vready_offset + vupdate_width + vupdate_offset) / htotal 1040 <= vblank_end) 1041 disp_dlg_regs->vready_after_vcount0 = 1; 1042 else 1043 disp_dlg_regs->vready_after_vcount0 = 0; 1044 } 1045 1046 // TODO: Where is this coming from? 1047 if (interlaced) 1048 vstartup_start = vstartup_start / 2; 1049 1050 // TODO: What if this min_vblank doesn't match the value in the dml_config_settings.cpp? 1051 if (vstartup_start >= min_vblank) { 1052 dml_print("WARNING: DML_DLG: %s: vblank_start=%d vblank_end=%d\n", 1053 __func__, 1054 vblank_start, 1055 vblank_end); 1056 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1057 __func__, 1058 vstartup_start, 1059 min_vblank); 1060 min_vblank = vstartup_start + 1; 1061 dml_print("WARNING: DML_DLG: %s: vstartup_start=%d should be less than min_vblank=%d\n", 1062 __func__, 1063 vstartup_start, 1064 min_vblank); 1065 } 1066 1067 dst_x_after_scaler = get_dst_x_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1068 dst_y_after_scaler = get_dst_y_after_scaler(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1069 1070 dml_print("DML_DLG: %s: htotal = %d\n", __func__, htotal); 1071 dml_print("DML_DLG: %s: pixel_rate_delay_subtotal = %d\n", 1072 __func__, 1073 pixel_rate_delay_subtotal); 1074 dml_print("DML_DLG: %s: dst_x_after_scaler = %d\n", 1075 __func__, 1076 dst_x_after_scaler); 1077 dml_print("DML_DLG: %s: dst_y_after_scaler = %d\n", 1078 __func__, 1079 dst_y_after_scaler); 1080 1081 // Lwait 1082 line_wait = mode_lib->soc.urgent_latency_us; 1083 if (cstate_en) 1084 line_wait = dml_max(mode_lib->soc.sr_enter_plus_exit_time_us, line_wait); 1085 if (pstate_en) 1086 line_wait = dml_max(mode_lib->soc.dram_clock_change_latency_us 1087 + mode_lib->soc.urgent_latency_us, 1088 line_wait); 1089 line_wait = line_wait / line_time_in_us; 1090 1091 dst_y_prefetch = get_dst_y_prefetch(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1092 dml_print("DML_DLG: %s: dst_y_prefetch (after rnd) = %3.2f\n", __func__, dst_y_prefetch); 1093 1094 dst_y_per_vm_vblank = get_dst_y_per_vm_vblank(mode_lib, 1095 e2e_pipe_param, 1096 num_pipes, 1097 pipe_idx); 1098 dst_y_per_row_vblank = get_dst_y_per_row_vblank(mode_lib, 1099 e2e_pipe_param, 1100 num_pipes, 1101 pipe_idx); 1102 dst_y_per_vm_flip = get_dst_y_per_vm_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1103 dst_y_per_row_flip = get_dst_y_per_row_flip(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1104 1105 min_dst_y_per_vm_vblank = 8.0; 1106 min_dst_y_per_row_vblank = 16.0; 1107 1108 // magic! 1109 if (htotal <= 75) { 1110 min_vblank = 300; 1111 min_dst_y_per_vm_vblank = 100.0; 1112 min_dst_y_per_row_vblank = 100.0; 1113 } 1114 1115 dml_print("DML_DLG: %s: dst_y_per_vm_vblank = %3.2f\n", __func__, dst_y_per_vm_vblank); 1116 dml_print("DML_DLG: %s: dst_y_per_row_vblank = %3.2f\n", __func__, dst_y_per_row_vblank); 1117 1118 ASSERT(dst_y_per_vm_vblank < min_dst_y_per_vm_vblank); 1119 ASSERT(dst_y_per_row_vblank < min_dst_y_per_row_vblank); 1120 1121 ASSERT(dst_y_prefetch > (dst_y_per_vm_vblank + dst_y_per_row_vblank)); 1122 lsw = dst_y_prefetch - (dst_y_per_vm_vblank + dst_y_per_row_vblank); 1123 1124 dml_print("DML_DLG: %s: lsw = %3.2f\n", __func__, lsw); 1125 1126 vratio_pre_l = get_vratio_prefetch_l(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1127 vratio_pre_c = get_vratio_prefetch_c(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1128 1129 dml_print("DML_DLG: %s: vratio_pre_l=%3.2f\n", __func__, vratio_pre_l); 1130 dml_print("DML_DLG: %s: vratio_pre_c=%3.2f\n", __func__, vratio_pre_c); 1131 1132 // Active 1133 req_per_swath_ub_l = rq_dlg_param.rq_l.req_per_swath_ub; 1134 req_per_swath_ub_c = rq_dlg_param.rq_c.req_per_swath_ub; 1135 meta_row_height_l = rq_dlg_param.rq_l.meta_row_height; 1136 meta_row_height_c = rq_dlg_param.rq_c.meta_row_height; 1137 swath_width_pixels_ub_l = 0; 1138 swath_width_pixels_ub_c = 0; 1139 scaler_rec_in_width_l = 0; 1140 scaler_rec_in_width_c = 0; 1141 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height; 1142 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height; 1143 1144 if (mode_422) { 1145 swath_width_pixels_ub_l = swath_width_ub_l * 2; // *2 for 2 pixel per element 1146 swath_width_pixels_ub_c = swath_width_ub_c * 2; 1147 } else { 1148 swath_width_pixels_ub_l = swath_width_ub_l * 1; 1149 swath_width_pixels_ub_c = swath_width_ub_c * 1; 1150 } 1151 1152 hscale_pixel_rate_l = 0.; 1153 hscale_pixel_rate_c = 0.; 1154 min_hratio_fact_l = 1.0; 1155 min_hratio_fact_c = 1.0; 1156 1157 if (htaps_l <= 1) 1158 min_hratio_fact_l = 2.0; 1159 else if (htaps_l <= 6) { 1160 if ((hratio_l * 2.0) > 4.0) 1161 min_hratio_fact_l = 4.0; 1162 else 1163 min_hratio_fact_l = hratio_l * 2.0; 1164 } else { 1165 if (hratio_l > 4.0) 1166 min_hratio_fact_l = 4.0; 1167 else 1168 min_hratio_fact_l = hratio_l; 1169 } 1170 1171 hscale_pixel_rate_l = min_hratio_fact_l * dppclk_freq_in_mhz; 1172 1173 if (htaps_c <= 1) 1174 min_hratio_fact_c = 2.0; 1175 else if (htaps_c <= 6) { 1176 if ((hratio_c * 2.0) > 4.0) 1177 min_hratio_fact_c = 4.0; 1178 else 1179 min_hratio_fact_c = hratio_c * 2.0; 1180 } else { 1181 if (hratio_c > 4.0) 1182 min_hratio_fact_c = 4.0; 1183 else 1184 min_hratio_fact_c = hratio_c; 1185 } 1186 1187 hscale_pixel_rate_c = min_hratio_fact_c * dppclk_freq_in_mhz; 1188 1189 refcyc_per_line_delivery_pre_l = 0.; 1190 refcyc_per_line_delivery_pre_c = 0.; 1191 refcyc_per_line_delivery_l = 0.; 1192 refcyc_per_line_delivery_c = 0.; 1193 1194 refcyc_per_req_delivery_pre_l = 0.; 1195 refcyc_per_req_delivery_pre_c = 0.; 1196 refcyc_per_req_delivery_l = 0.; 1197 refcyc_per_req_delivery_c = 0.; 1198 1199 full_recout_width = 0; 1200 // In ODM 1201 if (src->is_hsplit) { 1202 // This "hack" is only allowed (and valid) for MPC combine. In ODM 1203 // combine, you MUST specify the full_recout_width...according to Oswin 1204 if (dst->full_recout_width == 0 && !dst->odm_combine) { 1205 dml_print("DML_DLG: %s: Warning: full_recout_width not set in hsplit mode\n", 1206 __func__); 1207 full_recout_width = dst->recout_width * 2; // assume half split for dcn1 1208 } else 1209 full_recout_width = dst->full_recout_width; 1210 } else 1211 full_recout_width = dst->recout_width; 1212 1213 // As of DCN2, mpc_combine and odm_combine are mutually exclusive 1214 refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1215 refclk_freq_in_mhz, 1216 pclk_freq_in_mhz, 1217 dst->odm_combine, 1218 full_recout_width, 1219 dst->hactive, 1220 vratio_pre_l, 1221 hscale_pixel_rate_l, 1222 swath_width_pixels_ub_l, 1223 1); // per line 1224 1225 refcyc_per_line_delivery_l = get_refcyc_per_delivery(mode_lib, 1226 refclk_freq_in_mhz, 1227 pclk_freq_in_mhz, 1228 dst->odm_combine, 1229 full_recout_width, 1230 dst->hactive, 1231 vratio_l, 1232 hscale_pixel_rate_l, 1233 swath_width_pixels_ub_l, 1234 1); // per line 1235 1236 dml_print("DML_DLG: %s: full_recout_width = %d\n", 1237 __func__, 1238 full_recout_width); 1239 dml_print("DML_DLG: %s: hscale_pixel_rate_l = %3.2f\n", 1240 __func__, 1241 hscale_pixel_rate_l); 1242 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_l = %3.2f\n", 1243 __func__, 1244 refcyc_per_line_delivery_pre_l); 1245 dml_print("DML_DLG: %s: refcyc_per_line_delivery_l = %3.2f\n", 1246 __func__, 1247 refcyc_per_line_delivery_l); 1248 1249 if (dual_plane) { 1250 refcyc_per_line_delivery_pre_c = get_refcyc_per_delivery(mode_lib, 1251 refclk_freq_in_mhz, 1252 pclk_freq_in_mhz, 1253 dst->odm_combine, 1254 full_recout_width, 1255 dst->hactive, 1256 vratio_pre_c, 1257 hscale_pixel_rate_c, 1258 swath_width_pixels_ub_c, 1259 1); // per line 1260 1261 refcyc_per_line_delivery_c = get_refcyc_per_delivery(mode_lib, 1262 refclk_freq_in_mhz, 1263 pclk_freq_in_mhz, 1264 dst->odm_combine, 1265 full_recout_width, 1266 dst->hactive, 1267 vratio_c, 1268 hscale_pixel_rate_c, 1269 swath_width_pixels_ub_c, 1270 1); // per line 1271 1272 dml_print("DML_DLG: %s: refcyc_per_line_delivery_pre_c = %3.2f\n", 1273 __func__, 1274 refcyc_per_line_delivery_pre_c); 1275 dml_print("DML_DLG: %s: refcyc_per_line_delivery_c = %3.2f\n", 1276 __func__, 1277 refcyc_per_line_delivery_c); 1278 } 1279 1280 // TTU - Luma / Chroma 1281 if (access_dir) { // vertical access 1282 scaler_rec_in_width_l = vp_height_l; 1283 scaler_rec_in_width_c = vp_height_c; 1284 } else { 1285 scaler_rec_in_width_l = vp_width_l; 1286 scaler_rec_in_width_c = vp_width_c; 1287 } 1288 1289 refcyc_per_req_delivery_pre_l = get_refcyc_per_delivery(mode_lib, 1290 refclk_freq_in_mhz, 1291 pclk_freq_in_mhz, 1292 dst->odm_combine, 1293 full_recout_width, 1294 dst->hactive, 1295 vratio_pre_l, 1296 hscale_pixel_rate_l, 1297 scaler_rec_in_width_l, 1298 req_per_swath_ub_l); // per req 1299 refcyc_per_req_delivery_l = get_refcyc_per_delivery(mode_lib, 1300 refclk_freq_in_mhz, 1301 pclk_freq_in_mhz, 1302 dst->odm_combine, 1303 full_recout_width, 1304 dst->hactive, 1305 vratio_l, 1306 hscale_pixel_rate_l, 1307 scaler_rec_in_width_l, 1308 req_per_swath_ub_l); // per req 1309 1310 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_l = %3.2f\n", 1311 __func__, 1312 refcyc_per_req_delivery_pre_l); 1313 dml_print("DML_DLG: %s: refcyc_per_req_delivery_l = %3.2f\n", 1314 __func__, 1315 refcyc_per_req_delivery_l); 1316 1317 ASSERT(refcyc_per_req_delivery_pre_l < dml_pow(2, 13)); 1318 ASSERT(refcyc_per_req_delivery_l < dml_pow(2, 13)); 1319 1320 if (dual_plane) { 1321 refcyc_per_req_delivery_pre_c = get_refcyc_per_delivery(mode_lib, 1322 refclk_freq_in_mhz, 1323 pclk_freq_in_mhz, 1324 dst->odm_combine, 1325 full_recout_width, 1326 dst->hactive, 1327 vratio_pre_c, 1328 hscale_pixel_rate_c, 1329 scaler_rec_in_width_c, 1330 req_per_swath_ub_c); // per req 1331 refcyc_per_req_delivery_c = get_refcyc_per_delivery(mode_lib, 1332 refclk_freq_in_mhz, 1333 pclk_freq_in_mhz, 1334 dst->odm_combine, 1335 full_recout_width, 1336 dst->hactive, 1337 vratio_c, 1338 hscale_pixel_rate_c, 1339 scaler_rec_in_width_c, 1340 req_per_swath_ub_c); // per req 1341 1342 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_c = %3.2f\n", 1343 __func__, 1344 refcyc_per_req_delivery_pre_c); 1345 dml_print("DML_DLG: %s: refcyc_per_req_delivery_c = %3.2f\n", 1346 __func__, 1347 refcyc_per_req_delivery_c); 1348 1349 ASSERT(refcyc_per_req_delivery_pre_c < dml_pow(2, 13)); 1350 ASSERT(refcyc_per_req_delivery_c < dml_pow(2, 13)); 1351 } 1352 1353 // XFC 1354 xfc_transfer_delay = get_xfc_transfer_delay(mode_lib, e2e_pipe_param, num_pipes, pipe_idx); 1355 xfc_precharge_delay = get_xfc_precharge_delay(mode_lib, 1356 e2e_pipe_param, 1357 num_pipes, 1358 pipe_idx); 1359 xfc_remote_surface_flip_latency = get_xfc_remote_surface_flip_latency(mode_lib, 1360 e2e_pipe_param, 1361 num_pipes, 1362 pipe_idx); 1363 xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency; 1364 xfc_prefetch_margin = get_xfc_prefetch_margin(mode_lib, 1365 e2e_pipe_param, 1366 num_pipes, 1367 pipe_idx); 1368 1369 // TTU - Cursor 1370 refcyc_per_req_delivery_pre_cur0 = 0.0; 1371 refcyc_per_req_delivery_cur0 = 0.0; 1372 if (src->num_cursors > 0) { 1373 calculate_ttu_cursor(mode_lib, 1374 &refcyc_per_req_delivery_pre_cur0, 1375 &refcyc_per_req_delivery_cur0, 1376 refclk_freq_in_mhz, 1377 ref_freq_to_pix_freq, 1378 hscale_pixel_rate_l, 1379 scl->hscl_ratio, 1380 vratio_pre_l, 1381 vratio_l, 1382 src->cur0_src_width, 1383 (enum cursor_bpp)(src->cur0_bpp)); 1384 } 1385 1386 refcyc_per_req_delivery_pre_cur1 = 0.0; 1387 refcyc_per_req_delivery_cur1 = 0.0; 1388 if (src->num_cursors > 1) { 1389 calculate_ttu_cursor(mode_lib, 1390 &refcyc_per_req_delivery_pre_cur1, 1391 &refcyc_per_req_delivery_cur1, 1392 refclk_freq_in_mhz, 1393 ref_freq_to_pix_freq, 1394 hscale_pixel_rate_l, 1395 scl->hscl_ratio, 1396 vratio_pre_l, 1397 vratio_l, 1398 src->cur1_src_width, 1399 (enum cursor_bpp)(src->cur1_bpp)); 1400 } 1401 1402 // TTU - Misc 1403 // all hard-coded 1404 1405 // Assignment to register structures 1406 disp_dlg_regs->dst_y_after_scaler = dst_y_after_scaler; // in terms of line 1407 disp_dlg_regs->refcyc_x_after_scaler = dst_x_after_scaler * ref_freq_to_pix_freq; // in terms of refclk 1408 ASSERT(disp_dlg_regs->refcyc_x_after_scaler < (unsigned int) dml_pow(2, 13)); 1409 disp_dlg_regs->dst_y_prefetch = (unsigned int) (dst_y_prefetch * dml_pow(2, 2)); 1410 disp_dlg_regs->dst_y_per_vm_vblank = (unsigned int) (dst_y_per_vm_vblank * dml_pow(2, 2)); 1411 disp_dlg_regs->dst_y_per_row_vblank = (unsigned int) (dst_y_per_row_vblank * dml_pow(2, 2)); 1412 disp_dlg_regs->dst_y_per_vm_flip = (unsigned int) (dst_y_per_vm_flip * dml_pow(2, 2)); 1413 disp_dlg_regs->dst_y_per_row_flip = (unsigned int) (dst_y_per_row_flip * dml_pow(2, 2)); 1414 1415 disp_dlg_regs->vratio_prefetch = (unsigned int) (vratio_pre_l * dml_pow(2, 19)); 1416 disp_dlg_regs->vratio_prefetch_c = (unsigned int) (vratio_pre_c * dml_pow(2, 19)); 1417 1418 disp_dlg_regs->refcyc_per_pte_group_vblank_l = 1419 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1420 * ref_freq_to_pix_freq / (double) dpte_groups_per_row_ub_l); 1421 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_l < (unsigned int) dml_pow(2, 13)); 1422 1423 if (dual_plane) { 1424 disp_dlg_regs->refcyc_per_pte_group_vblank_c = (unsigned int) (dst_y_per_row_vblank 1425 * (double) htotal * ref_freq_to_pix_freq 1426 / (double) dpte_groups_per_row_ub_c); 1427 ASSERT(disp_dlg_regs->refcyc_per_pte_group_vblank_c 1428 < (unsigned int) dml_pow(2, 13)); 1429 } 1430 1431 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 1432 (unsigned int) (dst_y_per_row_vblank * (double) htotal 1433 * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); 1434 ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13)); 1435 1436 disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = 1437 disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1438 1439 disp_dlg_regs->refcyc_per_pte_group_flip_l = (unsigned int) (dst_y_per_row_flip * htotal 1440 * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_l; 1441 disp_dlg_regs->refcyc_per_meta_chunk_flip_l = (unsigned int) (dst_y_per_row_flip * htotal 1442 * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_l; 1443 1444 if (dual_plane) { 1445 disp_dlg_regs->refcyc_per_pte_group_flip_c = (unsigned int) (dst_y_per_row_flip 1446 * htotal * ref_freq_to_pix_freq) / dpte_groups_per_row_ub_c; 1447 disp_dlg_regs->refcyc_per_meta_chunk_flip_c = (unsigned int) (dst_y_per_row_flip 1448 * htotal * ref_freq_to_pix_freq) / meta_chunks_per_row_ub_c; 1449 } 1450 1451 disp_dlg_regs->dst_y_per_pte_row_nom_l = (unsigned int) ((double) dpte_row_height_l 1452 / (double) vratio_l * dml_pow(2, 2)); 1453 ASSERT(disp_dlg_regs->dst_y_per_pte_row_nom_l < (unsigned int) dml_pow(2, 17)); 1454 1455 if (dual_plane) { 1456 disp_dlg_regs->dst_y_per_pte_row_nom_c = (unsigned int) ((double) dpte_row_height_c 1457 / (double) vratio_c * dml_pow(2, 2)); 1458 if (disp_dlg_regs->dst_y_per_pte_row_nom_c >= (unsigned int) dml_pow(2, 17)) { 1459 dml_print("DML_DLG: %s: Warning dst_y_per_pte_row_nom_c %u larger than supported by register format U15.2 %u\n", 1460 __func__, 1461 disp_dlg_regs->dst_y_per_pte_row_nom_c, 1462 (unsigned int) dml_pow(2, 17) - 1); 1463 } 1464 } 1465 1466 disp_dlg_regs->dst_y_per_meta_row_nom_l = (unsigned int) ((double) meta_row_height_l 1467 / (double) vratio_l * dml_pow(2, 2)); 1468 ASSERT(disp_dlg_regs->dst_y_per_meta_row_nom_l < (unsigned int) dml_pow(2, 17)); 1469 1470 disp_dlg_regs->dst_y_per_meta_row_nom_c = disp_dlg_regs->dst_y_per_meta_row_nom_l; // TODO: dcc for 4:2:0 is not supported in dcn1.0. assigned to be the same as _l for now 1471 1472 disp_dlg_regs->refcyc_per_pte_group_nom_l = (unsigned int) ((double) dpte_row_height_l 1473 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1474 / (double) dpte_groups_per_row_ub_l); 1475 if (disp_dlg_regs->refcyc_per_pte_group_nom_l >= (unsigned int) dml_pow(2, 23)) 1476 disp_dlg_regs->refcyc_per_pte_group_nom_l = dml_pow(2, 23) - 1; 1477 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = (unsigned int) ((double) meta_row_height_l 1478 / (double) vratio_l * (double) htotal * ref_freq_to_pix_freq 1479 / (double) meta_chunks_per_row_ub_l); 1480 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_l >= (unsigned int) dml_pow(2, 23)) 1481 disp_dlg_regs->refcyc_per_meta_chunk_nom_l = dml_pow(2, 23) - 1; 1482 1483 if (dual_plane) { 1484 disp_dlg_regs->refcyc_per_pte_group_nom_c = 1485 (unsigned int) ((double) dpte_row_height_c / (double) vratio_c 1486 * (double) htotal * ref_freq_to_pix_freq 1487 / (double) dpte_groups_per_row_ub_c); 1488 if (disp_dlg_regs->refcyc_per_pte_group_nom_c >= (unsigned int) dml_pow(2, 23)) 1489 disp_dlg_regs->refcyc_per_pte_group_nom_c = dml_pow(2, 23) - 1; 1490 1491 // TODO: Is this the right calculation? Does htotal need to be halved? 1492 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = 1493 (unsigned int) ((double) meta_row_height_c / (double) vratio_c 1494 * (double) htotal * ref_freq_to_pix_freq 1495 / (double) meta_chunks_per_row_ub_c); 1496 if (disp_dlg_regs->refcyc_per_meta_chunk_nom_c >= (unsigned int) dml_pow(2, 23)) 1497 disp_dlg_regs->refcyc_per_meta_chunk_nom_c = dml_pow(2, 23) - 1; 1498 } 1499 1500 disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, 1501 1); 1502 disp_dlg_regs->refcyc_per_line_delivery_l = (unsigned int) dml_floor(refcyc_per_line_delivery_l, 1503 1); 1504 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); 1505 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_l < (unsigned int) dml_pow(2, 13)); 1506 1507 disp_dlg_regs->refcyc_per_line_delivery_pre_c = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_c, 1508 1); 1509 disp_dlg_regs->refcyc_per_line_delivery_c = (unsigned int) dml_floor(refcyc_per_line_delivery_c, 1510 1); 1511 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_c < (unsigned int) dml_pow(2, 13)); 1512 ASSERT(disp_dlg_regs->refcyc_per_line_delivery_c < (unsigned int) dml_pow(2, 13)); 1513 1514 disp_dlg_regs->chunk_hdl_adjust_cur0 = 3; 1515 disp_dlg_regs->dst_y_offset_cur0 = 0; 1516 disp_dlg_regs->chunk_hdl_adjust_cur1 = 3; 1517 disp_dlg_regs->dst_y_offset_cur1 = 0; 1518 1519 disp_dlg_regs->xfc_reg_transfer_delay = xfc_transfer_delay; 1520 disp_dlg_regs->xfc_reg_precharge_delay = xfc_precharge_delay; 1521 disp_dlg_regs->xfc_reg_remote_surface_flip_latency = xfc_remote_surface_flip_latency; 1522 disp_dlg_regs->xfc_reg_prefetch_margin = dml_ceil(xfc_prefetch_margin * refclk_freq_in_mhz, 1523 1); 1524 1525 // slave has to have this value also set to off 1526 if (src->xfc_enable && !src->xfc_slave) 1527 disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1); 1528 else 1529 disp_dlg_regs->dst_y_delta_drq_limit = 0x7fff; // off 1530 1531 disp_ttu_regs->refcyc_per_req_delivery_pre_l = (unsigned int) (refcyc_per_req_delivery_pre_l 1532 * dml_pow(2, 10)); 1533 disp_ttu_regs->refcyc_per_req_delivery_l = (unsigned int) (refcyc_per_req_delivery_l 1534 * dml_pow(2, 10)); 1535 disp_ttu_regs->refcyc_per_req_delivery_pre_c = (unsigned int) (refcyc_per_req_delivery_pre_c 1536 * dml_pow(2, 10)); 1537 disp_ttu_regs->refcyc_per_req_delivery_c = (unsigned int) (refcyc_per_req_delivery_c 1538 * dml_pow(2, 10)); 1539 disp_ttu_regs->refcyc_per_req_delivery_pre_cur0 = 1540 (unsigned int) (refcyc_per_req_delivery_pre_cur0 * dml_pow(2, 10)); 1541 disp_ttu_regs->refcyc_per_req_delivery_cur0 = (unsigned int) (refcyc_per_req_delivery_cur0 1542 * dml_pow(2, 10)); 1543 disp_ttu_regs->refcyc_per_req_delivery_pre_cur1 = 1544 (unsigned int) (refcyc_per_req_delivery_pre_cur1 * dml_pow(2, 10)); 1545 disp_ttu_regs->refcyc_per_req_delivery_cur1 = (unsigned int) (refcyc_per_req_delivery_cur1 1546 * dml_pow(2, 10)); 1547 disp_ttu_regs->qos_level_low_wm = 0; 1548 ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14)); 1549 disp_ttu_regs->qos_level_high_wm = (unsigned int) (4.0 * (double) htotal 1550 * ref_freq_to_pix_freq); 1551 /*ASSERT(disp_ttu_regs->qos_level_high_wm < dml_pow(2, 14));*/ 1552 1553 disp_ttu_regs->qos_level_flip = 14; 1554 disp_ttu_regs->qos_level_fixed_l = 8; 1555 disp_ttu_regs->qos_level_fixed_c = 8; 1556 disp_ttu_regs->qos_level_fixed_cur0 = 8; 1557 disp_ttu_regs->qos_ramp_disable_l = 0; 1558 disp_ttu_regs->qos_ramp_disable_c = 0; 1559 disp_ttu_regs->qos_ramp_disable_cur0 = 0; 1560 1561 disp_ttu_regs->min_ttu_vblank = min_ttu_vblank * refclk_freq_in_mhz; 1562 ASSERT(disp_ttu_regs->min_ttu_vblank < dml_pow(2, 24)); 1563 1564 print__ttu_regs_st(mode_lib, *disp_ttu_regs); 1565 print__dlg_regs_st(mode_lib, *disp_dlg_regs); 1566 } 1567 1568 void dml20v2_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib, 1569 display_dlg_regs_st *dlg_regs, 1570 display_ttu_regs_st *ttu_regs, 1571 display_e2e_pipe_params_st *e2e_pipe_param, 1572 const unsigned int num_pipes, 1573 const unsigned int pipe_idx, 1574 const bool cstate_en, 1575 const bool pstate_en, 1576 const bool vm_en, 1577 const bool ignore_viewport_pos, 1578 const bool immediate_flip_support) 1579 { 1580 display_rq_params_st rq_param = {0}; 1581 display_dlg_sys_params_st dlg_sys_param = {0}; 1582 1583 // Get watermark and Tex. 1584 dlg_sys_param.t_urg_wm_us = get_wm_urgent(mode_lib, e2e_pipe_param, num_pipes); 1585 dlg_sys_param.deepsleep_dcfclk_mhz = get_clk_dcf_deepsleep(mode_lib, 1586 e2e_pipe_param, 1587 num_pipes); 1588 dlg_sys_param.t_extra_us = get_urgent_extra_latency(mode_lib, e2e_pipe_param, num_pipes); 1589 dlg_sys_param.mem_trip_us = get_wm_memory_trip(mode_lib, e2e_pipe_param, num_pipes); 1590 dlg_sys_param.t_mclk_wm_us = get_wm_dram_clock_change(mode_lib, e2e_pipe_param, num_pipes); 1591 dlg_sys_param.t_sr_wm_us = get_wm_stutter_enter_exit(mode_lib, e2e_pipe_param, num_pipes); 1592 dlg_sys_param.total_flip_bw = get_total_immediate_flip_bw(mode_lib, 1593 e2e_pipe_param, 1594 num_pipes); 1595 dlg_sys_param.total_flip_bytes = get_total_immediate_flip_bytes(mode_lib, 1596 e2e_pipe_param, 1597 num_pipes); 1598 dlg_sys_param.t_srx_delay_us = mode_lib->ip.dcfclk_cstate_latency 1599 / dlg_sys_param.deepsleep_dcfclk_mhz; // TODO: Deprecated 1600 1601 print__dlg_sys_params_st(mode_lib, dlg_sys_param); 1602 1603 // system parameter calculation done 1604 1605 dml_print("DML_DLG: Calculation for pipe[%d] start\n\n", pipe_idx); 1606 dml20v2_rq_dlg_get_rq_params(mode_lib, &rq_param, e2e_pipe_param[pipe_idx].pipe.src); 1607 dml20v2_rq_dlg_get_dlg_params(mode_lib, 1608 e2e_pipe_param, 1609 num_pipes, 1610 pipe_idx, 1611 dlg_regs, 1612 ttu_regs, 1613 rq_param.dlg, 1614 dlg_sys_param, 1615 cstate_en, 1616 pstate_en); 1617 dml_print("DML_DLG: Calculation for pipe[%d] end\n", pipe_idx); 1618 } 1619 1620 static void calculate_ttu_cursor(struct display_mode_lib *mode_lib, 1621 double *refcyc_per_req_delivery_pre_cur, 1622 double *refcyc_per_req_delivery_cur, 1623 double refclk_freq_in_mhz, 1624 double ref_freq_to_pix_freq, 1625 double hscale_pixel_rate_l, 1626 double hscl_ratio, 1627 double vratio_pre_l, 1628 double vratio_l, 1629 unsigned int cur_width, 1630 enum cursor_bpp cur_bpp) 1631 { 1632 unsigned int cur_src_width = cur_width; 1633 unsigned int cur_req_size = 0; 1634 unsigned int cur_req_width = 0; 1635 double cur_width_ub = 0.0; 1636 double cur_req_per_width = 0.0; 1637 double hactive_cur = 0.0; 1638 1639 ASSERT(cur_src_width <= 256); 1640 1641 *refcyc_per_req_delivery_pre_cur = 0.0; 1642 *refcyc_per_req_delivery_cur = 0.0; 1643 if (cur_src_width > 0) { 1644 unsigned int cur_bit_per_pixel = 0; 1645 1646 if (cur_bpp == dm_cur_2bit) { 1647 cur_req_size = 64; // byte 1648 cur_bit_per_pixel = 2; 1649 } else { // 32bit 1650 cur_bit_per_pixel = 32; 1651 if (cur_src_width >= 1 && cur_src_width <= 16) 1652 cur_req_size = 64; 1653 else if (cur_src_width >= 17 && cur_src_width <= 31) 1654 cur_req_size = 128; 1655 else 1656 cur_req_size = 256; 1657 } 1658 1659 cur_req_width = (double) cur_req_size / ((double) cur_bit_per_pixel / 8.0); 1660 cur_width_ub = dml_ceil((double) cur_src_width / (double) cur_req_width, 1) 1661 * (double) cur_req_width; 1662 cur_req_per_width = cur_width_ub / (double) cur_req_width; 1663 hactive_cur = (double) cur_src_width / hscl_ratio; // TODO: oswin to think about what to do for cursor 1664 1665 if (vratio_pre_l <= 1.0) { 1666 *refcyc_per_req_delivery_pre_cur = hactive_cur * ref_freq_to_pix_freq 1667 / (double) cur_req_per_width; 1668 } else { 1669 *refcyc_per_req_delivery_pre_cur = (double) refclk_freq_in_mhz 1670 * (double) cur_src_width / hscale_pixel_rate_l 1671 / (double) cur_req_per_width; 1672 } 1673 1674 ASSERT(*refcyc_per_req_delivery_pre_cur < dml_pow(2, 13)); 1675 1676 if (vratio_l <= 1.0) { 1677 *refcyc_per_req_delivery_cur = hactive_cur * ref_freq_to_pix_freq 1678 / (double) cur_req_per_width; 1679 } else { 1680 *refcyc_per_req_delivery_cur = (double) refclk_freq_in_mhz 1681 * (double) cur_src_width / hscale_pixel_rate_l 1682 / (double) cur_req_per_width; 1683 } 1684 1685 dml_print("DML_DLG: %s: cur_req_width = %d\n", 1686 __func__, 1687 cur_req_width); 1688 dml_print("DML_DLG: %s: cur_width_ub = %3.2f\n", 1689 __func__, 1690 cur_width_ub); 1691 dml_print("DML_DLG: %s: cur_req_per_width = %3.2f\n", 1692 __func__, 1693 cur_req_per_width); 1694 dml_print("DML_DLG: %s: hactive_cur = %3.2f\n", 1695 __func__, 1696 hactive_cur); 1697 dml_print("DML_DLG: %s: refcyc_per_req_delivery_pre_cur = %3.2f\n", 1698 __func__, 1699 *refcyc_per_req_delivery_pre_cur); 1700 dml_print("DML_DLG: %s: refcyc_per_req_delivery_cur = %3.2f\n", 1701 __func__, 1702 *refcyc_per_req_delivery_cur); 1703 1704 ASSERT(*refcyc_per_req_delivery_cur < dml_pow(2, 13)); 1705 } 1706 } 1707
Indexes created Thu Oct 02 07:10:07 GMT 2025