1 /* $NetBSD: amdgpu_dmub_srv.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $ */ 2 3 /* 4 * Copyright 2019 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dmub_srv.c,v 1.2 2021/12/18 23:45:07 riastradh Exp $"); 30 31 #include "../inc/dmub_srv.h" 32 #include "dmub_dcn20.h" 33 #include "dmub_dcn21.h" 34 #include "dmub_fw_meta.h" 35 #include "os_types.h" 36 /* 37 * Note: the DMUB service is standalone. No additional headers should be 38 * added below or above this line unless they reside within the DMUB 39 * folder. 40 */ 41 42 /* Alignment for framebuffer memory. */ 43 #define DMUB_FB_ALIGNMENT (1024 * 1024) 44 45 /* Stack size. */ 46 #define DMUB_STACK_SIZE (128 * 1024) 47 48 /* Context size. */ 49 #define DMUB_CONTEXT_SIZE (512 * 1024) 50 51 /* Mailbox size */ 52 #define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE) 53 54 /* Default state size if meta is absent. */ 55 #define DMUB_FW_STATE_SIZE (1024) 56 57 /* Default tracebuffer size if meta is absent. */ 58 #define DMUB_TRACE_BUFFER_SIZE (1024) 59 60 /* Number of windows in use. */ 61 #define DMUB_NUM_WINDOWS (DMUB_WINDOW_6_FW_STATE + 1) 62 /* Base addresses. */ 63 64 #define DMUB_CW0_BASE (0x60000000) 65 #define DMUB_CW1_BASE (0x61000000) 66 #define DMUB_CW3_BASE (0x63000000) 67 #define DMUB_CW5_BASE (0x65000000) 68 #define DMUB_CW6_BASE (0x66000000) 69 70 static inline uint32_t dmub_align(uint32_t val, uint32_t factor) 71 { 72 return (val + factor - 1) / factor * factor; 73 } 74 75 static void dmub_flush_buffer_mem(const struct dmub_fb *fb) 76 { 77 const uint8_t *base = (const uint8_t *)fb->cpu_addr; 78 uint8_t buf[64]; 79 uint32_t pos, end; 80 81 /** 82 * Read 64-byte chunks since we don't want to store a 83 * large temporary buffer for this purpose. 84 */ 85 end = fb->size / sizeof(buf) * sizeof(buf); 86 87 for (pos = 0; pos < end; pos += sizeof(buf)) 88 dmub_memcpy(buf, base + pos, sizeof(buf)); 89 90 /* Read anything leftover into the buffer. */ 91 if (end < fb->size) 92 dmub_memcpy(buf, base + pos, fb->size - end); 93 } 94 95 static const struct dmub_fw_meta_info * 96 dmub_get_fw_meta_info(const uint8_t *fw_bss_data, uint32_t fw_bss_data_size) 97 { 98 const union dmub_fw_meta *meta; 99 100 if (fw_bss_data == NULL) 101 return NULL; 102 103 if (fw_bss_data_size < sizeof(union dmub_fw_meta) + DMUB_FW_META_OFFSET) 104 return NULL; 105 106 meta = (const union dmub_fw_meta *)(fw_bss_data + fw_bss_data_size - 107 DMUB_FW_META_OFFSET - 108 sizeof(union dmub_fw_meta)); 109 110 if (meta->info.magic_value != DMUB_FW_META_MAGIC) 111 return NULL; 112 113 return &meta->info; 114 } 115 116 static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic) 117 { 118 struct dmub_srv_hw_funcs *funcs = &dmub->hw_funcs; 119 120 switch (asic) { 121 case DMUB_ASIC_DCN20: 122 case DMUB_ASIC_DCN21: 123 dmub->regs = &dmub_srv_dcn20_regs; 124 125 funcs->reset = dmub_dcn20_reset; 126 funcs->reset_release = dmub_dcn20_reset_release; 127 funcs->backdoor_load = dmub_dcn20_backdoor_load; 128 funcs->setup_windows = dmub_dcn20_setup_windows; 129 funcs->setup_mailbox = dmub_dcn20_setup_mailbox; 130 funcs->get_inbox1_rptr = dmub_dcn20_get_inbox1_rptr; 131 funcs->set_inbox1_wptr = dmub_dcn20_set_inbox1_wptr; 132 funcs->is_supported = dmub_dcn20_is_supported; 133 funcs->is_hw_init = dmub_dcn20_is_hw_init; 134 135 if (asic == DMUB_ASIC_DCN21) { 136 dmub->regs = &dmub_srv_dcn21_regs; 137 138 funcs->is_auto_load_done = dmub_dcn21_is_auto_load_done; 139 funcs->is_phy_init = dmub_dcn21_is_phy_init; 140 } 141 break; 142 143 default: 144 return false; 145 } 146 147 return true; 148 } 149 150 enum dmub_status dmub_srv_create(struct dmub_srv *dmub, 151 const struct dmub_srv_create_params *params) 152 { 153 enum dmub_status status = DMUB_STATUS_OK; 154 155 dmub_memset(dmub, 0, sizeof(*dmub)); 156 157 dmub->funcs = params->funcs; 158 dmub->user_ctx = params->user_ctx; 159 dmub->asic = params->asic; 160 dmub->is_virtual = params->is_virtual; 161 162 /* Setup asic dependent hardware funcs. */ 163 if (!dmub_srv_hw_setup(dmub, params->asic)) { 164 status = DMUB_STATUS_INVALID; 165 goto cleanup; 166 } 167 168 /* Override (some) hardware funcs based on user params. */ 169 if (params->hw_funcs) { 170 if (params->hw_funcs->get_inbox1_rptr) 171 dmub->hw_funcs.get_inbox1_rptr = 172 params->hw_funcs->get_inbox1_rptr; 173 174 if (params->hw_funcs->set_inbox1_wptr) 175 dmub->hw_funcs.set_inbox1_wptr = 176 params->hw_funcs->set_inbox1_wptr; 177 178 if (params->hw_funcs->is_supported) 179 dmub->hw_funcs.is_supported = 180 params->hw_funcs->is_supported; 181 } 182 183 /* Sanity checks for required hw func pointers. */ 184 if (!dmub->hw_funcs.get_inbox1_rptr || 185 !dmub->hw_funcs.set_inbox1_wptr) { 186 status = DMUB_STATUS_INVALID; 187 goto cleanup; 188 } 189 190 cleanup: 191 if (status == DMUB_STATUS_OK) 192 dmub->sw_init = true; 193 else 194 dmub_srv_destroy(dmub); 195 196 return status; 197 } 198 199 void dmub_srv_destroy(struct dmub_srv *dmub) 200 { 201 dmub_memset(dmub, 0, sizeof(*dmub)); 202 } 203 204 enum dmub_status 205 dmub_srv_calc_region_info(struct dmub_srv *dmub, 206 const struct dmub_srv_region_params *params, 207 struct dmub_srv_region_info *out) 208 { 209 struct dmub_region *inst = &out->regions[DMUB_WINDOW_0_INST_CONST]; 210 struct dmub_region *stack = &out->regions[DMUB_WINDOW_1_STACK]; 211 struct dmub_region *data = &out->regions[DMUB_WINDOW_2_BSS_DATA]; 212 struct dmub_region *bios = &out->regions[DMUB_WINDOW_3_VBIOS]; 213 struct dmub_region *mail = &out->regions[DMUB_WINDOW_4_MAILBOX]; 214 struct dmub_region *trace_buff = &out->regions[DMUB_WINDOW_5_TRACEBUFF]; 215 struct dmub_region *fw_state = &out->regions[DMUB_WINDOW_6_FW_STATE]; 216 const struct dmub_fw_meta_info *fw_info; 217 uint32_t fw_state_size = DMUB_FW_STATE_SIZE; 218 uint32_t trace_buffer_size = DMUB_TRACE_BUFFER_SIZE; 219 220 if (!dmub->sw_init) 221 return DMUB_STATUS_INVALID; 222 223 memset(out, 0, sizeof(*out)); 224 225 out->num_regions = DMUB_NUM_WINDOWS; 226 227 inst->base = 0x0; 228 inst->top = inst->base + params->inst_const_size; 229 230 data->base = dmub_align(inst->top, 256); 231 data->top = data->base + params->bss_data_size; 232 233 /* 234 * All cache windows below should be aligned to the size 235 * of the DMCUB cache line, 64 bytes. 236 */ 237 238 stack->base = dmub_align(data->top, 256); 239 stack->top = stack->base + DMUB_STACK_SIZE + DMUB_CONTEXT_SIZE; 240 241 bios->base = dmub_align(stack->top, 256); 242 bios->top = bios->base + params->vbios_size; 243 244 mail->base = dmub_align(bios->top, 256); 245 mail->top = mail->base + DMUB_MAILBOX_SIZE; 246 247 fw_info = dmub_get_fw_meta_info(params->fw_bss_data, 248 params->bss_data_size); 249 250 if (fw_info) { 251 fw_state_size = fw_info->fw_region_size; 252 trace_buffer_size = fw_info->trace_buffer_size; 253 } 254 255 trace_buff->base = dmub_align(mail->top, 256); 256 trace_buff->top = trace_buff->base + dmub_align(trace_buffer_size, 64); 257 258 fw_state->base = dmub_align(trace_buff->top, 256); 259 fw_state->top = fw_state->base + dmub_align(fw_state_size, 64); 260 261 out->fb_size = dmub_align(fw_state->top, 4096); 262 263 return DMUB_STATUS_OK; 264 } 265 266 enum dmub_status dmub_srv_calc_fb_info(struct dmub_srv *dmub, 267 const struct dmub_srv_fb_params *params, 268 struct dmub_srv_fb_info *out) 269 { 270 uint8_t *cpu_base; 271 uint64_t gpu_base; 272 uint32_t i; 273 274 if (!dmub->sw_init) 275 return DMUB_STATUS_INVALID; 276 277 memset(out, 0, sizeof(*out)); 278 279 if (params->region_info->num_regions != DMUB_NUM_WINDOWS) 280 return DMUB_STATUS_INVALID; 281 282 cpu_base = (uint8_t *)params->cpu_addr; 283 gpu_base = params->gpu_addr; 284 285 for (i = 0; i < DMUB_NUM_WINDOWS; ++i) { 286 const struct dmub_region *reg = 287 ¶ms->region_info->regions[i]; 288 289 out->fb[i].cpu_addr = cpu_base + reg->base; 290 out->fb[i].gpu_addr = gpu_base + reg->base; 291 out->fb[i].size = reg->top - reg->base; 292 } 293 294 out->num_fb = DMUB_NUM_WINDOWS; 295 296 return DMUB_STATUS_OK; 297 } 298 299 enum dmub_status dmub_srv_has_hw_support(struct dmub_srv *dmub, 300 bool *is_supported) 301 { 302 *is_supported = false; 303 304 if (!dmub->sw_init) 305 return DMUB_STATUS_INVALID; 306 307 if (dmub->hw_funcs.is_supported) 308 *is_supported = dmub->hw_funcs.is_supported(dmub); 309 310 return DMUB_STATUS_OK; 311 } 312 313 enum dmub_status dmub_srv_is_hw_init(struct dmub_srv *dmub, bool *is_hw_init) 314 { 315 *is_hw_init = false; 316 317 if (!dmub->sw_init) 318 return DMUB_STATUS_INVALID; 319 320 if (!dmub->hw_init) 321 return DMUB_STATUS_OK; 322 323 if (dmub->hw_funcs.is_hw_init) 324 *is_hw_init = dmub->hw_funcs.is_hw_init(dmub); 325 326 return DMUB_STATUS_OK; 327 } 328 329 enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub, 330 const struct dmub_srv_hw_params *params) 331 { 332 struct dmub_fb *inst_fb = params->fb[DMUB_WINDOW_0_INST_CONST]; 333 struct dmub_fb *stack_fb = params->fb[DMUB_WINDOW_1_STACK]; 334 struct dmub_fb *data_fb = params->fb[DMUB_WINDOW_2_BSS_DATA]; 335 struct dmub_fb *bios_fb = params->fb[DMUB_WINDOW_3_VBIOS]; 336 struct dmub_fb *mail_fb = params->fb[DMUB_WINDOW_4_MAILBOX]; 337 struct dmub_fb *tracebuff_fb = params->fb[DMUB_WINDOW_5_TRACEBUFF]; 338 struct dmub_fb *fw_state_fb = params->fb[DMUB_WINDOW_6_FW_STATE]; 339 340 struct dmub_rb_init_params rb_params; 341 struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6; 342 struct dmub_region inbox1; 343 344 if (!dmub->sw_init) 345 return DMUB_STATUS_INVALID; 346 347 dmub->fb_base = params->fb_base; 348 dmub->fb_offset = params->fb_offset; 349 dmub->psp_version = params->psp_version; 350 351 if (inst_fb && data_fb) { 352 cw0.offset.quad_part = inst_fb->gpu_addr; 353 cw0.region.base = DMUB_CW0_BASE; 354 cw0.region.top = cw0.region.base + inst_fb->size - 1; 355 356 cw1.offset.quad_part = stack_fb->gpu_addr; 357 cw1.region.base = DMUB_CW1_BASE; 358 cw1.region.top = cw1.region.base + stack_fb->size - 1; 359 360 /** 361 * Read back all the instruction memory so we don't hang the 362 * DMCUB when backdoor loading if the write from x86 hasn't been 363 * flushed yet. This only occurs in backdoor loading. 364 */ 365 dmub_flush_buffer_mem(inst_fb); 366 367 if (params->load_inst_const && dmub->hw_funcs.backdoor_load) 368 dmub->hw_funcs.backdoor_load(dmub, &cw0, &cw1); 369 } 370 371 if (dmub->hw_funcs.reset) 372 dmub->hw_funcs.reset(dmub); 373 374 if (inst_fb && data_fb && bios_fb && mail_fb && tracebuff_fb && 375 fw_state_fb) { 376 cw2.offset.quad_part = data_fb->gpu_addr; 377 cw2.region.base = DMUB_CW0_BASE + inst_fb->size; 378 cw2.region.top = cw2.region.base + data_fb->size; 379 380 cw3.offset.quad_part = bios_fb->gpu_addr; 381 cw3.region.base = DMUB_CW3_BASE; 382 cw3.region.top = cw3.region.base + bios_fb->size; 383 384 cw4.offset.quad_part = mail_fb->gpu_addr; 385 cw4.region.base = cw3.region.top + 1; 386 cw4.region.top = cw4.region.base + mail_fb->size; 387 388 inbox1.base = cw4.region.base; 389 inbox1.top = cw4.region.top; 390 391 cw5.offset.quad_part = tracebuff_fb->gpu_addr; 392 cw5.region.base = DMUB_CW5_BASE; 393 cw5.region.top = cw5.region.base + tracebuff_fb->size; 394 395 cw6.offset.quad_part = fw_state_fb->gpu_addr; 396 cw6.region.base = DMUB_CW6_BASE; 397 cw6.region.top = cw6.region.base + fw_state_fb->size; 398 399 dmub->fw_state = fw_state_fb->cpu_addr; 400 401 if (dmub->hw_funcs.setup_windows) 402 dmub->hw_funcs.setup_windows(dmub, &cw2, &cw3, &cw4, 403 &cw5, &cw6); 404 405 if (dmub->hw_funcs.setup_mailbox) 406 dmub->hw_funcs.setup_mailbox(dmub, &inbox1); 407 } 408 409 if (mail_fb) { 410 dmub_memset(&rb_params, 0, sizeof(rb_params)); 411 rb_params.ctx = dmub; 412 rb_params.base_address = mail_fb->cpu_addr; 413 rb_params.capacity = DMUB_RB_SIZE; 414 415 dmub_rb_init(&dmub->inbox1_rb, &rb_params); 416 } 417 418 if (dmub->hw_funcs.reset_release) 419 dmub->hw_funcs.reset_release(dmub); 420 421 dmub->hw_init = true; 422 423 return DMUB_STATUS_OK; 424 } 425 426 enum dmub_status dmub_srv_hw_reset(struct dmub_srv *dmub) 427 { 428 if (!dmub->sw_init) 429 return DMUB_STATUS_INVALID; 430 431 if (dmub->hw_init == false) 432 return DMUB_STATUS_OK; 433 434 if (dmub->hw_funcs.reset) 435 dmub->hw_funcs.reset(dmub); 436 437 dmub->hw_init = false; 438 439 return DMUB_STATUS_OK; 440 } 441 442 enum dmub_status dmub_srv_cmd_queue(struct dmub_srv *dmub, 443 const struct dmub_cmd_header *cmd) 444 { 445 if (!dmub->hw_init) 446 return DMUB_STATUS_INVALID; 447 448 if (dmub_rb_push_front(&dmub->inbox1_rb, cmd)) 449 return DMUB_STATUS_OK; 450 451 return DMUB_STATUS_QUEUE_FULL; 452 } 453 454 enum dmub_status dmub_srv_cmd_execute(struct dmub_srv *dmub) 455 { 456 if (!dmub->hw_init) 457 return DMUB_STATUS_INVALID; 458 459 /** 460 * Read back all the queued commands to ensure that they've 461 * been flushed to framebuffer memory. Otherwise DMCUB might 462 * read back stale, fully invalid or partially invalid data. 463 */ 464 dmub_rb_flush_pending(&dmub->inbox1_rb); 465 466 dmub->hw_funcs.set_inbox1_wptr(dmub, dmub->inbox1_rb.wrpt); 467 return DMUB_STATUS_OK; 468 } 469 470 enum dmub_status dmub_srv_wait_for_auto_load(struct dmub_srv *dmub, 471 uint32_t timeout_us) 472 { 473 uint32_t i; 474 475 if (!dmub->hw_init) 476 return DMUB_STATUS_INVALID; 477 478 if (!dmub->hw_funcs.is_auto_load_done) 479 return DMUB_STATUS_OK; 480 481 for (i = 0; i <= timeout_us; i += 100) { 482 if (dmub->hw_funcs.is_auto_load_done(dmub)) 483 return DMUB_STATUS_OK; 484 485 udelay(100); 486 } 487 488 return DMUB_STATUS_TIMEOUT; 489 } 490 491 enum dmub_status dmub_srv_wait_for_phy_init(struct dmub_srv *dmub, 492 uint32_t timeout_us) 493 { 494 uint32_t i = 0; 495 496 if (!dmub->hw_init) 497 return DMUB_STATUS_INVALID; 498 499 if (!dmub->hw_funcs.is_phy_init) 500 return DMUB_STATUS_OK; 501 502 for (i = 0; i <= timeout_us; i += 10) { 503 if (dmub->hw_funcs.is_phy_init(dmub)) 504 return DMUB_STATUS_OK; 505 506 udelay(10); 507 } 508 509 return DMUB_STATUS_TIMEOUT; 510 } 511 512 enum dmub_status dmub_srv_wait_for_idle(struct dmub_srv *dmub, 513 uint32_t timeout_us) 514 { 515 uint32_t i; 516 517 if (!dmub->hw_init) 518 return DMUB_STATUS_INVALID; 519 520 for (i = 0; i <= timeout_us; ++i) { 521 dmub->inbox1_rb.rptr = dmub->hw_funcs.get_inbox1_rptr(dmub); 522 if (dmub_rb_empty(&dmub->inbox1_rb)) 523 return DMUB_STATUS_OK; 524 525 udelay(1); 526 } 527 528 return DMUB_STATUS_TIMEOUT; 529 } 530
Indexes created Sat Sep 20 22:09:52 GMT 2025