| /src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/sprd/ |
| sharkl3.dtsi | 123 dpll: dpll { label in label:soc.anlg_phy_g7_regs
124 compatible = "sprd,sc9863a-dpll";
|
| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dvo.c | 452 u32 dpll[I915_MAX_PIPES]; local in function:intel_dvo_init
489 dpll[pipe] = I915_READ(DPLL(pipe));
490 I915_WRITE(DPLL(pipe), dpll[pipe] | DPLL_DVO_2X_MODE);
497 I915_WRITE(DPLL(pipe), dpll[pipe]);
|
| intel_dpll_mgr.h | 51 * enum intel_dpll_id - possible DPLL ids
53 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
57 * @DPLL_ID_PRIVATE: non-shared dpll in use
62 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
66 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
172 u32 dpll; member in struct:intel_dpll_hw_state
183 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
186 * the DPLL.
218 * struct intel_shared_dpll_state - hold the DPLL atomic stat
[all...] |
| intel_display_types.h | 447 struct dpll { struct
898 /* Settings for the intel dpll used on pretty much everything but
900 struct dpll dpll; member in struct:intel_crtc_state
902 /* Selected dpll when shared or NULL. */
905 /* Actual register state of the dpll, for shared dpll cross-checking. */
934 * Frequence the dpll for the port should run at. Differs from the
|
| intel_dp.c | 92 struct dpll dpll; member in struct:dp_link_dpll
791 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
794 * The DPLL for the pipe must be enabled for this to work.
802 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
1816 pipe_config->dpll = divisor[i].dpll;
|
| intel_display.c | 580 static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
592 static u32 i9xx_dpll_compute_m(struct dpll *dpll)
594 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
597 static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
609 static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
621 int chv_calc_dpll_params(int refclk, struct dpll *clock)
642 const struct dpll *clock)
715 int target, int refclk, struct dpll *match_clock
1511 u32 dpll = crtc_state->dpll_hw_state.dpll; local in function:i9xx_enable_pll
8480 u32 dpll; local in function:i9xx_compute_dpll
8554 u32 dpll; local in function:i8xx_compute_dpll
10025 u32 dpll, fp, fp2; local in function:ilk_compute_dpll
11878 u32 dpll = pipe_config->dpll_hw_state.dpll; local in function:i9xx_pll_refclk
11897 u32 dpll = pipe_config->dpll_hw_state.dpll; local in function:i9xx_crtc_clock_get
17703 u32 dpll, fp; local in function:i830_enable_pipe
[all...] |
