| /src/sys/external/bsd/drm2/dist/drm/i915/display/ |
| intel_dpll_mgr.c | 474 &crtc_state->dpll_hw_state,
484 pll, &crtc_state->dpll_hw_state);
494 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
836 crtc_state->dpll_hw_state.wrpll = val;
839 &crtc_state->dpll_hw_state,
888 memset(&crtc_state->dpll_hw_state, 0,
889 sizeof(crtc_state->dpll_hw_state));
899 crtc_state->dpll_hw_state.spll =
903 &crtc_state->dpll_hw_state,
913 pll, &crtc_state->dpll_hw_state);
1809 struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state; local in function:bxt_ddi_set_dpll_hw_state
[all...] |
| intel_display_types.h | 906 struct intel_dpll_hw_state dpll_hw_state; member in struct:intel_crtc_state
910 * setting shared_dpll and dpll_hw_state to one of these reserved ones.
|
| intel_display.c | 1404 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1423 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1426 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1454 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1472 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1483 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1485 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1493 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1511 u32 dpll = crtc_state->dpll_hw_state.dpll;
1534 crtc_state->dpll_hw_state.dpll_md)
14056 struct intel_dpll_hw_state dpll_hw_state; local in function:verify_single_dpll_state
[all...] |
