1 /* $NetBSD: amdgpu_dcn10_dpp.c,v 1.3 2021/12/19 11:24:00 riastradh Exp $ */ 2 3 /* 4 * Copyright 2016 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #include <sys/cdefs.h> 29 __KERNEL_RCSID(0, "$NetBSD: amdgpu_dcn10_dpp.c,v 1.3 2021/12/19 11:24:00 riastradh Exp $"); 30 31 #include "dm_services.h" 32 33 #include "core_types.h" 34 35 #include "reg_helper.h" 36 #include "dcn10_dpp.h" 37 #include "basics/conversion.h" 38 39 #define NUM_PHASES 64 40 #define HORZ_MAX_TAPS 8 41 #define VERT_MAX_TAPS 8 42 43 #define BLACK_OFFSET_RGB_Y 0x0 44 #define BLACK_OFFSET_CBCR 0x8000 45 46 #define REG(reg)\ 47 dpp->tf_regs->reg 48 49 #define CTX \ 50 dpp->base.ctx 51 52 #undef FN 53 #define FN(reg_name, field_name) \ 54 dpp->tf_shift->field_name, dpp->tf_mask->field_name 55 56 enum pixel_format_description { 57 PIXEL_FORMAT_FIXED = 0, 58 PIXEL_FORMAT_FIXED16, 59 PIXEL_FORMAT_FLOAT 60 61 }; 62 63 enum dcn10_coef_filter_type_sel { 64 SCL_COEF_LUMA_VERT_FILTER = 0, 65 SCL_COEF_LUMA_HORZ_FILTER = 1, 66 SCL_COEF_CHROMA_VERT_FILTER = 2, 67 SCL_COEF_CHROMA_HORZ_FILTER = 3, 68 SCL_COEF_ALPHA_VERT_FILTER = 4, 69 SCL_COEF_ALPHA_HORZ_FILTER = 5 70 }; 71 72 enum dscl_autocal_mode { 73 AUTOCAL_MODE_OFF = 0, 74 75 /* Autocal calculate the scaling ratio and initial phase and the 76 * DSCL_MODE_SEL must be set to 1 77 */ 78 AUTOCAL_MODE_AUTOSCALE = 1, 79 /* Autocal perform auto centering without replication and the 80 * DSCL_MODE_SEL must be set to 0 81 */ 82 AUTOCAL_MODE_AUTOCENTER = 2, 83 /* Autocal perform auto centering and auto replication and the 84 * DSCL_MODE_SEL must be set to 0 85 */ 86 AUTOCAL_MODE_AUTOREPLICATE = 3 87 }; 88 89 enum dscl_mode_sel { 90 DSCL_MODE_SCALING_444_BYPASS = 0, 91 DSCL_MODE_SCALING_444_RGB_ENABLE = 1, 92 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2, 93 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3, 94 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4, 95 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5, 96 DSCL_MODE_DSCL_BYPASS = 6 97 }; 98 99 void dpp_read_state(struct dpp *dpp_base, 100 struct dcn_dpp_state *s) 101 { 102 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 103 104 REG_GET(DPP_CONTROL, 105 DPP_CLOCK_ENABLE, &s->is_enabled); 106 REG_GET(CM_IGAM_CONTROL, 107 CM_IGAM_LUT_MODE, &s->igam_lut_mode); 108 REG_GET(CM_IGAM_CONTROL, 109 CM_IGAM_INPUT_FORMAT, &s->igam_input_format); 110 REG_GET(CM_DGAM_CONTROL, 111 CM_DGAM_LUT_MODE, &s->dgam_lut_mode); 112 REG_GET(CM_RGAM_CONTROL, 113 CM_RGAM_LUT_MODE, &s->rgam_lut_mode); 114 REG_GET(CM_GAMUT_REMAP_CONTROL, 115 CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode); 116 117 if (s->gamut_remap_mode) { 118 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12); 119 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14); 120 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22); 121 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24); 122 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32); 123 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34); 124 } 125 } 126 127 /* Program gamut remap in bypass mode */ 128 void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp) 129 { 130 REG_SET(CM_GAMUT_REMAP_CONTROL, 0, 131 CM_GAMUT_REMAP_MODE, 0); 132 /* Gamut remap in bypass */ 133 } 134 135 #define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19)) 136 137 bool dpp1_get_optimal_number_of_taps( 138 struct dpp *dpp, 139 struct scaler_data *scl_data, 140 const struct scaling_taps *in_taps) 141 { 142 uint32_t pixel_width __unused; 143 144 if (scl_data->viewport.width > scl_data->recout.width) 145 pixel_width = scl_data->recout.width; 146 else 147 pixel_width = scl_data->viewport.width; 148 149 /* Some ASICs does not support FP16 scaling, so we reject modes require this*/ 150 if (scl_data->format == PIXEL_FORMAT_FP16 && 151 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT && 152 scl_data->ratios.horz.value != dc_fixpt_one.value && 153 scl_data->ratios.vert.value != dc_fixpt_one.value) 154 return false; 155 156 if (scl_data->viewport.width > scl_data->h_active && 157 dpp->ctx->dc->debug.max_downscale_src_width != 0 && 158 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) 159 return false; 160 161 /* TODO: add lb check */ 162 163 /* No support for programming ratio of 4, drop to 3.99999.. */ 164 if (scl_data->ratios.horz.value == (4ll << 32)) 165 scl_data->ratios.horz.value--; 166 if (scl_data->ratios.vert.value == (4ll << 32)) 167 scl_data->ratios.vert.value--; 168 if (scl_data->ratios.horz_c.value == (4ll << 32)) 169 scl_data->ratios.horz_c.value--; 170 if (scl_data->ratios.vert_c.value == (4ll << 32)) 171 scl_data->ratios.vert_c.value--; 172 173 /* Set default taps if none are provided */ 174 if (in_taps->h_taps == 0) 175 scl_data->taps.h_taps = 4; 176 else 177 scl_data->taps.h_taps = in_taps->h_taps; 178 if (in_taps->v_taps == 0) 179 scl_data->taps.v_taps = 4; 180 else 181 scl_data->taps.v_taps = in_taps->v_taps; 182 if (in_taps->v_taps_c == 0) 183 scl_data->taps.v_taps_c = 2; 184 else 185 scl_data->taps.v_taps_c = in_taps->v_taps_c; 186 if (in_taps->h_taps_c == 0) 187 scl_data->taps.h_taps_c = 2; 188 /* Only 1 and even h_taps_c are supported by hw */ 189 else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) 190 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; 191 else 192 scl_data->taps.h_taps_c = in_taps->h_taps_c; 193 194 if (!dpp->ctx->dc->debug.always_scale) { 195 if (IDENTITY_RATIO(scl_data->ratios.horz)) 196 scl_data->taps.h_taps = 1; 197 if (IDENTITY_RATIO(scl_data->ratios.vert)) 198 scl_data->taps.v_taps = 1; 199 if (IDENTITY_RATIO(scl_data->ratios.horz_c)) 200 scl_data->taps.h_taps_c = 1; 201 if (IDENTITY_RATIO(scl_data->ratios.vert_c)) 202 scl_data->taps.v_taps_c = 1; 203 } 204 205 return true; 206 } 207 208 void dpp_reset(struct dpp *dpp_base) 209 { 210 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 211 212 dpp->filter_h_c = NULL; 213 dpp->filter_v_c = NULL; 214 dpp->filter_h = NULL; 215 dpp->filter_v = NULL; 216 217 memset(&dpp->scl_data, 0, sizeof(dpp->scl_data)); 218 memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data)); 219 } 220 221 222 223 static void dpp1_cm_set_regamma_pwl( 224 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode) 225 { 226 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 227 uint32_t re_mode = 0; 228 229 switch (mode) { 230 case OPP_REGAMMA_BYPASS: 231 re_mode = 0; 232 break; 233 case OPP_REGAMMA_SRGB: 234 re_mode = 1; 235 break; 236 case OPP_REGAMMA_XVYCC: 237 re_mode = 2; 238 break; 239 case OPP_REGAMMA_USER: 240 re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3; 241 if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0) 242 break; 243 244 dpp1_cm_power_on_regamma_lut(dpp_base, true); 245 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe); 246 247 if (dpp->is_write_to_ram_a_safe) 248 dpp1_cm_program_regamma_luta_settings(dpp_base, params); 249 else 250 dpp1_cm_program_regamma_lutb_settings(dpp_base, params); 251 252 dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted, 253 params->hw_points_num); 254 dpp->pwl_data = *params; 255 256 re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4; 257 dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe; 258 break; 259 default: 260 break; 261 } 262 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode); 263 } 264 265 static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\ 266 enum pixel_format_description *fmt) 267 { 268 269 if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F || 270 input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) 271 *fmt = PIXEL_FORMAT_FLOAT; 272 else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616) 273 *fmt = PIXEL_FORMAT_FIXED16; 274 else 275 *fmt = PIXEL_FORMAT_FIXED; 276 } 277 278 static void dpp1_set_degamma_format_float( 279 struct dpp *dpp_base, 280 bool is_float) 281 { 282 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 283 284 if (is_float) { 285 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3); 286 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1); 287 } else { 288 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2); 289 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0); 290 } 291 } 292 293 void dpp1_cnv_setup ( 294 struct dpp *dpp_base, 295 enum surface_pixel_format format, 296 enum expansion_mode mode, 297 struct dc_csc_transform input_csc_color_matrix, 298 enum dc_color_space input_color_space, 299 struct cnv_alpha_2bit_lut *alpha_2bit_lut) 300 { 301 uint32_t pixel_format; 302 uint32_t alpha_en; 303 enum pixel_format_description fmt ; 304 enum dc_color_space color_space; 305 enum dcn10_input_csc_select select; 306 bool is_float; 307 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 308 bool force_disable_cursor = false; 309 struct out_csc_color_matrix tbl_entry; 310 int i = 0; 311 312 dpp1_setup_format_flags(format, &fmt); 313 alpha_en = 1; 314 pixel_format = 0; 315 color_space = COLOR_SPACE_SRGB; 316 select = INPUT_CSC_SELECT_BYPASS; 317 is_float = false; 318 319 switch (fmt) { 320 case PIXEL_FORMAT_FIXED: 321 case PIXEL_FORMAT_FIXED16: 322 /*when output is float then FORMAT_CONTROL__OUTPUT_FP=1*/ 323 REG_SET_3(FORMAT_CONTROL, 0, 324 CNVC_BYPASS, 0, 325 FORMAT_EXPANSION_MODE, mode, 326 OUTPUT_FP, 0); 327 break; 328 case PIXEL_FORMAT_FLOAT: 329 REG_SET_3(FORMAT_CONTROL, 0, 330 CNVC_BYPASS, 0, 331 FORMAT_EXPANSION_MODE, mode, 332 OUTPUT_FP, 1); 333 is_float = true; 334 break; 335 default: 336 337 break; 338 } 339 340 dpp1_set_degamma_format_float(dpp_base, is_float); 341 342 switch (format) { 343 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555: 344 pixel_format = 1; 345 break; 346 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 347 pixel_format = 3; 348 alpha_en = 0; 349 break; 350 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 351 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 352 pixel_format = 8; 353 break; 354 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 355 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 356 pixel_format = 10; 357 break; 358 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr: 359 force_disable_cursor = false; 360 pixel_format = 65; 361 color_space = COLOR_SPACE_YCBCR709; 362 select = INPUT_CSC_SELECT_ICSC; 363 break; 364 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb: 365 force_disable_cursor = true; 366 pixel_format = 64; 367 color_space = COLOR_SPACE_YCBCR709; 368 select = INPUT_CSC_SELECT_ICSC; 369 break; 370 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr: 371 force_disable_cursor = true; 372 pixel_format = 67; 373 color_space = COLOR_SPACE_YCBCR709; 374 select = INPUT_CSC_SELECT_ICSC; 375 break; 376 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb: 377 force_disable_cursor = true; 378 pixel_format = 66; 379 color_space = COLOR_SPACE_YCBCR709; 380 select = INPUT_CSC_SELECT_ICSC; 381 break; 382 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 383 pixel_format = 22; 384 break; 385 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F: 386 pixel_format = 24; 387 break; 388 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 389 pixel_format = 25; 390 break; 391 default: 392 break; 393 } 394 395 /* Set default color space based on format if none is given. */ 396 color_space = input_color_space ? input_color_space : color_space; 397 398 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, 399 CNVC_SURFACE_PIXEL_FORMAT, pixel_format); 400 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en); 401 402 // if input adjustments exist, program icsc with those values 403 404 if (input_csc_color_matrix.enable_adjustment 405 == true) { 406 for (i = 0; i < 12; i++) 407 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i]; 408 409 tbl_entry.color_space = color_space; 410 411 if (color_space >= COLOR_SPACE_YCBCR601) 412 select = INPUT_CSC_SELECT_ICSC; 413 else 414 select = INPUT_CSC_SELECT_BYPASS; 415 416 dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry); 417 } else 418 dpp1_program_input_csc(dpp_base, color_space, select, NULL); 419 420 if (force_disable_cursor) { 421 REG_UPDATE(CURSOR_CONTROL, 422 CURSOR_ENABLE, 0); 423 REG_UPDATE(CURSOR0_CONTROL, 424 CUR0_ENABLE, 0); 425 } 426 } 427 428 void dpp1_set_cursor_attributes( 429 struct dpp *dpp_base, 430 struct dc_cursor_attributes *cursor_attributes) 431 { 432 enum dc_cursor_color_format color_format = cursor_attributes->color_format; 433 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 434 435 REG_UPDATE_2(CURSOR0_CONTROL, 436 CUR0_MODE, color_format, 437 CUR0_EXPANSION_MODE, 0); 438 439 if (color_format == CURSOR_MODE_MONO) { 440 /* todo: clarify what to program these to */ 441 REG_UPDATE(CURSOR0_COLOR0, 442 CUR0_COLOR0, 0x00000000); 443 REG_UPDATE(CURSOR0_COLOR1, 444 CUR0_COLOR1, 0xFFFFFFFF); 445 } 446 } 447 448 449 void dpp1_set_cursor_position( 450 struct dpp *dpp_base, 451 const struct dc_cursor_position *pos, 452 const struct dc_cursor_mi_param *param, 453 uint32_t width, 454 uint32_t height) 455 { 456 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 457 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x; 458 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y; 459 uint32_t cur_en = pos->enable ? 1 : 0; 460 461 // Cursor width/height and hotspots need to be rotated for offset calculation 462 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) { 463 swap(width, height); 464 if (param->rotation == ROTATION_ANGLE_90) { 465 src_x_offset = pos->x - pos->y_hotspot - param->viewport.x; 466 src_y_offset = pos->y - pos->x_hotspot - param->viewport.y; 467 } 468 } else if (param->rotation == ROTATION_ANGLE_180) { 469 src_x_offset = pos->x - param->viewport.x; 470 src_y_offset = pos->y - param->viewport.y; 471 } 472 473 474 if (src_x_offset >= (int)param->viewport.width) 475 cur_en = 0; /* not visible beyond right edge*/ 476 477 if (src_x_offset + (int)width <= 0) 478 cur_en = 0; /* not visible beyond left edge*/ 479 480 if (src_y_offset >= (int)param->viewport.height) 481 cur_en = 0; /* not visible beyond bottom edge*/ 482 483 if (src_y_offset + (int)height <= 0) 484 cur_en = 0; /* not visible beyond top edge*/ 485 486 REG_UPDATE(CURSOR0_CONTROL, 487 CUR0_ENABLE, cur_en); 488 489 } 490 491 void dpp1_cnv_set_optional_cursor_attributes( 492 struct dpp *dpp_base, 493 struct dpp_cursor_attributes *attr) 494 { 495 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 496 497 if (attr) { 498 REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, attr->bias); 499 REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, attr->scale); 500 } 501 } 502 503 void dpp1_dppclk_control( 504 struct dpp *dpp_base, 505 bool dppclk_div, 506 bool enable) 507 { 508 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base); 509 510 if (enable) { 511 if (dpp->tf_mask->DPPCLK_RATE_CONTROL) 512 REG_UPDATE_2(DPP_CONTROL, 513 DPPCLK_RATE_CONTROL, dppclk_div, 514 DPP_CLOCK_ENABLE, 1); 515 else 516 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1); 517 } else 518 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0); 519 } 520 521 static const struct dpp_funcs dcn10_dpp_funcs = { 522 .dpp_read_state = dpp_read_state, 523 .dpp_reset = dpp_reset, 524 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale, 525 .dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps, 526 .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap, 527 .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment, 528 .dpp_set_csc_default = dpp1_cm_set_output_csc_default, 529 .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut, 530 .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut, 531 .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut, 532 .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings, 533 .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings, 534 .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl, 535 .dpp_program_bias_and_scale = dpp1_program_bias_and_scale, 536 .dpp_set_degamma = dpp1_set_degamma, 537 .dpp_program_input_lut = dpp1_program_input_lut, 538 .dpp_program_degamma_pwl = dpp1_set_degamma_pwl, 539 .dpp_setup = dpp1_cnv_setup, 540 .dpp_full_bypass = dpp1_full_bypass, 541 .set_cursor_attributes = dpp1_set_cursor_attributes, 542 .set_cursor_position = dpp1_set_cursor_position, 543 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes, 544 .dpp_dppclk_control = dpp1_dppclk_control, 545 .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier, 546 .dpp_program_blnd_lut = NULL, 547 .dpp_program_shaper_lut = NULL, 548 .dpp_program_3dlut = NULL 549 }; 550 551 static struct dpp_caps dcn10_dpp_cap = { 552 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT, 553 .dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions, 554 }; 555 556 /*****************************************/ 557 /* Constructor, Destructor */ 558 /*****************************************/ 559 560 void dpp1_construct( 561 struct dcn10_dpp *dpp, 562 struct dc_context *ctx, 563 uint32_t inst, 564 const struct dcn_dpp_registers *tf_regs, 565 const struct dcn_dpp_shift *tf_shift, 566 const struct dcn_dpp_mask *tf_mask) 567 { 568 dpp->base.ctx = ctx; 569 570 dpp->base.inst = inst; 571 dpp->base.funcs = &dcn10_dpp_funcs; 572 dpp->base.caps = &dcn10_dpp_cap; 573 574 dpp->tf_regs = tf_regs; 575 dpp->tf_shift = tf_shift; 576 dpp->tf_mask = tf_mask; 577 578 dpp->lb_pixel_depth_supported = 579 LB_PIXEL_DEPTH_18BPP | 580 LB_PIXEL_DEPTH_24BPP | 581 LB_PIXEL_DEPTH_30BPP; 582 583 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY; 584 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES; /*0x1404*/ 585 } 586
Indexes created Sun Sep 21 15:09:59 GMT 2025