| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/ |
| amdgpu_dml1_display_rq_dlg_calc.c | 602 unsigned int dpte_row_height; local in function:get_surf_rq_param
796 dpte_row_height = 0;
846 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
849 * the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
852 data_pitch * dpte_row_height - 1,
871 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
883 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
938 if (rq_dlg_param->dpte_row_height != func_dpte_row_height) {
940 "MISMATCH: rq_dlg_param->dpte_row_height = %d",
941 rq_dlg_param->dpte_row_height);
[all...] |
| display_mode_structs.h | 387 unsigned int dpte_row_height; member in struct:_vcs_dpi_display_data_rq_dlg_params_st
|
| display_mode_vba.h | 586 unsigned int dpte_row_height[DC__NUM_DPP__MAX]; member in struct:vba_vars_st
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn20/ |
| amdgpu_display_rq_dlg_calc_20.c | 203 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
208 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
595 unsigned int dpte_row_height; local in function:get_meta_and_pte_attr
611 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
612 dpte_row_height = 1 << log2_dpte_row_height;
613 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
639 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
1140 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1141 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
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| amdgpu_display_rq_dlg_calc_20v2.c | 203 rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
208 rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
595 unsigned int dpte_row_height; local in function:get_meta_and_pte_attr
611 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
612 dpte_row_height = 1 << log2_dpte_row_height;
613 dpte_row_width_ub = dml_round_to_multiple(data_pitch * dpte_row_height - 1,
639 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
1141 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1142 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
|
| /src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dml/dcn21/ |
| amdgpu_display_rq_dlg_calc_21.c | 182 dml_log2(rq_param.dlg.rq_l.dpte_row_height),
188 dml_log2(rq_param.dlg.rq_c.dpte_row_height),
593 unsigned int dpte_row_height; local in function:get_meta_and_pte_attr
612 // the dpte_row_width_ub is the upper bound of data_pitch*dpte_row_height in elements with this unique buffering.
613 dpte_row_height = 1 << log2_dpte_row_height;
615 data_pitch * dpte_row_height - 1,
641 rq_dlg_param->dpte_row_height = 1 << log2_dpte_row_height;
1192 dpte_row_height_l = rq_dlg_param.rq_l.dpte_row_height;
1193 dpte_row_height_c = rq_dlg_param.rq_c.dpte_row_height;
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