1 /* $NetBSD: drm_edid.c,v 1.15 2021/12/19 12:44:04 riastradh Exp $ */ 2 3 /* 4 * Copyright (c) 2006 Luc Verhaegen (quirks list) 5 * Copyright (c) 2007-2008 Intel Corporation 6 * Jesse Barnes <jesse.barnes (at) intel.com> 7 * Copyright 2010 Red Hat, Inc. 8 * 9 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 10 * FB layer. 11 * Copyright (C) 2006 Dennis Munsie <dmunsie (at) cecropia.com> 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a 14 * copy of this software and associated documentation files (the "Software"), 15 * to deal in the Software without restriction, including without limitation 16 * the rights to use, copy, modify, merge, publish, distribute, sub license, 17 * and/or sell copies of the Software, and to permit persons to whom the 18 * Software is furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice (including the 21 * next paragraph) shall be included in all copies or substantial portions 22 * of the Software. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 25 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 26 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 27 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 28 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 29 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 30 * DEALINGS IN THE SOFTWARE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: drm_edid.c,v 1.15 2021/12/19 12:44:04 riastradh Exp $"); 35 36 #include <linux/hdmi.h> 37 #include <linux/i2c.h> 38 #include <linux/kernel.h> 39 #include <linux/module.h> 40 #include <linux/slab.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include <drm/drm_displayid.h> 44 #include <drm/drm_drv.h> 45 #include <linux/bitmap.h> 46 #include <drm/drm_edid.h> 47 #include <drm/drm_encoder.h> 48 #include <drm/drm_print.h> 49 #include <drm/drm_scdc_helper.h> 50 51 #include "drm_crtc_internal.h" 52 53 #include <linux/nbsd-namespace.h> 54 55 #define version_greater(edid, maj, min) \ 56 (((edid)->version > (maj)) || \ 57 ((edid)->version == (maj) && (edid)->revision > (min))) 58 59 #define EDID_EST_TIMINGS 16 60 #define EDID_STD_TIMINGS 8 61 #define EDID_DETAILED_TIMINGS 4 62 63 /* 64 * EDID blocks out in the wild have a variety of bugs, try to collect 65 * them here (note that userspace may work around broken monitors first, 66 * but fixes should make their way here so that the kernel "just works" 67 * on as many displays as possible). 68 */ 69 70 /* First detailed mode wrong, use largest 60Hz mode */ 71 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 72 /* Reported 135MHz pixel clock is too high, needs adjustment */ 73 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 74 /* Prefer the largest mode at 75 Hz */ 75 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 76 /* Detail timing is in cm not mm */ 77 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 78 /* Detailed timing descriptors have bogus size values, so just take the 79 * maximum size and use that. 80 */ 81 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 82 /* use +hsync +vsync for detailed mode */ 83 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 84 /* Force reduced-blanking timings for detailed modes */ 85 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 86 /* Force 8bpc */ 87 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 88 /* Force 12bpc */ 89 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 90 /* Force 6bpc */ 91 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 92 /* Force 10bpc */ 93 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 94 /* Non desktop display (i.e. HMD) */ 95 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 96 97 struct detailed_mode_closure { 98 struct drm_connector *connector; 99 struct edid *edid; 100 bool preferred; 101 u32 quirks; 102 int modes; 103 }; 104 105 #define LEVEL_DMT 0 106 #define LEVEL_GTF 1 107 #define LEVEL_GTF2 2 108 #define LEVEL_CVT 3 109 110 static const struct edid_quirk { 111 char vendor[4]; 112 int product_id; 113 u32 quirks; 114 } edid_quirk_list[] = { 115 /* Acer AL1706 */ 116 { "ACR", 44358, EDID_QUIRK_PREFER_LARGE_60 }, 117 /* Acer F51 */ 118 { "API", 0x7602, EDID_QUIRK_PREFER_LARGE_60 }, 119 120 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 121 { "AEO", 0, EDID_QUIRK_FORCE_6BPC }, 122 123 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 124 { "BOE", 0x78b, EDID_QUIRK_FORCE_6BPC }, 125 126 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 127 { "CPT", 0x17df, EDID_QUIRK_FORCE_6BPC }, 128 129 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 130 { "SDC", 0x3652, EDID_QUIRK_FORCE_6BPC }, 131 132 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 133 { "BOE", 0x0771, EDID_QUIRK_FORCE_6BPC }, 134 135 /* Belinea 10 15 55 */ 136 { "MAX", 1516, EDID_QUIRK_PREFER_LARGE_60 }, 137 { "MAX", 0x77e, EDID_QUIRK_PREFER_LARGE_60 }, 138 139 /* Envision Peripherals, Inc. EN-7100e */ 140 { "EPI", 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH }, 141 /* Envision EN2028 */ 142 { "EPI", 8232, EDID_QUIRK_PREFER_LARGE_60 }, 143 144 /* Funai Electronics PM36B */ 145 { "FCM", 13600, EDID_QUIRK_PREFER_LARGE_75 | 146 EDID_QUIRK_DETAILED_IN_CM }, 147 148 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 149 { "LGD", 764, EDID_QUIRK_FORCE_10BPC }, 150 151 /* LG Philips LCD LP154W01-A5 */ 152 { "LPL", 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 153 { "LPL", 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE }, 154 155 /* Samsung SyncMaster 205BW. Note: irony */ 156 { "SAM", 541, EDID_QUIRK_DETAILED_SYNC_PP }, 157 /* Samsung SyncMaster 22[5-6]BW */ 158 { "SAM", 596, EDID_QUIRK_PREFER_LARGE_60 }, 159 { "SAM", 638, EDID_QUIRK_PREFER_LARGE_60 }, 160 161 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 162 { "SNY", 0x2541, EDID_QUIRK_FORCE_12BPC }, 163 164 /* ViewSonic VA2026w */ 165 { "VSC", 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING }, 166 167 /* Medion MD 30217 PG */ 168 { "MED", 0x7b8, EDID_QUIRK_PREFER_LARGE_75 }, 169 170 /* Lenovo G50 */ 171 { "SDC", 18514, EDID_QUIRK_FORCE_6BPC }, 172 173 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 174 { "SEC", 0xd033, EDID_QUIRK_FORCE_8BPC }, 175 176 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 177 { "ETR", 13896, EDID_QUIRK_FORCE_8BPC }, 178 179 /* Valve Index Headset */ 180 { "VLV", 0x91a8, EDID_QUIRK_NON_DESKTOP }, 181 { "VLV", 0x91b0, EDID_QUIRK_NON_DESKTOP }, 182 { "VLV", 0x91b1, EDID_QUIRK_NON_DESKTOP }, 183 { "VLV", 0x91b2, EDID_QUIRK_NON_DESKTOP }, 184 { "VLV", 0x91b3, EDID_QUIRK_NON_DESKTOP }, 185 { "VLV", 0x91b4, EDID_QUIRK_NON_DESKTOP }, 186 { "VLV", 0x91b5, EDID_QUIRK_NON_DESKTOP }, 187 { "VLV", 0x91b6, EDID_QUIRK_NON_DESKTOP }, 188 { "VLV", 0x91b7, EDID_QUIRK_NON_DESKTOP }, 189 { "VLV", 0x91b8, EDID_QUIRK_NON_DESKTOP }, 190 { "VLV", 0x91b9, EDID_QUIRK_NON_DESKTOP }, 191 { "VLV", 0x91ba, EDID_QUIRK_NON_DESKTOP }, 192 { "VLV", 0x91bb, EDID_QUIRK_NON_DESKTOP }, 193 { "VLV", 0x91bc, EDID_QUIRK_NON_DESKTOP }, 194 { "VLV", 0x91bd, EDID_QUIRK_NON_DESKTOP }, 195 { "VLV", 0x91be, EDID_QUIRK_NON_DESKTOP }, 196 { "VLV", 0x91bf, EDID_QUIRK_NON_DESKTOP }, 197 198 /* HTC Vive and Vive Pro VR Headsets */ 199 { "HVR", 0xaa01, EDID_QUIRK_NON_DESKTOP }, 200 { "HVR", 0xaa02, EDID_QUIRK_NON_DESKTOP }, 201 202 /* Oculus Rift DK1, DK2, and CV1 VR Headsets */ 203 { "OVR", 0x0001, EDID_QUIRK_NON_DESKTOP }, 204 { "OVR", 0x0003, EDID_QUIRK_NON_DESKTOP }, 205 { "OVR", 0x0004, EDID_QUIRK_NON_DESKTOP }, 206 207 /* Windows Mixed Reality Headsets */ 208 { "ACR", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 209 { "HPN", 0x3515, EDID_QUIRK_NON_DESKTOP }, 210 { "LEN", 0x0408, EDID_QUIRK_NON_DESKTOP }, 211 { "LEN", 0xb800, EDID_QUIRK_NON_DESKTOP }, 212 { "FUJ", 0x1970, EDID_QUIRK_NON_DESKTOP }, 213 { "DEL", 0x7fce, EDID_QUIRK_NON_DESKTOP }, 214 { "SEC", 0x144a, EDID_QUIRK_NON_DESKTOP }, 215 { "AUS", 0xc102, EDID_QUIRK_NON_DESKTOP }, 216 217 /* Sony PlayStation VR Headset */ 218 { "SNY", 0x0704, EDID_QUIRK_NON_DESKTOP }, 219 220 /* Sensics VR Headsets */ 221 { "SEN", 0x1019, EDID_QUIRK_NON_DESKTOP }, 222 223 /* OSVR HDK and HDK2 VR Headsets */ 224 { "SVR", 0x1019, EDID_QUIRK_NON_DESKTOP }, 225 }; 226 227 /* 228 * Autogenerated from the DMT spec. 229 * This table is copied from xfree86/modes/xf86EdidModes.c. 230 */ 231 static const struct drm_display_mode drm_dmt_modes[] = { 232 /* 0x01 - 640x350@85Hz */ 233 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 234 736, 832, 0, 350, 382, 385, 445, 0, 235 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 236 /* 0x02 - 640x400@85Hz */ 237 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 238 736, 832, 0, 400, 401, 404, 445, 0, 239 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 240 /* 0x03 - 720x400@85Hz */ 241 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 242 828, 936, 0, 400, 401, 404, 446, 0, 243 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 244 /* 0x04 - 640x480@60Hz */ 245 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 246 752, 800, 0, 480, 490, 492, 525, 0, 247 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 248 /* 0x05 - 640x480@72Hz */ 249 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 250 704, 832, 0, 480, 489, 492, 520, 0, 251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 252 /* 0x06 - 640x480@75Hz */ 253 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 254 720, 840, 0, 480, 481, 484, 500, 0, 255 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 256 /* 0x07 - 640x480@85Hz */ 257 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 258 752, 832, 0, 480, 481, 484, 509, 0, 259 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 260 /* 0x08 - 800x600@56Hz */ 261 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 262 896, 1024, 0, 600, 601, 603, 625, 0, 263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x09 - 800x600@60Hz */ 265 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 266 968, 1056, 0, 600, 601, 605, 628, 0, 267 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 0x0a - 800x600@72Hz */ 269 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 270 976, 1040, 0, 600, 637, 643, 666, 0, 271 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 272 /* 0x0b - 800x600@75Hz */ 273 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 274 896, 1056, 0, 600, 601, 604, 625, 0, 275 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 276 /* 0x0c - 800x600@85Hz */ 277 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 278 896, 1048, 0, 600, 601, 604, 631, 0, 279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 280 /* 0x0d - 800x600@120Hz RB */ 281 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 282 880, 960, 0, 600, 603, 607, 636, 0, 283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 284 /* 0x0e - 848x480@60Hz */ 285 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 286 976, 1088, 0, 480, 486, 494, 517, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x0f - 1024x768@43Hz, interlace */ 289 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 290 1208, 1264, 0, 768, 768, 776, 817, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 292 DRM_MODE_FLAG_INTERLACE) }, 293 /* 0x10 - 1024x768@60Hz */ 294 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 295 1184, 1344, 0, 768, 771, 777, 806, 0, 296 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 297 /* 0x11 - 1024x768@70Hz */ 298 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 299 1184, 1328, 0, 768, 771, 777, 806, 0, 300 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 301 /* 0x12 - 1024x768@75Hz */ 302 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 303 1136, 1312, 0, 768, 769, 772, 800, 0, 304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 305 /* 0x13 - 1024x768@85Hz */ 306 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 307 1168, 1376, 0, 768, 769, 772, 808, 0, 308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 309 /* 0x14 - 1024x768@120Hz RB */ 310 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 311 1104, 1184, 0, 768, 771, 775, 813, 0, 312 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 313 /* 0x15 - 1152x864@75Hz */ 314 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 315 1344, 1600, 0, 864, 865, 868, 900, 0, 316 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 317 /* 0x55 - 1280x720@60Hz */ 318 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 319 1430, 1650, 0, 720, 725, 730, 750, 0, 320 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 321 /* 0x16 - 1280x768@60Hz RB */ 322 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 323 1360, 1440, 0, 768, 771, 778, 790, 0, 324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 325 /* 0x17 - 1280x768@60Hz */ 326 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 327 1472, 1664, 0, 768, 771, 778, 798, 0, 328 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x18 - 1280x768@75Hz */ 330 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 331 1488, 1696, 0, 768, 771, 778, 805, 0, 332 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x19 - 1280x768@85Hz */ 334 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 335 1496, 1712, 0, 768, 771, 778, 809, 0, 336 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 337 /* 0x1a - 1280x768@120Hz RB */ 338 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 339 1360, 1440, 0, 768, 771, 778, 813, 0, 340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 341 /* 0x1b - 1280x800@60Hz RB */ 342 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 343 1360, 1440, 0, 800, 803, 809, 823, 0, 344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 345 /* 0x1c - 1280x800@60Hz */ 346 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 347 1480, 1680, 0, 800, 803, 809, 831, 0, 348 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 349 /* 0x1d - 1280x800@75Hz */ 350 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 351 1488, 1696, 0, 800, 803, 809, 838, 0, 352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 353 /* 0x1e - 1280x800@85Hz */ 354 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 355 1496, 1712, 0, 800, 803, 809, 843, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x1f - 1280x800@120Hz RB */ 358 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 359 1360, 1440, 0, 800, 803, 809, 847, 0, 360 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 361 /* 0x20 - 1280x960@60Hz */ 362 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 363 1488, 1800, 0, 960, 961, 964, 1000, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 365 /* 0x21 - 1280x960@85Hz */ 366 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 367 1504, 1728, 0, 960, 961, 964, 1011, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 369 /* 0x22 - 1280x960@120Hz RB */ 370 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 371 1360, 1440, 0, 960, 963, 967, 1017, 0, 372 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 373 /* 0x23 - 1280x1024@60Hz */ 374 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 375 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 376 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x24 - 1280x1024@75Hz */ 378 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 379 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 380 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x25 - 1280x1024@85Hz */ 382 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 383 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 385 /* 0x26 - 1280x1024@120Hz RB */ 386 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 387 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 389 /* 0x27 - 1360x768@60Hz */ 390 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 391 1536, 1792, 0, 768, 771, 777, 795, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x28 - 1360x768@120Hz RB */ 394 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 395 1440, 1520, 0, 768, 771, 776, 813, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 397 /* 0x51 - 1366x768@60Hz */ 398 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 399 1579, 1792, 0, 768, 771, 774, 798, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 401 /* 0x56 - 1366x768@60Hz */ 402 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 403 1436, 1500, 0, 768, 769, 772, 800, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x29 - 1400x1050@60Hz RB */ 406 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 407 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 409 /* 0x2a - 1400x1050@60Hz */ 410 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 411 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 412 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 413 /* 0x2b - 1400x1050@75Hz */ 414 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 415 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 416 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 0x2c - 1400x1050@85Hz */ 418 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 419 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 420 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 421 /* 0x2d - 1400x1050@120Hz RB */ 422 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 423 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 425 /* 0x2e - 1440x900@60Hz RB */ 426 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 427 1520, 1600, 0, 900, 903, 909, 926, 0, 428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 429 /* 0x2f - 1440x900@60Hz */ 430 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 431 1672, 1904, 0, 900, 903, 909, 934, 0, 432 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 433 /* 0x30 - 1440x900@75Hz */ 434 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 435 1688, 1936, 0, 900, 903, 909, 942, 0, 436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 437 /* 0x31 - 1440x900@85Hz */ 438 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 439 1696, 1952, 0, 900, 903, 909, 948, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 441 /* 0x32 - 1440x900@120Hz RB */ 442 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 443 1520, 1600, 0, 900, 903, 909, 953, 0, 444 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 445 /* 0x53 - 1600x900@60Hz */ 446 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 447 1704, 1800, 0, 900, 901, 904, 1000, 0, 448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 449 /* 0x33 - 1600x1200@60Hz */ 450 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 451 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 453 /* 0x34 - 1600x1200@65Hz */ 454 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 455 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x35 - 1600x1200@70Hz */ 458 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 459 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 460 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x36 - 1600x1200@75Hz */ 462 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 463 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 464 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x37 - 1600x1200@85Hz */ 466 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 467 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 469 /* 0x38 - 1600x1200@120Hz RB */ 470 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 471 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 473 /* 0x39 - 1680x1050@60Hz RB */ 474 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 475 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 477 /* 0x3a - 1680x1050@60Hz */ 478 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 479 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 480 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 481 /* 0x3b - 1680x1050@75Hz */ 482 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 483 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 484 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 485 /* 0x3c - 1680x1050@85Hz */ 486 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 487 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 488 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x3d - 1680x1050@120Hz RB */ 490 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 491 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 493 /* 0x3e - 1792x1344@60Hz */ 494 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 495 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 496 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 497 /* 0x3f - 1792x1344@75Hz */ 498 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 499 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 500 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 501 /* 0x40 - 1792x1344@120Hz RB */ 502 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 503 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 505 /* 0x41 - 1856x1392@60Hz */ 506 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 507 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 509 /* 0x42 - 1856x1392@75Hz */ 510 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 511 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 513 /* 0x43 - 1856x1392@120Hz RB */ 514 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 515 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x52 - 1920x1080@60Hz */ 518 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 519 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 521 /* 0x44 - 1920x1200@60Hz RB */ 522 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 523 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 524 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 525 /* 0x45 - 1920x1200@60Hz */ 526 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 527 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 528 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 529 /* 0x46 - 1920x1200@75Hz */ 530 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 531 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 533 /* 0x47 - 1920x1200@85Hz */ 534 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 535 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 537 /* 0x48 - 1920x1200@120Hz RB */ 538 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 539 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 541 /* 0x49 - 1920x1440@60Hz */ 542 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 543 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 545 /* 0x4a - 1920x1440@75Hz */ 546 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 547 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 548 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 549 /* 0x4b - 1920x1440@120Hz RB */ 550 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 551 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 552 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 553 /* 0x54 - 2048x1152@60Hz */ 554 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 555 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 556 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 557 /* 0x4c - 2560x1600@60Hz RB */ 558 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 559 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 560 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 561 /* 0x4d - 2560x1600@60Hz */ 562 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 563 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 564 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 565 /* 0x4e - 2560x1600@75Hz */ 566 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 567 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 569 /* 0x4f - 2560x1600@85Hz */ 570 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 571 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 573 /* 0x50 - 2560x1600@120Hz RB */ 574 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 575 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 577 /* 0x57 - 4096x2160@60Hz RB */ 578 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 579 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 581 /* 0x58 - 4096x2160 (at) 59.94Hz RB */ 582 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 583 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 585 }; 586 587 /* 588 * These more or less come from the DMT spec. The 720x400 modes are 589 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 590 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 591 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 592 * mode. 593 * 594 * The DMT modes have been fact-checked; the rest are mild guesses. 595 */ 596 static const struct drm_display_mode edid_est_modes[] = { 597 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 598 968, 1056, 0, 600, 601, 605, 628, 0, 599 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 600 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 601 896, 1024, 0, 600, 601, 603, 625, 0, 602 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 603 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 604 720, 840, 0, 480, 481, 484, 500, 0, 605 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 606 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 607 704, 832, 0, 480, 489, 492, 520, 0, 608 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 609 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 610 768, 864, 0, 480, 483, 486, 525, 0, 611 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 612 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 613 752, 800, 0, 480, 490, 492, 525, 0, 614 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 615 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 616 846, 900, 0, 400, 421, 423, 449, 0, 617 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 618 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 619 846, 900, 0, 400, 412, 414, 449, 0, 620 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 621 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 622 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 623 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 624 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 625 1136, 1312, 0, 768, 769, 772, 800, 0, 626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 627 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 628 1184, 1328, 0, 768, 771, 777, 806, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 630 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 631 1184, 1344, 0, 768, 771, 777, 806, 0, 632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 633 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 634 1208, 1264, 0, 768, 768, 776, 817, 0, 635 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 636 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 637 928, 1152, 0, 624, 625, 628, 667, 0, 638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 639 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 640 896, 1056, 0, 600, 601, 604, 625, 0, 641 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 642 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 643 976, 1040, 0, 600, 637, 643, 666, 0, 644 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 645 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 646 1344, 1600, 0, 864, 865, 868, 900, 0, 647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 648 }; 649 650 struct minimode { 651 short w; 652 short h; 653 short r; 654 short rb; 655 }; 656 657 static const struct minimode est3_modes[] = { 658 /* byte 6 */ 659 { 640, 350, 85, 0 }, 660 { 640, 400, 85, 0 }, 661 { 720, 400, 85, 0 }, 662 { 640, 480, 85, 0 }, 663 { 848, 480, 60, 0 }, 664 { 800, 600, 85, 0 }, 665 { 1024, 768, 85, 0 }, 666 { 1152, 864, 75, 0 }, 667 /* byte 7 */ 668 { 1280, 768, 60, 1 }, 669 { 1280, 768, 60, 0 }, 670 { 1280, 768, 75, 0 }, 671 { 1280, 768, 85, 0 }, 672 { 1280, 960, 60, 0 }, 673 { 1280, 960, 85, 0 }, 674 { 1280, 1024, 60, 0 }, 675 { 1280, 1024, 85, 0 }, 676 /* byte 8 */ 677 { 1360, 768, 60, 0 }, 678 { 1440, 900, 60, 1 }, 679 { 1440, 900, 60, 0 }, 680 { 1440, 900, 75, 0 }, 681 { 1440, 900, 85, 0 }, 682 { 1400, 1050, 60, 1 }, 683 { 1400, 1050, 60, 0 }, 684 { 1400, 1050, 75, 0 }, 685 /* byte 9 */ 686 { 1400, 1050, 85, 0 }, 687 { 1680, 1050, 60, 1 }, 688 { 1680, 1050, 60, 0 }, 689 { 1680, 1050, 75, 0 }, 690 { 1680, 1050, 85, 0 }, 691 { 1600, 1200, 60, 0 }, 692 { 1600, 1200, 65, 0 }, 693 { 1600, 1200, 70, 0 }, 694 /* byte 10 */ 695 { 1600, 1200, 75, 0 }, 696 { 1600, 1200, 85, 0 }, 697 { 1792, 1344, 60, 0 }, 698 { 1792, 1344, 75, 0 }, 699 { 1856, 1392, 60, 0 }, 700 { 1856, 1392, 75, 0 }, 701 { 1920, 1200, 60, 1 }, 702 { 1920, 1200, 60, 0 }, 703 /* byte 11 */ 704 { 1920, 1200, 75, 0 }, 705 { 1920, 1200, 85, 0 }, 706 { 1920, 1440, 60, 0 }, 707 { 1920, 1440, 75, 0 }, 708 }; 709 710 static const struct minimode extra_modes[] = { 711 { 1024, 576, 60, 0 }, 712 { 1366, 768, 60, 0 }, 713 { 1600, 900, 60, 0 }, 714 { 1680, 945, 60, 0 }, 715 { 1920, 1080, 60, 0 }, 716 { 2048, 1152, 60, 0 }, 717 { 2048, 1536, 60, 0 }, 718 }; 719 720 /* 721 * From CEA/CTA-861 spec. 722 * 723 * Do not access directly, instead always use cea_mode_for_vic(). 724 */ 725 static const struct drm_display_mode edid_cea_modes_1[] = { 726 /* 1 - 640x480@60Hz 4:3 */ 727 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 728 752, 800, 0, 480, 490, 492, 525, 0, 729 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 730 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 731 /* 2 - 720x480@60Hz 4:3 */ 732 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 733 798, 858, 0, 480, 489, 495, 525, 0, 734 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 735 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 736 /* 3 - 720x480@60Hz 16:9 */ 737 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 738 798, 858, 0, 480, 489, 495, 525, 0, 739 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 740 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 741 /* 4 - 1280x720@60Hz 16:9 */ 742 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 743 1430, 1650, 0, 720, 725, 730, 750, 0, 744 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 745 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 746 /* 5 - 1920x1080i@60Hz 16:9 */ 747 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 748 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 749 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 750 DRM_MODE_FLAG_INTERLACE), 751 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 752 /* 6 - 720(1440)x480i@60Hz 4:3 */ 753 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 754 801, 858, 0, 480, 488, 494, 525, 0, 755 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 756 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 757 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 758 /* 7 - 720(1440)x480i@60Hz 16:9 */ 759 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 760 801, 858, 0, 480, 488, 494, 525, 0, 761 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 762 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 763 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 764 /* 8 - 720(1440)x240@60Hz 4:3 */ 765 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 766 801, 858, 0, 240, 244, 247, 262, 0, 767 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 768 DRM_MODE_FLAG_DBLCLK), 769 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 770 /* 9 - 720(1440)x240@60Hz 16:9 */ 771 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 772 801, 858, 0, 240, 244, 247, 262, 0, 773 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 774 DRM_MODE_FLAG_DBLCLK), 775 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 776 /* 10 - 2880x480i@60Hz 4:3 */ 777 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 778 3204, 3432, 0, 480, 488, 494, 525, 0, 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 780 DRM_MODE_FLAG_INTERLACE), 781 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 782 /* 11 - 2880x480i@60Hz 16:9 */ 783 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 784 3204, 3432, 0, 480, 488, 494, 525, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 786 DRM_MODE_FLAG_INTERLACE), 787 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 788 /* 12 - 2880x240@60Hz 4:3 */ 789 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 790 3204, 3432, 0, 240, 244, 247, 262, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 792 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 793 /* 13 - 2880x240@60Hz 16:9 */ 794 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 795 3204, 3432, 0, 240, 244, 247, 262, 0, 796 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 797 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 798 /* 14 - 1440x480@60Hz 4:3 */ 799 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 800 1596, 1716, 0, 480, 489, 495, 525, 0, 801 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 802 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 803 /* 15 - 1440x480@60Hz 16:9 */ 804 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 805 1596, 1716, 0, 480, 489, 495, 525, 0, 806 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 807 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 808 /* 16 - 1920x1080@60Hz 16:9 */ 809 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 810 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 811 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 812 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 813 /* 17 - 720x576@50Hz 4:3 */ 814 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 815 796, 864, 0, 576, 581, 586, 625, 0, 816 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 817 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 818 /* 18 - 720x576@50Hz 16:9 */ 819 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 820 796, 864, 0, 576, 581, 586, 625, 0, 821 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 822 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 823 /* 19 - 1280x720@50Hz 16:9 */ 824 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 825 1760, 1980, 0, 720, 725, 730, 750, 0, 826 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 827 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 828 /* 20 - 1920x1080i@50Hz 16:9 */ 829 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 830 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 831 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 832 DRM_MODE_FLAG_INTERLACE), 833 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 834 /* 21 - 720(1440)x576i@50Hz 4:3 */ 835 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 836 795, 864, 0, 576, 580, 586, 625, 0, 837 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 838 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 839 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 840 /* 22 - 720(1440)x576i@50Hz 16:9 */ 841 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 842 795, 864, 0, 576, 580, 586, 625, 0, 843 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 844 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 845 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 846 /* 23 - 720(1440)x288@50Hz 4:3 */ 847 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 848 795, 864, 0, 288, 290, 293, 312, 0, 849 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 850 DRM_MODE_FLAG_DBLCLK), 851 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 852 /* 24 - 720(1440)x288@50Hz 16:9 */ 853 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 854 795, 864, 0, 288, 290, 293, 312, 0, 855 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 856 DRM_MODE_FLAG_DBLCLK), 857 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 25 - 2880x576i@50Hz 4:3 */ 859 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 860 3180, 3456, 0, 576, 580, 586, 625, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 862 DRM_MODE_FLAG_INTERLACE), 863 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 864 /* 26 - 2880x576i@50Hz 16:9 */ 865 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 866 3180, 3456, 0, 576, 580, 586, 625, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 868 DRM_MODE_FLAG_INTERLACE), 869 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 870 /* 27 - 2880x288@50Hz 4:3 */ 871 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 872 3180, 3456, 0, 288, 290, 293, 312, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 874 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 875 /* 28 - 2880x288@50Hz 16:9 */ 876 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 877 3180, 3456, 0, 288, 290, 293, 312, 0, 878 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 879 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 880 /* 29 - 1440x576@50Hz 4:3 */ 881 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 882 1592, 1728, 0, 576, 581, 586, 625, 0, 883 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 884 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 885 /* 30 - 1440x576@50Hz 16:9 */ 886 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 887 1592, 1728, 0, 576, 581, 586, 625, 0, 888 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 889 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 890 /* 31 - 1920x1080@50Hz 16:9 */ 891 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 892 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 893 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 894 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 895 /* 32 - 1920x1080@24Hz 16:9 */ 896 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 897 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 898 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 899 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 900 /* 33 - 1920x1080@25Hz 16:9 */ 901 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 902 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 903 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 904 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 905 /* 34 - 1920x1080@30Hz 16:9 */ 906 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 907 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 908 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 909 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 910 /* 35 - 2880x480@60Hz 4:3 */ 911 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 912 3192, 3432, 0, 480, 489, 495, 525, 0, 913 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 914 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 915 /* 36 - 2880x480@60Hz 16:9 */ 916 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 917 3192, 3432, 0, 480, 489, 495, 525, 0, 918 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 919 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 920 /* 37 - 2880x576@50Hz 4:3 */ 921 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 922 3184, 3456, 0, 576, 581, 586, 625, 0, 923 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 924 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 925 /* 38 - 2880x576@50Hz 16:9 */ 926 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 927 3184, 3456, 0, 576, 581, 586, 625, 0, 928 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 929 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 930 /* 39 - 1920x1080i@50Hz 16:9 */ 931 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 932 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 933 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 934 DRM_MODE_FLAG_INTERLACE), 935 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 936 /* 40 - 1920x1080i@100Hz 16:9 */ 937 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 938 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 939 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 940 DRM_MODE_FLAG_INTERLACE), 941 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 942 /* 41 - 1280x720@100Hz 16:9 */ 943 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 944 1760, 1980, 0, 720, 725, 730, 750, 0, 945 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 946 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 947 /* 42 - 720x576@100Hz 4:3 */ 948 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 949 796, 864, 0, 576, 581, 586, 625, 0, 950 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 951 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 952 /* 43 - 720x576@100Hz 16:9 */ 953 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 954 796, 864, 0, 576, 581, 586, 625, 0, 955 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 956 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 957 /* 44 - 720(1440)x576i@100Hz 4:3 */ 958 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 959 795, 864, 0, 576, 580, 586, 625, 0, 960 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 961 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 962 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 963 /* 45 - 720(1440)x576i@100Hz 16:9 */ 964 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 965 795, 864, 0, 576, 580, 586, 625, 0, 966 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 967 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 968 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 969 /* 46 - 1920x1080i@120Hz 16:9 */ 970 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 971 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 972 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 973 DRM_MODE_FLAG_INTERLACE), 974 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 975 /* 47 - 1280x720@120Hz 16:9 */ 976 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 977 1430, 1650, 0, 720, 725, 730, 750, 0, 978 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 979 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 980 /* 48 - 720x480@120Hz 4:3 */ 981 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 982 798, 858, 0, 480, 489, 495, 525, 0, 983 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 984 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 985 /* 49 - 720x480@120Hz 16:9 */ 986 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 987 798, 858, 0, 480, 489, 495, 525, 0, 988 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 989 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 990 /* 50 - 720(1440)x480i@120Hz 4:3 */ 991 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 992 801, 858, 0, 480, 488, 494, 525, 0, 993 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 994 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 995 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 996 /* 51 - 720(1440)x480i@120Hz 16:9 */ 997 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 998 801, 858, 0, 480, 488, 494, 525, 0, 999 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1000 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1001 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1002 /* 52 - 720x576@200Hz 4:3 */ 1003 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1004 796, 864, 0, 576, 581, 586, 625, 0, 1005 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1006 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1007 /* 53 - 720x576@200Hz 16:9 */ 1008 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1009 796, 864, 0, 576, 581, 586, 625, 0, 1010 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1011 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1012 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1013 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1014 795, 864, 0, 576, 580, 586, 625, 0, 1015 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1016 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1017 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1018 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1019 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1020 795, 864, 0, 576, 580, 586, 625, 0, 1021 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1022 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1023 .vrefresh = 200, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1024 /* 56 - 720x480@240Hz 4:3 */ 1025 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1026 798, 858, 0, 480, 489, 495, 525, 0, 1027 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1028 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1029 /* 57 - 720x480@240Hz 16:9 */ 1030 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1031 798, 858, 0, 480, 489, 495, 525, 0, 1032 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1033 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1034 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1035 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1036 801, 858, 0, 480, 488, 494, 525, 0, 1037 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1038 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1039 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1040 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1041 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1042 801, 858, 0, 480, 488, 494, 525, 0, 1043 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1044 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1045 .vrefresh = 240, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1046 /* 60 - 1280x720@24Hz 16:9 */ 1047 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1048 3080, 3300, 0, 720, 725, 730, 750, 0, 1049 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1050 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1051 /* 61 - 1280x720@25Hz 16:9 */ 1052 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1053 3740, 3960, 0, 720, 725, 730, 750, 0, 1054 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1055 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1056 /* 62 - 1280x720@30Hz 16:9 */ 1057 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1058 3080, 3300, 0, 720, 725, 730, 750, 0, 1059 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1060 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1061 /* 63 - 1920x1080@120Hz 16:9 */ 1062 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1063 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1064 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1065 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1066 /* 64 - 1920x1080@100Hz 16:9 */ 1067 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1068 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1069 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1070 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1071 /* 65 - 1280x720@24Hz 64:27 */ 1072 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1073 3080, 3300, 0, 720, 725, 730, 750, 0, 1074 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1075 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1076 /* 66 - 1280x720@25Hz 64:27 */ 1077 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1078 3740, 3960, 0, 720, 725, 730, 750, 0, 1079 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1080 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1081 /* 67 - 1280x720@30Hz 64:27 */ 1082 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1083 3080, 3300, 0, 720, 725, 730, 750, 0, 1084 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1085 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1086 /* 68 - 1280x720@50Hz 64:27 */ 1087 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1088 1760, 1980, 0, 720, 725, 730, 750, 0, 1089 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1090 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1091 /* 69 - 1280x720@60Hz 64:27 */ 1092 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1093 1430, 1650, 0, 720, 725, 730, 750, 0, 1094 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1095 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1096 /* 70 - 1280x720@100Hz 64:27 */ 1097 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1098 1760, 1980, 0, 720, 725, 730, 750, 0, 1099 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1100 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1101 /* 71 - 1280x720@120Hz 64:27 */ 1102 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1103 1430, 1650, 0, 720, 725, 730, 750, 0, 1104 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1105 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1106 /* 72 - 1920x1080@24Hz 64:27 */ 1107 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1108 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1109 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1110 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1111 /* 73 - 1920x1080@25Hz 64:27 */ 1112 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1113 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1114 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1115 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1116 /* 74 - 1920x1080@30Hz 64:27 */ 1117 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1118 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1119 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1120 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1121 /* 75 - 1920x1080@50Hz 64:27 */ 1122 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1123 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1124 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1125 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1126 /* 76 - 1920x1080@60Hz 64:27 */ 1127 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1128 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1129 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1130 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1131 /* 77 - 1920x1080@100Hz 64:27 */ 1132 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1133 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1134 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1135 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1136 /* 78 - 1920x1080@120Hz 64:27 */ 1137 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1138 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1139 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1140 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1141 /* 79 - 1680x720@24Hz 64:27 */ 1142 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1143 3080, 3300, 0, 720, 725, 730, 750, 0, 1144 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1145 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1146 /* 80 - 1680x720@25Hz 64:27 */ 1147 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1148 2948, 3168, 0, 720, 725, 730, 750, 0, 1149 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1150 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1151 /* 81 - 1680x720@30Hz 64:27 */ 1152 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1153 2420, 2640, 0, 720, 725, 730, 750, 0, 1154 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1155 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1156 /* 82 - 1680x720@50Hz 64:27 */ 1157 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1158 1980, 2200, 0, 720, 725, 730, 750, 0, 1159 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1160 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1161 /* 83 - 1680x720@60Hz 64:27 */ 1162 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1163 1980, 2200, 0, 720, 725, 730, 750, 0, 1164 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1165 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1166 /* 84 - 1680x720@100Hz 64:27 */ 1167 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1168 1780, 2000, 0, 720, 725, 730, 825, 0, 1169 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1170 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1171 /* 85 - 1680x720@120Hz 64:27 */ 1172 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1173 1780, 2000, 0, 720, 725, 730, 825, 0, 1174 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1175 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1176 /* 86 - 2560x1080@24Hz 64:27 */ 1177 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1178 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1179 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1180 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1181 /* 87 - 2560x1080@25Hz 64:27 */ 1182 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1183 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1184 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1185 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1186 /* 88 - 2560x1080@30Hz 64:27 */ 1187 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1188 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1189 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1190 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1191 /* 89 - 2560x1080@50Hz 64:27 */ 1192 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1193 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1194 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1195 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1196 /* 90 - 2560x1080@60Hz 64:27 */ 1197 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1198 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1199 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1200 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1201 /* 91 - 2560x1080@100Hz 64:27 */ 1202 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1203 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1204 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1205 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1206 /* 92 - 2560x1080@120Hz 64:27 */ 1207 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1208 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1209 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1210 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1211 /* 93 - 3840x2160@24Hz 16:9 */ 1212 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1213 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1214 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1215 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1216 /* 94 - 3840x2160@25Hz 16:9 */ 1217 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1218 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1219 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1220 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1221 /* 95 - 3840x2160@30Hz 16:9 */ 1222 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1223 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1224 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1225 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1226 /* 96 - 3840x2160@50Hz 16:9 */ 1227 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1228 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1229 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1230 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1231 /* 97 - 3840x2160@60Hz 16:9 */ 1232 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1233 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1234 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1235 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1236 /* 98 - 4096x2160@24Hz 256:135 */ 1237 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1238 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1239 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1240 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1241 /* 99 - 4096x2160@25Hz 256:135 */ 1242 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1243 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1244 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1245 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1246 /* 100 - 4096x2160@30Hz 256:135 */ 1247 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1248 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1249 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1250 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1251 /* 101 - 4096x2160@50Hz 256:135 */ 1252 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1253 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1254 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1255 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1256 /* 102 - 4096x2160@60Hz 256:135 */ 1257 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1258 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1260 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1261 /* 103 - 3840x2160@24Hz 64:27 */ 1262 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1263 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1264 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1265 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1266 /* 104 - 3840x2160@25Hz 64:27 */ 1267 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1268 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1269 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1270 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1271 /* 105 - 3840x2160@30Hz 64:27 */ 1272 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1273 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1274 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1275 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1276 /* 106 - 3840x2160@50Hz 64:27 */ 1277 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1278 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1279 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1280 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1281 /* 107 - 3840x2160@60Hz 64:27 */ 1282 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1283 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1284 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1285 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1286 /* 108 - 1280x720@48Hz 16:9 */ 1287 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1288 2280, 2500, 0, 720, 725, 730, 750, 0, 1289 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1290 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1291 /* 109 - 1280x720@48Hz 64:27 */ 1292 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1293 2280, 2500, 0, 720, 725, 730, 750, 0, 1294 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1295 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1296 /* 110 - 1680x720@48Hz 64:27 */ 1297 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1298 2530, 2750, 0, 720, 725, 730, 750, 0, 1299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1300 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1301 /* 111 - 1920x1080@48Hz 16:9 */ 1302 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1303 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1304 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1305 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1306 /* 112 - 1920x1080@48Hz 64:27 */ 1307 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1308 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1309 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1310 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1311 /* 113 - 2560x1080@48Hz 64:27 */ 1312 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1313 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1314 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1315 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1316 /* 114 - 3840x2160@48Hz 16:9 */ 1317 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1318 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1319 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1320 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1321 /* 115 - 4096x2160@48Hz 256:135 */ 1322 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1323 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1324 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1325 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1326 /* 116 - 3840x2160@48Hz 64:27 */ 1327 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1328 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1329 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1330 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1331 /* 117 - 3840x2160@100Hz 16:9 */ 1332 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1333 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1334 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1335 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1336 /* 118 - 3840x2160@120Hz 16:9 */ 1337 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1338 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1339 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1340 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1341 /* 119 - 3840x2160@100Hz 64:27 */ 1342 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1343 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1345 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1346 /* 120 - 3840x2160@120Hz 64:27 */ 1347 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1348 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1349 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1350 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1351 /* 121 - 5120x2160@24Hz 64:27 */ 1352 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1353 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1354 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1355 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1356 /* 122 - 5120x2160@25Hz 64:27 */ 1357 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1358 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1359 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1360 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1361 /* 123 - 5120x2160@30Hz 64:27 */ 1362 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1363 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1365 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1366 /* 124 - 5120x2160@48Hz 64:27 */ 1367 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1368 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1369 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1370 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1371 /* 125 - 5120x2160@50Hz 64:27 */ 1372 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1373 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1374 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1375 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1376 /* 126 - 5120x2160@60Hz 64:27 */ 1377 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1378 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1379 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1380 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1381 /* 127 - 5120x2160@100Hz 64:27 */ 1382 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1383 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1385 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1386 }; 1387 1388 /* 1389 * From CEA/CTA-861 spec. 1390 * 1391 * Do not access directly, instead always use cea_mode_for_vic(). 1392 */ 1393 static const struct drm_display_mode edid_cea_modes_193[] = { 1394 /* 193 - 5120x2160@120Hz 64:27 */ 1395 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1396 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1397 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1398 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1399 /* 194 - 7680x4320@24Hz 16:9 */ 1400 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1401 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1402 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1403 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1404 /* 195 - 7680x4320@25Hz 16:9 */ 1405 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1406 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1407 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1408 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1409 /* 196 - 7680x4320@30Hz 16:9 */ 1410 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1411 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1413 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1414 /* 197 - 7680x4320@48Hz 16:9 */ 1415 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1416 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1417 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1418 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1419 /* 198 - 7680x4320@50Hz 16:9 */ 1420 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1421 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1422 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1423 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1424 /* 199 - 7680x4320@60Hz 16:9 */ 1425 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1426 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1427 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1428 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1429 /* 200 - 7680x4320@100Hz 16:9 */ 1430 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1431 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1433 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1434 /* 201 - 7680x4320@120Hz 16:9 */ 1435 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1436 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1437 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1438 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1439 /* 202 - 7680x4320@24Hz 64:27 */ 1440 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1441 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1442 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1443 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1444 /* 203 - 7680x4320@25Hz 64:27 */ 1445 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1446 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1447 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1448 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1449 /* 204 - 7680x4320@30Hz 64:27 */ 1450 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1451 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1453 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1454 /* 205 - 7680x4320@48Hz 64:27 */ 1455 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1456 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1457 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1458 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1459 /* 206 - 7680x4320@50Hz 64:27 */ 1460 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1461 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1462 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1463 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1464 /* 207 - 7680x4320@60Hz 64:27 */ 1465 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1466 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1467 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1468 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1469 /* 208 - 7680x4320@100Hz 64:27 */ 1470 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1471 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1473 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1474 /* 209 - 7680x4320@120Hz 64:27 */ 1475 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1476 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1477 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1478 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1479 /* 210 - 10240x4320@24Hz 64:27 */ 1480 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1481 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1482 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1483 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1484 /* 211 - 10240x4320@25Hz 64:27 */ 1485 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1486 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1488 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1489 /* 212 - 10240x4320@30Hz 64:27 */ 1490 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1491 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1493 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1494 /* 213 - 10240x4320@48Hz 64:27 */ 1495 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1496 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1497 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1498 .vrefresh = 48, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1499 /* 214 - 10240x4320@50Hz 64:27 */ 1500 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1501 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1503 .vrefresh = 50, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1504 /* 215 - 10240x4320@60Hz 64:27 */ 1505 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1506 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1508 .vrefresh = 60, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1509 /* 216 - 10240x4320@100Hz 64:27 */ 1510 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1511 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1512 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1513 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1514 /* 217 - 10240x4320@120Hz 64:27 */ 1515 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1516 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1518 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1519 /* 218 - 4096x2160@100Hz 256:135 */ 1520 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1521 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1523 .vrefresh = 100, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1524 /* 219 - 4096x2160@120Hz 256:135 */ 1525 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1526 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1527 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1528 .vrefresh = 120, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1529 }; 1530 1531 /* 1532 * HDMI 1.4 4k modes. Index using the VIC. 1533 */ 1534 static const struct drm_display_mode edid_4k_modes[] = { 1535 /* 0 - dummy, VICs start at 1 */ 1536 { }, 1537 /* 1 - 3840x2160@30Hz */ 1538 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1539 3840, 4016, 4104, 4400, 0, 1540 2160, 2168, 2178, 2250, 0, 1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1542 .vrefresh = 30, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1543 /* 2 - 3840x2160@25Hz */ 1544 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1545 3840, 4896, 4984, 5280, 0, 1546 2160, 2168, 2178, 2250, 0, 1547 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1548 .vrefresh = 25, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1549 /* 3 - 3840x2160@24Hz */ 1550 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1551 3840, 5116, 5204, 5500, 0, 1552 2160, 2168, 2178, 2250, 0, 1553 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1554 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1555 /* 4 - 4096x2160@24Hz (SMPTE) */ 1556 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1557 4096, 5116, 5204, 5500, 0, 1558 2160, 2168, 2178, 2250, 0, 1559 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1560 .vrefresh = 24, .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1561 }; 1562 1563 /*** DDC fetch and block validation ***/ 1564 1565 static const u8 edid_header[] = { 1566 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1567 }; 1568 1569 /** 1570 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1571 * @raw_edid: pointer to raw base EDID block 1572 * 1573 * Sanity check the header of the base EDID block. 1574 * 1575 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1576 */ 1577 int drm_edid_header_is_valid(const u8 *raw_edid) 1578 { 1579 int i, score = 0; 1580 1581 for (i = 0; i < sizeof(edid_header); i++) 1582 if (raw_edid[i] == edid_header[i]) 1583 score++; 1584 1585 return score; 1586 } 1587 EXPORT_SYMBOL(drm_edid_header_is_valid); 1588 1589 static int edid_fixup __read_mostly = 6; 1590 module_param_named(edid_fixup, edid_fixup, int, 0400); 1591 MODULE_PARM_DESC(edid_fixup, 1592 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1593 1594 static void drm_get_displayid(struct drm_connector *connector, 1595 struct edid *edid); 1596 static int validate_displayid(const u8 *displayid, int length, int idx); 1597 1598 static int drm_edid_block_checksum(const u8 *raw_edid) 1599 { 1600 int i; 1601 u8 csum = 0; 1602 for (i = 0; i < EDID_LENGTH; i++) 1603 csum += raw_edid[i]; 1604 1605 return csum; 1606 } 1607 1608 static bool drm_edid_is_zero(const u8 *in_edid, int length) 1609 { 1610 if (memchr_inv(in_edid, 0, length)) 1611 return false; 1612 1613 return true; 1614 } 1615 1616 /** 1617 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1618 * @raw_edid: pointer to raw EDID block 1619 * @block: type of block to validate (0 for base, extension otherwise) 1620 * @print_bad_edid: if true, dump bad EDID blocks to the console 1621 * @edid_corrupt: if true, the header or checksum is invalid 1622 * 1623 * Validate a base or extension EDID block and optionally dump bad blocks to 1624 * the console. 1625 * 1626 * Return: True if the block is valid, false otherwise. 1627 */ 1628 bool drm_edid_block_valid(u8 *raw_edid, int block, bool print_bad_edid, 1629 bool *edid_corrupt) 1630 { 1631 u8 csum; 1632 struct edid *edid = (struct edid *)raw_edid; 1633 1634 if (WARN_ON(!raw_edid)) 1635 return false; 1636 1637 if (edid_fixup > 8 || edid_fixup < 0) 1638 edid_fixup = 6; 1639 1640 if (block == 0) { 1641 int score = drm_edid_header_is_valid(raw_edid); 1642 if (score == 8) { 1643 if (edid_corrupt) 1644 *edid_corrupt = false; 1645 } else if (score >= edid_fixup) { 1646 /* Displayport Link CTS Core 1.2 rev1.1 test 4.2.2.6 1647 * The corrupt flag needs to be set here otherwise, the 1648 * fix-up code here will correct the problem, the 1649 * checksum is correct and the test fails 1650 */ 1651 if (edid_corrupt) 1652 *edid_corrupt = true; 1653 DRM_DEBUG("Fixing EDID header, your hardware may be failing\n"); 1654 memcpy(raw_edid, edid_header, sizeof(edid_header)); 1655 } else { 1656 if (edid_corrupt) 1657 *edid_corrupt = true; 1658 goto bad; 1659 } 1660 } 1661 1662 csum = drm_edid_block_checksum(raw_edid); 1663 if (csum) { 1664 if (edid_corrupt) 1665 *edid_corrupt = true; 1666 1667 /* allow CEA to slide through, switches mangle this */ 1668 if (raw_edid[0] == CEA_EXT) { 1669 DRM_DEBUG("EDID checksum is invalid, remainder is %d\n", csum); 1670 DRM_DEBUG("Assuming a KVM switch modified the CEA block but left the original checksum\n"); 1671 } else { 1672 if (print_bad_edid) 1673 DRM_NOTE("EDID checksum is invalid, remainder is %d\n", csum); 1674 1675 goto bad; 1676 } 1677 } 1678 1679 /* per-block-type checks */ 1680 switch (raw_edid[0]) { 1681 case 0: /* base */ 1682 if (edid->version != 1) { 1683 DRM_NOTE("EDID has major version %d, instead of 1\n", edid->version); 1684 goto bad; 1685 } 1686 1687 if (edid->revision > 4) 1688 DRM_DEBUG("EDID minor > 4, assuming backward compatibility\n"); 1689 break; 1690 1691 default: 1692 break; 1693 } 1694 1695 return true; 1696 1697 bad: 1698 if (print_bad_edid) { 1699 if (drm_edid_is_zero(raw_edid, EDID_LENGTH)) { 1700 pr_notice("EDID block is all zeroes\n"); 1701 } else { 1702 pr_notice("Raw EDID:\n"); 1703 print_hex_dump(KERN_NOTICE, 1704 " \t", DUMP_PREFIX_NONE, 16, 1, 1705 raw_edid, EDID_LENGTH, false); 1706 } 1707 } 1708 return false; 1709 } 1710 EXPORT_SYMBOL(drm_edid_block_valid); 1711 1712 /** 1713 * drm_edid_is_valid - sanity check EDID data 1714 * @edid: EDID data 1715 * 1716 * Sanity-check an entire EDID record (including extensions) 1717 * 1718 * Return: True if the EDID data is valid, false otherwise. 1719 */ 1720 bool drm_edid_is_valid(struct edid *edid) 1721 { 1722 int i; 1723 u8 *raw = (u8 *)edid; 1724 1725 if (!edid) 1726 return false; 1727 1728 for (i = 0; i <= edid->extensions; i++) 1729 if (!drm_edid_block_valid(raw + i * EDID_LENGTH, i, true, NULL)) 1730 return false; 1731 1732 return true; 1733 } 1734 EXPORT_SYMBOL(drm_edid_is_valid); 1735 1736 #define DDC_SEGMENT_ADDR 0x30 1737 /** 1738 * drm_do_probe_ddc_edid() - get EDID information via I2C 1739 * @data: I2C device adapter 1740 * @buf: EDID data buffer to be filled 1741 * @block: 128 byte EDID block to start fetching from 1742 * @len: EDID data buffer length to fetch 1743 * 1744 * Try to fetch EDID information by calling I2C driver functions. 1745 * 1746 * Return: 0 on success or -1 on failure. 1747 */ 1748 static int 1749 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 1750 { 1751 struct i2c_adapter *adapter = data; 1752 unsigned char start = block * EDID_LENGTH; 1753 unsigned char segment = block >> 1; 1754 unsigned char xfers = segment ? 3 : 2; 1755 int ret, retries = 5; 1756 1757 /* 1758 * The core I2C driver will automatically retry the transfer if the 1759 * adapter reports EAGAIN. However, we find that bit-banging transfers 1760 * are susceptible to errors under a heavily loaded machine and 1761 * generate spurious NAKs and timeouts. Retrying the transfer 1762 * of the individual block a few times seems to overcome this. 1763 */ 1764 do { 1765 struct i2c_msg msgs[] = { 1766 { 1767 .addr = DDC_SEGMENT_ADDR, 1768 .flags = 0, 1769 .len = 1, 1770 .buf = &segment, 1771 }, { 1772 .addr = DDC_ADDR, 1773 .flags = 0, 1774 .len = 1, 1775 .buf = &start, 1776 }, { 1777 .addr = DDC_ADDR, 1778 .flags = I2C_M_RD, 1779 .len = len, 1780 .buf = buf, 1781 } 1782 }; 1783 1784 /* 1785 * Avoid sending the segment addr to not upset non-compliant 1786 * DDC monitors. 1787 */ 1788 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 1789 1790 if (ret == -ENXIO) { 1791 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 1792 adapter->name); 1793 break; 1794 } 1795 } while (ret != xfers && --retries); 1796 1797 return ret == xfers ? 0 : -1; 1798 } 1799 1800 static void connector_bad_edid(struct drm_connector *connector, 1801 u8 *edid, int num_blocks) 1802 { 1803 int i; 1804 1805 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 1806 return; 1807 1808 dev_warn(connector->dev->dev, 1809 "%s: EDID is invalid:\n", 1810 connector->name); 1811 for (i = 0; i < num_blocks; i++) { 1812 u8 *block = edid + i * EDID_LENGTH; 1813 char prefix[20]; 1814 1815 if (drm_edid_is_zero(block, EDID_LENGTH)) 1816 snprintf(prefix, sizeof prefix, "\t[%02x] ZERO ", i); 1817 else if (!drm_edid_block_valid(block, i, false, NULL)) 1818 snprintf(prefix, sizeof prefix, "\t[%02x] BAD ", i); 1819 else 1820 snprintf(prefix, sizeof prefix, "\t[%02x] GOOD ", i); 1821 1822 print_hex_dump(KERN_WARNING, 1823 prefix, DUMP_PREFIX_NONE, 16, 1, 1824 block, EDID_LENGTH, false); 1825 } 1826 } 1827 1828 /* Get override or firmware EDID */ 1829 static struct edid *drm_get_override_edid(struct drm_connector *connector) 1830 { 1831 struct edid *override = NULL; 1832 1833 if (connector->override_edid) 1834 override = drm_edid_duplicate(connector->edid_blob_ptr->data); 1835 1836 if (!override) 1837 override = drm_load_edid_firmware(connector); 1838 1839 return IS_ERR(override) ? NULL : override; 1840 } 1841 1842 /** 1843 * drm_add_override_edid_modes - add modes from override/firmware EDID 1844 * @connector: connector we're probing 1845 * 1846 * Add modes from the override/firmware EDID, if available. Only to be used from 1847 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 1848 * failed during drm_get_edid() and caused the override/firmware EDID to be 1849 * skipped. 1850 * 1851 * Return: The number of modes added or 0 if we couldn't find any. 1852 */ 1853 int drm_add_override_edid_modes(struct drm_connector *connector) 1854 { 1855 struct edid *override; 1856 int num_modes = 0; 1857 1858 override = drm_get_override_edid(connector); 1859 if (override) { 1860 drm_connector_update_edid_property(connector, override); 1861 num_modes = drm_add_edid_modes(connector, override); 1862 kfree(override); 1863 1864 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 1865 connector->base.id, connector->name, num_modes); 1866 } 1867 1868 return num_modes; 1869 } 1870 EXPORT_SYMBOL(drm_add_override_edid_modes); 1871 1872 /** 1873 * drm_do_get_edid - get EDID data using a custom EDID block read function 1874 * @connector: connector we're probing 1875 * @get_edid_block: EDID block read function 1876 * @data: private data passed to the block read function 1877 * 1878 * When the I2C adapter connected to the DDC bus is hidden behind a device that 1879 * exposes a different interface to read EDID blocks this function can be used 1880 * to get EDID data using a custom block read function. 1881 * 1882 * As in the general case the DDC bus is accessible by the kernel at the I2C 1883 * level, drivers must make all reasonable efforts to expose it as an I2C 1884 * adapter and use drm_get_edid() instead of abusing this function. 1885 * 1886 * The EDID may be overridden using debugfs override_edid or firmare EDID 1887 * (drm_load_edid_firmware() and drm.edid_firmware parameter), in this priority 1888 * order. Having either of them bypasses actual EDID reads. 1889 * 1890 * Return: Pointer to valid EDID or NULL if we couldn't find any. 1891 */ 1892 struct edid *drm_do_get_edid(struct drm_connector *connector, 1893 int (*get_edid_block)(void *data, u8 *buf, unsigned int block, 1894 size_t len), 1895 void *data) 1896 { 1897 int i, j = 0, valid_extensions = 0; 1898 u8 *edid, *new; 1899 struct edid *override; 1900 1901 override = drm_get_override_edid(connector); 1902 if (override) 1903 return override; 1904 1905 if ((edid = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) 1906 return NULL; 1907 1908 /* base block fetch */ 1909 for (i = 0; i < 4; i++) { 1910 if (get_edid_block(data, edid, 0, EDID_LENGTH)) 1911 goto out; 1912 if (drm_edid_block_valid(edid, 0, false, 1913 &connector->edid_corrupt)) 1914 break; 1915 if (i == 0 && drm_edid_is_zero(edid, EDID_LENGTH)) { 1916 connector->null_edid_counter++; 1917 goto carp; 1918 } 1919 } 1920 if (i == 4) 1921 goto carp; 1922 1923 /* if there's no extensions, we're done */ 1924 valid_extensions = edid[0x7e]; 1925 if (valid_extensions == 0) 1926 return (struct edid *)edid; 1927 1928 new = krealloc(edid, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); 1929 if (!new) 1930 goto out; 1931 edid = new; 1932 1933 for (j = 1; j <= edid[0x7e]; j++) { 1934 u8 *block = edid + j * EDID_LENGTH; 1935 1936 for (i = 0; i < 4; i++) { 1937 if (get_edid_block(data, block, j, EDID_LENGTH)) 1938 goto out; 1939 if (drm_edid_block_valid(block, j, false, NULL)) 1940 break; 1941 } 1942 1943 if (i == 4) 1944 valid_extensions--; 1945 } 1946 1947 if (valid_extensions != edid[0x7e]) { 1948 u8 *base; 1949 1950 connector_bad_edid(connector, edid, edid[0x7e] + 1); 1951 1952 edid[EDID_LENGTH-1] += edid[0x7e] - valid_extensions; 1953 edid[0x7e] = valid_extensions; 1954 1955 new = kmalloc_array(valid_extensions + 1, EDID_LENGTH, 1956 GFP_KERNEL); 1957 if (!new) 1958 goto out; 1959 1960 base = new; 1961 for (i = 0; i <= edid[0x7e]; i++) { 1962 u8 *block = edid + i * EDID_LENGTH; 1963 1964 if (!drm_edid_block_valid(block, i, false, NULL)) 1965 continue; 1966 1967 memcpy(base, block, EDID_LENGTH); 1968 base += EDID_LENGTH; 1969 } 1970 1971 kfree(edid); 1972 edid = new; 1973 } 1974 1975 return (struct edid *)edid; 1976 1977 carp: 1978 connector_bad_edid(connector, edid, 1); 1979 out: 1980 kfree(edid); 1981 return NULL; 1982 } 1983 EXPORT_SYMBOL_GPL(drm_do_get_edid); 1984 1985 /** 1986 * drm_probe_ddc() - probe DDC presence 1987 * @adapter: I2C adapter to probe 1988 * 1989 * Return: True on success, false on failure. 1990 */ 1991 bool 1992 drm_probe_ddc(struct i2c_adapter *adapter) 1993 { 1994 unsigned char out; 1995 1996 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 1997 } 1998 EXPORT_SYMBOL(drm_probe_ddc); 1999 2000 /** 2001 * drm_get_edid - get EDID data, if available 2002 * @connector: connector we're probing 2003 * @adapter: I2C adapter to use for DDC 2004 * 2005 * Poke the given I2C channel to grab EDID data if possible. If found, 2006 * attach it to the connector. 2007 * 2008 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2009 */ 2010 struct edid *drm_get_edid(struct drm_connector *connector, 2011 struct i2c_adapter *adapter) 2012 { 2013 struct edid *edid; 2014 2015 if (connector->force == DRM_FORCE_OFF) 2016 return NULL; 2017 2018 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2019 return NULL; 2020 2021 edid = drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter); 2022 if (edid) 2023 drm_get_displayid(connector, edid); 2024 return edid; 2025 } 2026 EXPORT_SYMBOL(drm_get_edid); 2027 2028 /** 2029 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2030 * @connector: connector we're probing 2031 * @adapter: I2C adapter to use for DDC 2032 * 2033 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2034 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2035 * switch DDC to the GPU which is retrieving EDID. 2036 * 2037 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2038 */ 2039 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2040 struct i2c_adapter *adapter) 2041 { 2042 #ifndef __NetBSD__ /* XXX vga switcheroo */ 2043 struct pci_dev *pdev = connector->dev->pdev; 2044 #endif 2045 struct edid *edid; 2046 2047 #ifndef __NetBSD__ /* XXX vga switcheroo */ 2048 vga_switcheroo_lock_ddc(pdev); 2049 #endif 2050 edid = drm_get_edid(connector, adapter); 2051 #ifndef __NetBSD__ /* XXX vga switcheroo */ 2052 vga_switcheroo_unlock_ddc(pdev); 2053 #endif 2054 2055 return edid; 2056 } 2057 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2058 2059 /** 2060 * drm_edid_duplicate - duplicate an EDID and the extensions 2061 * @edid: EDID to duplicate 2062 * 2063 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2064 */ 2065 struct edid *drm_edid_duplicate(const struct edid *edid) 2066 { 2067 return kmemdup(edid, (edid->extensions + 1) * EDID_LENGTH, GFP_KERNEL); 2068 } 2069 EXPORT_SYMBOL(drm_edid_duplicate); 2070 2071 /*** EDID parsing ***/ 2072 2073 /** 2074 * edid_vendor - match a string against EDID's obfuscated vendor field 2075 * @edid: EDID to match 2076 * @vendor: vendor string 2077 * 2078 * Returns true if @vendor is in @edid, false otherwise 2079 */ 2080 static bool edid_vendor(const struct edid *edid, const char *vendor) 2081 { 2082 char edid_vendor[3]; 2083 2084 edid_vendor[0] = ((edid->mfg_id[0] & 0x7c) >> 2) + '@'; 2085 edid_vendor[1] = (((edid->mfg_id[0] & 0x3) << 3) | 2086 ((edid->mfg_id[1] & 0xe0) >> 5)) + '@'; 2087 edid_vendor[2] = (edid->mfg_id[1] & 0x1f) + '@'; 2088 2089 return !strncmp(edid_vendor, vendor, 3); 2090 } 2091 2092 /** 2093 * edid_get_quirks - return quirk flags for a given EDID 2094 * @edid: EDID to process 2095 * 2096 * This tells subsequent routines what fixes they need to apply. 2097 */ 2098 static u32 edid_get_quirks(const struct edid *edid) 2099 { 2100 const struct edid_quirk *quirk; 2101 int i; 2102 2103 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2104 quirk = &edid_quirk_list[i]; 2105 2106 if (edid_vendor(edid, quirk->vendor) && 2107 (EDID_PRODUCT_ID(edid) == quirk->product_id)) 2108 return quirk->quirks; 2109 } 2110 2111 return 0; 2112 } 2113 2114 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2115 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2116 2117 /** 2118 * edid_fixup_preferred - set preferred modes based on quirk list 2119 * @connector: has mode list to fix up 2120 * @quirks: quirks list 2121 * 2122 * Walk the mode list for @connector, clearing the preferred status 2123 * on existing modes and setting it anew for the right mode ala @quirks. 2124 */ 2125 static void edid_fixup_preferred(struct drm_connector *connector, 2126 u32 quirks) 2127 { 2128 struct drm_display_mode *t, *cur_mode, *preferred_mode; 2129 int target_refresh = 0; 2130 int cur_vrefresh, preferred_vrefresh; 2131 2132 if (list_empty(&connector->probed_modes)) 2133 return; 2134 2135 if (quirks & EDID_QUIRK_PREFER_LARGE_60) 2136 target_refresh = 60; 2137 if (quirks & EDID_QUIRK_PREFER_LARGE_75) 2138 target_refresh = 75; 2139 2140 preferred_mode = list_first_entry(&connector->probed_modes, 2141 struct drm_display_mode, head); 2142 2143 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 2144 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 2145 2146 if (cur_mode == preferred_mode) 2147 continue; 2148 2149 /* Largest mode is preferred */ 2150 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 2151 preferred_mode = cur_mode; 2152 2153 cur_vrefresh = cur_mode->vrefresh ? 2154 cur_mode->vrefresh : drm_mode_vrefresh(cur_mode); 2155 preferred_vrefresh = preferred_mode->vrefresh ? 2156 preferred_mode->vrefresh : drm_mode_vrefresh(preferred_mode); 2157 /* At a given size, try to get closest to target refresh */ 2158 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 2159 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 2160 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 2161 preferred_mode = cur_mode; 2162 } 2163 } 2164 2165 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 2166 } 2167 2168 static bool 2169 mode_is_rb(const struct drm_display_mode *mode) 2170 { 2171 return (mode->htotal - mode->hdisplay == 160) && 2172 (mode->hsync_end - mode->hdisplay == 80) && 2173 (mode->hsync_end - mode->hsync_start == 32) && 2174 (mode->vsync_start - mode->vdisplay == 3); 2175 } 2176 2177 /* 2178 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 2179 * @dev: Device to duplicate against 2180 * @hsize: Mode width 2181 * @vsize: Mode height 2182 * @fresh: Mode refresh rate 2183 * @rb: Mode reduced-blanking-ness 2184 * 2185 * Walk the DMT mode list looking for a match for the given parameters. 2186 * 2187 * Return: A newly allocated copy of the mode, or NULL if not found. 2188 */ 2189 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 2190 int hsize, int vsize, int fresh, 2191 bool rb) 2192 { 2193 int i; 2194 2195 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2196 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 2197 if (hsize != ptr->hdisplay) 2198 continue; 2199 if (vsize != ptr->vdisplay) 2200 continue; 2201 if (fresh != drm_mode_vrefresh(ptr)) 2202 continue; 2203 if (rb != mode_is_rb(ptr)) 2204 continue; 2205 2206 return drm_mode_duplicate(dev, ptr); 2207 } 2208 2209 return NULL; 2210 } 2211 EXPORT_SYMBOL(drm_mode_find_dmt); 2212 2213 typedef void detailed_cb(struct detailed_timing *timing, void *closure); 2214 2215 static void 2216 cea_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2217 { 2218 int i, n = 0; 2219 u8 d = ext[0x02]; 2220 u8 *det_base = ext + d; 2221 2222 n = (127 - d) / 18; 2223 for (i = 0; i < n; i++) 2224 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2225 } 2226 2227 static void 2228 vtb_for_each_detailed_block(u8 *ext, detailed_cb *cb, void *closure) 2229 { 2230 unsigned int i, n = min((int)ext[0x02], 6); 2231 u8 *det_base = ext + 5; 2232 2233 if (ext[0x01] != 1) 2234 return; /* unknown version */ 2235 2236 for (i = 0; i < n; i++) 2237 cb((struct detailed_timing *)(det_base + 18 * i), closure); 2238 } 2239 2240 static void 2241 drm_for_each_detailed_block(u8 *raw_edid, detailed_cb *cb, void *closure) 2242 { 2243 int i; 2244 struct edid *edid = (struct edid *)raw_edid; 2245 2246 if (edid == NULL) 2247 return; 2248 2249 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 2250 cb(&(edid->detailed_timings[i]), closure); 2251 2252 for (i = 1; i <= raw_edid[0x7e]; i++) { 2253 u8 *ext = raw_edid + (i * EDID_LENGTH); 2254 switch (*ext) { 2255 case CEA_EXT: 2256 cea_for_each_detailed_block(ext, cb, closure); 2257 break; 2258 case VTB_EXT: 2259 vtb_for_each_detailed_block(ext, cb, closure); 2260 break; 2261 default: 2262 break; 2263 } 2264 } 2265 } 2266 2267 static void 2268 is_rb(struct detailed_timing *t, void *data) 2269 { 2270 u8 *r = (u8 *)t; 2271 if (r[3] == EDID_DETAIL_MONITOR_RANGE) 2272 if (r[15] & 0x10) 2273 *(bool *)data = true; 2274 } 2275 2276 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 2277 static bool 2278 drm_monitor_supports_rb(struct edid *edid) 2279 { 2280 if (edid->revision >= 4) { 2281 bool ret = false; 2282 drm_for_each_detailed_block((u8 *)edid, is_rb, &ret); 2283 return ret; 2284 } 2285 2286 return ((edid->input & DRM_EDID_INPUT_DIGITAL) != 0); 2287 } 2288 2289 static void 2290 find_gtf2(struct detailed_timing *t, void *data) 2291 { 2292 u8 *r = (u8 *)t; 2293 if (r[3] == EDID_DETAIL_MONITOR_RANGE && r[10] == 0x02) 2294 *(u8 **)data = r; 2295 } 2296 2297 /* Secondary GTF curve kicks in above some break frequency */ 2298 static int 2299 drm_gtf2_hbreak(struct edid *edid) 2300 { 2301 u8 *r = NULL; 2302 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2303 return r ? (r[12] * 2) : 0; 2304 } 2305 2306 static int 2307 drm_gtf2_2c(struct edid *edid) 2308 { 2309 u8 *r = NULL; 2310 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2311 return r ? r[13] : 0; 2312 } 2313 2314 static int 2315 drm_gtf2_m(struct edid *edid) 2316 { 2317 u8 *r = NULL; 2318 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2319 return r ? (r[15] << 8) + r[14] : 0; 2320 } 2321 2322 static int 2323 drm_gtf2_k(struct edid *edid) 2324 { 2325 u8 *r = NULL; 2326 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2327 return r ? r[16] : 0; 2328 } 2329 2330 static int 2331 drm_gtf2_2j(struct edid *edid) 2332 { 2333 u8 *r = NULL; 2334 drm_for_each_detailed_block((u8 *)edid, find_gtf2, &r); 2335 return r ? r[17] : 0; 2336 } 2337 2338 /** 2339 * standard_timing_level - get std. timing level(CVT/GTF/DMT) 2340 * @edid: EDID block to scan 2341 */ 2342 static int standard_timing_level(struct edid *edid) 2343 { 2344 if (edid->revision >= 2) { 2345 if (edid->revision >= 4 && (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF)) 2346 return LEVEL_CVT; 2347 if (drm_gtf2_hbreak(edid)) 2348 return LEVEL_GTF2; 2349 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 2350 return LEVEL_GTF; 2351 } 2352 return LEVEL_DMT; 2353 } 2354 2355 /* 2356 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 2357 * monitors fill with ascii space (0x20) instead. 2358 */ 2359 static int 2360 bad_std_timing(u8 a, u8 b) 2361 { 2362 return (a == 0x00 && b == 0x00) || 2363 (a == 0x01 && b == 0x01) || 2364 (a == 0x20 && b == 0x20); 2365 } 2366 2367 /** 2368 * drm_mode_std - convert standard mode info (width, height, refresh) into mode 2369 * @connector: connector of for the EDID block 2370 * @edid: EDID block to scan 2371 * @t: standard timing params 2372 * 2373 * Take the standard timing params (in this case width, aspect, and refresh) 2374 * and convert them into a real mode using CVT/GTF/DMT. 2375 */ 2376 static struct drm_display_mode * 2377 drm_mode_std(struct drm_connector *connector, struct edid *edid, 2378 struct std_timing *t) 2379 { 2380 struct drm_device *dev = connector->dev; 2381 struct drm_display_mode *m, *mode = NULL; 2382 int hsize, vsize; 2383 int vrefresh_rate; 2384 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 2385 >> EDID_TIMING_ASPECT_SHIFT; 2386 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 2387 >> EDID_TIMING_VFREQ_SHIFT; 2388 int timing_level = standard_timing_level(edid); 2389 2390 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 2391 return NULL; 2392 2393 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 2394 hsize = t->hsize * 8 + 248; 2395 /* vrefresh_rate = vfreq + 60 */ 2396 vrefresh_rate = vfreq + 60; 2397 /* the vdisplay is calculated based on the aspect ratio */ 2398 if (aspect_ratio == 0) { 2399 if (edid->revision < 3) 2400 vsize = hsize; 2401 else 2402 vsize = (hsize * 10) / 16; 2403 } else if (aspect_ratio == 1) 2404 vsize = (hsize * 3) / 4; 2405 else if (aspect_ratio == 2) 2406 vsize = (hsize * 4) / 5; 2407 else 2408 vsize = (hsize * 9) / 16; 2409 2410 /* HDTV hack, part 1 */ 2411 if (vrefresh_rate == 60 && 2412 ((hsize == 1360 && vsize == 765) || 2413 (hsize == 1368 && vsize == 769))) { 2414 hsize = 1366; 2415 vsize = 768; 2416 } 2417 2418 /* 2419 * If this connector already has a mode for this size and refresh 2420 * rate (because it came from detailed or CVT info), use that 2421 * instead. This way we don't have to guess at interlace or 2422 * reduced blanking. 2423 */ 2424 list_for_each_entry(m, &connector->probed_modes, head) 2425 if (m->hdisplay == hsize && m->vdisplay == vsize && 2426 drm_mode_vrefresh(m) == vrefresh_rate) 2427 return NULL; 2428 2429 /* HDTV hack, part 2 */ 2430 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 2431 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 2432 false); 2433 if (!mode) 2434 return NULL; 2435 mode->hdisplay = 1366; 2436 mode->hsync_start = mode->hsync_start - 1; 2437 mode->hsync_end = mode->hsync_end - 1; 2438 return mode; 2439 } 2440 2441 /* check whether it can be found in default mode table */ 2442 if (drm_monitor_supports_rb(edid)) { 2443 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 2444 true); 2445 if (mode) 2446 return mode; 2447 } 2448 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 2449 if (mode) 2450 return mode; 2451 2452 /* okay, generate it */ 2453 switch (timing_level) { 2454 case LEVEL_DMT: 2455 break; 2456 case LEVEL_GTF: 2457 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2458 break; 2459 case LEVEL_GTF2: 2460 /* 2461 * This is potentially wrong if there's ever a monitor with 2462 * more than one ranges section, each claiming a different 2463 * secondary GTF curve. Please don't do that. 2464 */ 2465 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 2466 if (!mode) 2467 return NULL; 2468 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(edid)) { 2469 drm_mode_destroy(dev, mode); 2470 mode = drm_gtf_mode_complex(dev, hsize, vsize, 2471 vrefresh_rate, 0, 0, 2472 drm_gtf2_m(edid), 2473 drm_gtf2_2c(edid), 2474 drm_gtf2_k(edid), 2475 drm_gtf2_2j(edid)); 2476 } 2477 break; 2478 case LEVEL_CVT: 2479 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 2480 false); 2481 break; 2482 } 2483 return mode; 2484 } 2485 2486 /* 2487 * EDID is delightfully ambiguous about how interlaced modes are to be 2488 * encoded. Our internal representation is of frame height, but some 2489 * HDTV detailed timings are encoded as field height. 2490 * 2491 * The format list here is from CEA, in frame size. Technically we 2492 * should be checking refresh rate too. Whatever. 2493 */ 2494 static void 2495 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 2496 struct detailed_pixel_timing *pt) 2497 { 2498 int i; 2499 static const struct { 2500 int w, h; 2501 } cea_interlaced[] = { 2502 { 1920, 1080 }, 2503 { 720, 480 }, 2504 { 1440, 480 }, 2505 { 2880, 480 }, 2506 { 720, 576 }, 2507 { 1440, 576 }, 2508 { 2880, 576 }, 2509 }; 2510 2511 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 2512 return; 2513 2514 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 2515 if ((mode->hdisplay == cea_interlaced[i].w) && 2516 (mode->vdisplay == cea_interlaced[i].h / 2)) { 2517 mode->vdisplay *= 2; 2518 mode->vsync_start *= 2; 2519 mode->vsync_end *= 2; 2520 mode->vtotal *= 2; 2521 mode->vtotal |= 1; 2522 } 2523 } 2524 2525 mode->flags |= DRM_MODE_FLAG_INTERLACE; 2526 } 2527 2528 /** 2529 * drm_mode_detailed - create a new mode from an EDID detailed timing section 2530 * @dev: DRM device (needed to create new mode) 2531 * @edid: EDID block 2532 * @timing: EDID detailed timing info 2533 * @quirks: quirks to apply 2534 * 2535 * An EDID detailed timing block contains enough info for us to create and 2536 * return a new struct drm_display_mode. 2537 */ 2538 static struct drm_display_mode *drm_mode_detailed(struct drm_device *dev, 2539 struct edid *edid, 2540 struct detailed_timing *timing, 2541 u32 quirks) 2542 { 2543 struct drm_display_mode *mode; 2544 struct detailed_pixel_timing *pt = &timing->data.pixel_data; 2545 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 2546 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 2547 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 2548 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 2549 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 2550 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 2551 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 2552 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 2553 2554 /* ignore tiny modes */ 2555 if (hactive < 64 || vactive < 64) 2556 return NULL; 2557 2558 if (pt->misc & DRM_EDID_PT_STEREO) { 2559 DRM_DEBUG_KMS("stereo mode not supported\n"); 2560 return NULL; 2561 } 2562 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 2563 DRM_DEBUG_KMS("composite sync not supported\n"); 2564 } 2565 2566 /* it is incorrect if hsync/vsync width is zero */ 2567 if (!hsync_pulse_width || !vsync_pulse_width) { 2568 DRM_DEBUG_KMS("Incorrect Detailed timing. " 2569 "Wrong Hsync/Vsync pulse width\n"); 2570 return NULL; 2571 } 2572 2573 if (quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 2574 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 2575 if (!mode) 2576 return NULL; 2577 2578 goto set_size; 2579 } 2580 2581 mode = drm_mode_create(dev); 2582 if (!mode) 2583 return NULL; 2584 2585 if (quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 2586 timing->pixel_clock = cpu_to_le16(1088); 2587 2588 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 2589 2590 mode->hdisplay = hactive; 2591 mode->hsync_start = mode->hdisplay + hsync_offset; 2592 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 2593 mode->htotal = mode->hdisplay + hblank; 2594 2595 mode->vdisplay = vactive; 2596 mode->vsync_start = mode->vdisplay + vsync_offset; 2597 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 2598 mode->vtotal = mode->vdisplay + vblank; 2599 2600 /* Some EDIDs have bogus h/vtotal values */ 2601 if (mode->hsync_end > mode->htotal) 2602 mode->htotal = mode->hsync_end + 1; 2603 if (mode->vsync_end > mode->vtotal) 2604 mode->vtotal = mode->vsync_end + 1; 2605 2606 drm_mode_do_interlace_quirk(mode, pt); 2607 2608 if (quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 2609 pt->misc |= DRM_EDID_PT_HSYNC_POSITIVE | DRM_EDID_PT_VSYNC_POSITIVE; 2610 } 2611 2612 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 2613 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 2614 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 2615 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 2616 2617 set_size: 2618 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 2619 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 2620 2621 if (quirks & EDID_QUIRK_DETAILED_IN_CM) { 2622 mode->width_mm *= 10; 2623 mode->height_mm *= 10; 2624 } 2625 2626 if (quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 2627 mode->width_mm = edid->width_cm * 10; 2628 mode->height_mm = edid->height_cm * 10; 2629 } 2630 2631 mode->type = DRM_MODE_TYPE_DRIVER; 2632 mode->vrefresh = drm_mode_vrefresh(mode); 2633 drm_mode_set_name(mode); 2634 2635 return mode; 2636 } 2637 2638 static bool 2639 mode_in_hsync_range(const struct drm_display_mode *mode, 2640 struct edid *edid, u8 *t) 2641 { 2642 int hsync, hmin, hmax; 2643 2644 hmin = t[7]; 2645 if (edid->revision >= 4) 2646 hmin += ((t[4] & 0x04) ? 255 : 0); 2647 hmax = t[8]; 2648 if (edid->revision >= 4) 2649 hmax += ((t[4] & 0x08) ? 255 : 0); 2650 hsync = drm_mode_hsync(mode); 2651 2652 return (hsync <= hmax && hsync >= hmin); 2653 } 2654 2655 static bool 2656 mode_in_vsync_range(const struct drm_display_mode *mode, 2657 struct edid *edid, u8 *t) 2658 { 2659 int vsync, vmin, vmax; 2660 2661 vmin = t[5]; 2662 if (edid->revision >= 4) 2663 vmin += ((t[4] & 0x01) ? 255 : 0); 2664 vmax = t[6]; 2665 if (edid->revision >= 4) 2666 vmax += ((t[4] & 0x02) ? 255 : 0); 2667 vsync = drm_mode_vrefresh(mode); 2668 2669 return (vsync <= vmax && vsync >= vmin); 2670 } 2671 2672 static u32 2673 range_pixel_clock(struct edid *edid, u8 *t) 2674 { 2675 /* unspecified */ 2676 if (t[9] == 0 || t[9] == 255) 2677 return 0; 2678 2679 /* 1.4 with CVT support gives us real precision, yay */ 2680 if (edid->revision >= 4 && t[10] == 0x04) 2681 return (t[9] * 10000) - ((t[12] >> 2) * 250); 2682 2683 /* 1.3 is pathetic, so fuzz up a bit */ 2684 return t[9] * 10000 + 5001; 2685 } 2686 2687 static bool 2688 mode_in_range(const struct drm_display_mode *mode, struct edid *edid, 2689 struct detailed_timing *timing) 2690 { 2691 u32 max_clock; 2692 u8 *t = (u8 *)timing; 2693 2694 if (!mode_in_hsync_range(mode, edid, t)) 2695 return false; 2696 2697 if (!mode_in_vsync_range(mode, edid, t)) 2698 return false; 2699 2700 if ((max_clock = range_pixel_clock(edid, t))) 2701 if (mode->clock > max_clock) 2702 return false; 2703 2704 /* 1.4 max horizontal check */ 2705 if (edid->revision >= 4 && t[10] == 0x04) 2706 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 2707 return false; 2708 2709 if (mode_is_rb(mode) && !drm_monitor_supports_rb(edid)) 2710 return false; 2711 2712 return true; 2713 } 2714 2715 static bool valid_inferred_mode(const struct drm_connector *connector, 2716 const struct drm_display_mode *mode) 2717 { 2718 const struct drm_display_mode *m; 2719 bool ok = false; 2720 2721 list_for_each_entry(m, &connector->probed_modes, head) { 2722 if (mode->hdisplay == m->hdisplay && 2723 mode->vdisplay == m->vdisplay && 2724 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 2725 return false; /* duplicated */ 2726 if (mode->hdisplay <= m->hdisplay && 2727 mode->vdisplay <= m->vdisplay) 2728 ok = true; 2729 } 2730 return ok; 2731 } 2732 2733 static int 2734 drm_dmt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2735 struct detailed_timing *timing) 2736 { 2737 int i, modes = 0; 2738 struct drm_display_mode *newmode; 2739 struct drm_device *dev = connector->dev; 2740 2741 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 2742 if (mode_in_range(drm_dmt_modes + i, edid, timing) && 2743 valid_inferred_mode(connector, drm_dmt_modes + i)) { 2744 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 2745 if (newmode) { 2746 drm_mode_probed_add(connector, newmode); 2747 modes++; 2748 } 2749 } 2750 } 2751 2752 return modes; 2753 } 2754 2755 /* fix up 1366x768 mode from 1368x768; 2756 * GFT/CVT can't express 1366 width which isn't dividable by 8 2757 */ 2758 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 2759 { 2760 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 2761 mode->hdisplay = 1366; 2762 mode->hsync_start--; 2763 mode->hsync_end--; 2764 drm_mode_set_name(mode); 2765 } 2766 } 2767 2768 static int 2769 drm_gtf_modes_for_range(struct drm_connector *connector, struct edid *edid, 2770 struct detailed_timing *timing) 2771 { 2772 int i, modes = 0; 2773 struct drm_display_mode *newmode; 2774 struct drm_device *dev = connector->dev; 2775 2776 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2777 const struct minimode *m = &extra_modes[i]; 2778 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 2779 if (!newmode) 2780 return modes; 2781 2782 drm_mode_fixup_1366x768(newmode); 2783 if (!mode_in_range(newmode, edid, timing) || 2784 !valid_inferred_mode(connector, newmode)) { 2785 drm_mode_destroy(dev, newmode); 2786 continue; 2787 } 2788 2789 drm_mode_probed_add(connector, newmode); 2790 modes++; 2791 } 2792 2793 return modes; 2794 } 2795 2796 static int 2797 drm_cvt_modes_for_range(struct drm_connector *connector, struct edid *edid, 2798 struct detailed_timing *timing) 2799 { 2800 int i, modes = 0; 2801 struct drm_display_mode *newmode; 2802 struct drm_device *dev = connector->dev; 2803 bool rb = drm_monitor_supports_rb(edid); 2804 2805 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 2806 const struct minimode *m = &extra_modes[i]; 2807 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 2808 if (!newmode) 2809 return modes; 2810 2811 drm_mode_fixup_1366x768(newmode); 2812 if (!mode_in_range(newmode, edid, timing) || 2813 !valid_inferred_mode(connector, newmode)) { 2814 drm_mode_destroy(dev, newmode); 2815 continue; 2816 } 2817 2818 drm_mode_probed_add(connector, newmode); 2819 modes++; 2820 } 2821 2822 return modes; 2823 } 2824 2825 static void 2826 do_inferred_modes(struct detailed_timing *timing, void *c) 2827 { 2828 struct detailed_mode_closure *closure = c; 2829 struct detailed_non_pixel *data = &timing->data.other_data; 2830 struct detailed_data_monitor_range *range = &data->data.range; 2831 2832 if (data->type != EDID_DETAIL_MONITOR_RANGE) 2833 return; 2834 2835 closure->modes += drm_dmt_modes_for_range(closure->connector, 2836 closure->edid, 2837 timing); 2838 2839 if (!version_greater(closure->edid, 1, 1)) 2840 return; /* GTF not defined yet */ 2841 2842 switch (range->flags) { 2843 case 0x02: /* secondary gtf, XXX could do more */ 2844 case 0x00: /* default gtf */ 2845 closure->modes += drm_gtf_modes_for_range(closure->connector, 2846 closure->edid, 2847 timing); 2848 break; 2849 case 0x04: /* cvt, only in 1.4+ */ 2850 if (!version_greater(closure->edid, 1, 3)) 2851 break; 2852 2853 closure->modes += drm_cvt_modes_for_range(closure->connector, 2854 closure->edid, 2855 timing); 2856 break; 2857 case 0x01: /* just the ranges, no formula */ 2858 default: 2859 break; 2860 } 2861 } 2862 2863 static int 2864 add_inferred_modes(struct drm_connector *connector, struct edid *edid) 2865 { 2866 struct detailed_mode_closure closure = { 2867 .connector = connector, 2868 .edid = edid, 2869 }; 2870 2871 if (version_greater(edid, 1, 0)) 2872 drm_for_each_detailed_block((u8 *)edid, do_inferred_modes, 2873 &closure); 2874 2875 return closure.modes; 2876 } 2877 2878 static int 2879 drm_est3_modes(struct drm_connector *connector, struct detailed_timing *timing) 2880 { 2881 int i, j, m, modes = 0; 2882 struct drm_display_mode *mode; 2883 u8 *est = ((u8 *)timing) + 6; 2884 2885 for (i = 0; i < 6; i++) { 2886 for (j = 7; j >= 0; j--) { 2887 m = (i * 8) + (7 - j); 2888 if (m >= ARRAY_SIZE(est3_modes)) 2889 break; 2890 if (est[i] & (1 << j)) { 2891 mode = drm_mode_find_dmt(connector->dev, 2892 est3_modes[m].w, 2893 est3_modes[m].h, 2894 est3_modes[m].r, 2895 est3_modes[m].rb); 2896 if (mode) { 2897 drm_mode_probed_add(connector, mode); 2898 modes++; 2899 } 2900 } 2901 } 2902 } 2903 2904 return modes; 2905 } 2906 2907 static void 2908 do_established_modes(struct detailed_timing *timing, void *c) 2909 { 2910 struct detailed_mode_closure *closure = c; 2911 struct detailed_non_pixel *data = &timing->data.other_data; 2912 2913 if (data->type == EDID_DETAIL_EST_TIMINGS) 2914 closure->modes += drm_est3_modes(closure->connector, timing); 2915 } 2916 2917 /** 2918 * add_established_modes - get est. modes from EDID and add them 2919 * @connector: connector to add mode(s) to 2920 * @edid: EDID block to scan 2921 * 2922 * Each EDID block contains a bitmap of the supported "established modes" list 2923 * (defined above). Tease them out and add them to the global modes list. 2924 */ 2925 static int 2926 add_established_modes(struct drm_connector *connector, struct edid *edid) 2927 { 2928 struct drm_device *dev = connector->dev; 2929 unsigned long est_bits = edid->established_timings.t1 | 2930 (edid->established_timings.t2 << 8) | 2931 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 2932 int i, modes = 0; 2933 struct detailed_mode_closure closure = { 2934 .connector = connector, 2935 .edid = edid, 2936 }; 2937 2938 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 2939 if (est_bits & (1<<i)) { 2940 struct drm_display_mode *newmode; 2941 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 2942 if (newmode) { 2943 drm_mode_probed_add(connector, newmode); 2944 modes++; 2945 } 2946 } 2947 } 2948 2949 if (version_greater(edid, 1, 0)) 2950 drm_for_each_detailed_block((u8 *)edid, 2951 do_established_modes, &closure); 2952 2953 return modes + closure.modes; 2954 } 2955 2956 static void 2957 do_standard_modes(struct detailed_timing *timing, void *c) 2958 { 2959 struct detailed_mode_closure *closure = c; 2960 struct detailed_non_pixel *data = &timing->data.other_data; 2961 struct drm_connector *connector = closure->connector; 2962 struct edid *edid = closure->edid; 2963 2964 if (data->type == EDID_DETAIL_STD_MODES) { 2965 int i; 2966 for (i = 0; i < 6; i++) { 2967 struct std_timing *std; 2968 struct drm_display_mode *newmode; 2969 2970 std = &data->data.timings[i]; 2971 newmode = drm_mode_std(connector, edid, std); 2972 if (newmode) { 2973 drm_mode_probed_add(connector, newmode); 2974 closure->modes++; 2975 } 2976 } 2977 } 2978 } 2979 2980 /** 2981 * add_standard_modes - get std. modes from EDID and add them 2982 * @connector: connector to add mode(s) to 2983 * @edid: EDID block to scan 2984 * 2985 * Standard modes can be calculated using the appropriate standard (DMT, 2986 * GTF or CVT. Grab them from @edid and add them to the list. 2987 */ 2988 static int 2989 add_standard_modes(struct drm_connector *connector, struct edid *edid) 2990 { 2991 int i, modes = 0; 2992 struct detailed_mode_closure closure = { 2993 .connector = connector, 2994 .edid = edid, 2995 }; 2996 2997 for (i = 0; i < EDID_STD_TIMINGS; i++) { 2998 struct drm_display_mode *newmode; 2999 3000 newmode = drm_mode_std(connector, edid, 3001 &edid->standard_timings[i]); 3002 if (newmode) { 3003 drm_mode_probed_add(connector, newmode); 3004 modes++; 3005 } 3006 } 3007 3008 if (version_greater(edid, 1, 0)) 3009 drm_for_each_detailed_block((u8 *)edid, do_standard_modes, 3010 &closure); 3011 3012 /* XXX should also look for standard codes in VTB blocks */ 3013 3014 return modes + closure.modes; 3015 } 3016 3017 static int drm_cvt_modes(struct drm_connector *connector, 3018 struct detailed_timing *timing) 3019 { 3020 int i, j, modes = 0; 3021 struct drm_display_mode *newmode; 3022 struct drm_device *dev = connector->dev; 3023 struct cvt_timing *cvt; 3024 const int rates[] = { 60, 85, 75, 60, 50 }; 3025 const u8 empty[3] = { 0, 0, 0 }; 3026 3027 for (i = 0; i < 4; i++) { 3028 int uninitialized_var(width), height; 3029 cvt = &(timing->data.other_data.data.cvt[i]); 3030 3031 if (!memcmp(cvt->code, empty, 3)) 3032 continue; 3033 3034 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 3035 switch (cvt->code[1] & 0x0c) { 3036 case 0x00: 3037 width = height * 4 / 3; 3038 break; 3039 case 0x04: 3040 width = height * 16 / 9; 3041 break; 3042 case 0x08: 3043 width = height * 16 / 10; 3044 break; 3045 case 0x0c: 3046 width = height * 15 / 9; 3047 break; 3048 } 3049 3050 for (j = 1; j < 5; j++) { 3051 if (cvt->code[2] & (1 << j)) { 3052 newmode = drm_cvt_mode(dev, width, height, 3053 rates[j], j == 0, 3054 false, false); 3055 if (newmode) { 3056 drm_mode_probed_add(connector, newmode); 3057 modes++; 3058 } 3059 } 3060 } 3061 } 3062 3063 return modes; 3064 } 3065 3066 static void 3067 do_cvt_mode(struct detailed_timing *timing, void *c) 3068 { 3069 struct detailed_mode_closure *closure = c; 3070 struct detailed_non_pixel *data = &timing->data.other_data; 3071 3072 if (data->type == EDID_DETAIL_CVT_3BYTE) 3073 closure->modes += drm_cvt_modes(closure->connector, timing); 3074 } 3075 3076 static int 3077 add_cvt_modes(struct drm_connector *connector, struct edid *edid) 3078 { 3079 struct detailed_mode_closure closure = { 3080 .connector = connector, 3081 .edid = edid, 3082 }; 3083 3084 if (version_greater(edid, 1, 2)) 3085 drm_for_each_detailed_block((u8 *)edid, do_cvt_mode, &closure); 3086 3087 /* XXX should also look for CVT codes in VTB blocks */ 3088 3089 return closure.modes; 3090 } 3091 3092 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode); 3093 3094 static void 3095 do_detailed_mode(struct detailed_timing *timing, void *c) 3096 { 3097 struct detailed_mode_closure *closure = c; 3098 struct drm_display_mode *newmode; 3099 3100 if (timing->pixel_clock) { 3101 newmode = drm_mode_detailed(closure->connector->dev, 3102 closure->edid, timing, 3103 closure->quirks); 3104 if (!newmode) 3105 return; 3106 3107 if (closure->preferred) 3108 newmode->type |= DRM_MODE_TYPE_PREFERRED; 3109 3110 /* 3111 * Detailed modes are limited to 10kHz pixel clock resolution, 3112 * so fix up anything that looks like CEA/HDMI mode, but the clock 3113 * is just slightly off. 3114 */ 3115 fixup_detailed_cea_mode_clock(newmode); 3116 3117 drm_mode_probed_add(closure->connector, newmode); 3118 closure->modes++; 3119 closure->preferred = false; 3120 } 3121 } 3122 3123 /* 3124 * add_detailed_modes - Add modes from detailed timings 3125 * @connector: attached connector 3126 * @edid: EDID block to scan 3127 * @quirks: quirks to apply 3128 */ 3129 static int 3130 add_detailed_modes(struct drm_connector *connector, struct edid *edid, 3131 u32 quirks) 3132 { 3133 struct detailed_mode_closure closure = { 3134 .connector = connector, 3135 .edid = edid, 3136 .preferred = true, 3137 .quirks = quirks, 3138 }; 3139 3140 if (closure.preferred && !version_greater(edid, 1, 3)) 3141 closure.preferred = 3142 (edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING); 3143 3144 drm_for_each_detailed_block((u8 *)edid, do_detailed_mode, &closure); 3145 3146 return closure.modes; 3147 } 3148 3149 #define AUDIO_BLOCK 0x01 3150 #define VIDEO_BLOCK 0x02 3151 #define VENDOR_BLOCK 0x03 3152 #define SPEAKER_BLOCK 0x04 3153 #define HDR_STATIC_METADATA_BLOCK 0x6 3154 #define USE_EXTENDED_TAG 0x07 3155 #define EXT_VIDEO_CAPABILITY_BLOCK 0x00 3156 #define EXT_VIDEO_DATA_BLOCK_420 0x0E 3157 #define EXT_VIDEO_CAP_BLOCK_Y420CMDB 0x0F 3158 #define EDID_BASIC_AUDIO (1 << 6) 3159 #define EDID_CEA_YCRCB444 (1 << 5) 3160 #define EDID_CEA_YCRCB422 (1 << 4) 3161 #define EDID_CEA_VCDB_QS (1 << 6) 3162 3163 /* 3164 * Search EDID for CEA extension block. 3165 */ 3166 static const u8 *drm_find_edid_extension(const struct edid *edid, int ext_id) 3167 { 3168 const u8 *edid_ext = NULL; 3169 int i; 3170 3171 /* No EDID or EDID extensions */ 3172 if (edid == NULL || edid->extensions == 0) 3173 return NULL; 3174 3175 /* Find CEA extension */ 3176 for (i = 0; i < edid->extensions; i++) { 3177 edid_ext = (const u8 *)edid + EDID_LENGTH * (i + 1); 3178 if (edid_ext[0] == ext_id) 3179 break; 3180 } 3181 3182 if (i == edid->extensions) 3183 return NULL; 3184 3185 return edid_ext; 3186 } 3187 3188 3189 static const u8 *drm_find_displayid_extension(const struct edid *edid) 3190 { 3191 return drm_find_edid_extension(edid, DISPLAYID_EXT); 3192 } 3193 3194 static const u8 *drm_find_cea_extension(const struct edid *edid) 3195 { 3196 int ret; 3197 int idx = 1; 3198 int length = EDID_LENGTH; 3199 const struct displayid_block *block; 3200 const u8 *cea; 3201 const u8 *displayid; 3202 3203 /* Look for a top level CEA extension block */ 3204 cea = drm_find_edid_extension(edid, CEA_EXT); 3205 if (cea) 3206 return cea; 3207 3208 /* CEA blocks can also be found embedded in a DisplayID block */ 3209 displayid = drm_find_displayid_extension(edid); 3210 if (!displayid) 3211 return NULL; 3212 3213 ret = validate_displayid(displayid, length, idx); 3214 if (ret) 3215 return NULL; 3216 3217 idx += sizeof(struct displayid_hdr); 3218 for_each_displayid_db(displayid, block, idx, length) { 3219 if (block->tag == DATA_BLOCK_CTA) { 3220 cea = (const u8 *)block; 3221 break; 3222 } 3223 } 3224 3225 return cea; 3226 } 3227 3228 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 3229 { 3230 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 3231 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 3232 3233 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 3234 return &edid_cea_modes_1[vic - 1]; 3235 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 3236 return &edid_cea_modes_193[vic - 193]; 3237 return NULL; 3238 } 3239 3240 static u8 cea_num_vics(void) 3241 { 3242 return 193 + ARRAY_SIZE(edid_cea_modes_193); 3243 } 3244 3245 static u8 cea_next_vic(u8 vic) 3246 { 3247 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 3248 vic = 193; 3249 return vic; 3250 } 3251 3252 /* 3253 * Calculate the alternate clock for the CEA mode 3254 * (60Hz vs. 59.94Hz etc.) 3255 */ 3256 static unsigned int 3257 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 3258 { 3259 unsigned int clock = cea_mode->clock; 3260 3261 if (cea_mode->vrefresh % 6 != 0) 3262 return clock; 3263 3264 /* 3265 * edid_cea_modes contains the 59.94Hz 3266 * variant for 240 and 480 line modes, 3267 * and the 60Hz variant otherwise. 3268 */ 3269 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 3270 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 3271 else 3272 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 3273 3274 return clock; 3275 } 3276 3277 static bool 3278 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 3279 { 3280 /* 3281 * For certain VICs the spec allows the vertical 3282 * front porch to vary by one or two lines. 3283 * 3284 * cea_modes[] stores the variant with the shortest 3285 * vertical front porch. We can adjust the mode to 3286 * get the other variants by simply increasing the 3287 * vertical front porch length. 3288 */ 3289 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 3290 cea_mode_for_vic(9)->vtotal != 262 || 3291 cea_mode_for_vic(12)->vtotal != 262 || 3292 cea_mode_for_vic(13)->vtotal != 262 || 3293 cea_mode_for_vic(23)->vtotal != 312 || 3294 cea_mode_for_vic(24)->vtotal != 312 || 3295 cea_mode_for_vic(27)->vtotal != 312 || 3296 cea_mode_for_vic(28)->vtotal != 312); 3297 3298 if (((vic == 8 || vic == 9 || 3299 vic == 12 || vic == 13) && mode->vtotal < 263) || 3300 ((vic == 23 || vic == 24 || 3301 vic == 27 || vic == 28) && mode->vtotal < 314)) { 3302 mode->vsync_start++; 3303 mode->vsync_end++; 3304 mode->vtotal++; 3305 3306 return true; 3307 } 3308 3309 return false; 3310 } 3311 3312 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 3313 unsigned int clock_tolerance) 3314 { 3315 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3316 u8 vic; 3317 3318 if (!to_match->clock) 3319 return 0; 3320 3321 if (to_match->picture_aspect_ratio) 3322 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3323 3324 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3325 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3326 unsigned int clock1, clock2; 3327 3328 /* Check both 60Hz and 59.94Hz */ 3329 clock1 = cea_mode.clock; 3330 clock2 = cea_mode_alternate_clock(&cea_mode); 3331 3332 if (abs(to_match->clock - clock1) > clock_tolerance && 3333 abs(to_match->clock - clock2) > clock_tolerance) 3334 continue; 3335 3336 do { 3337 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3338 return vic; 3339 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3340 } 3341 3342 return 0; 3343 } 3344 3345 /** 3346 * drm_match_cea_mode - look for a CEA mode matching given mode 3347 * @to_match: display mode 3348 * 3349 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 3350 * mode. 3351 */ 3352 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 3353 { 3354 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3355 u8 vic; 3356 3357 if (!to_match->clock) 3358 return 0; 3359 3360 if (to_match->picture_aspect_ratio) 3361 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3362 3363 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 3364 struct drm_display_mode cea_mode = *cea_mode_for_vic(vic); 3365 unsigned int clock1, clock2; 3366 3367 /* Check both 60Hz and 59.94Hz */ 3368 clock1 = cea_mode.clock; 3369 clock2 = cea_mode_alternate_clock(&cea_mode); 3370 3371 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 3372 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 3373 continue; 3374 3375 do { 3376 if (drm_mode_match(to_match, &cea_mode, match_flags)) 3377 return vic; 3378 } while (cea_mode_alternate_timings(vic, &cea_mode)); 3379 } 3380 3381 return 0; 3382 } 3383 EXPORT_SYMBOL(drm_match_cea_mode); 3384 3385 static bool drm_valid_cea_vic(u8 vic) 3386 { 3387 return cea_mode_for_vic(vic) != NULL; 3388 } 3389 3390 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 3391 { 3392 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 3393 3394 if (mode) 3395 return mode->picture_aspect_ratio; 3396 3397 return HDMI_PICTURE_ASPECT_NONE; 3398 } 3399 3400 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 3401 { 3402 return edid_4k_modes[video_code].picture_aspect_ratio; 3403 } 3404 3405 /* 3406 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 3407 * specific block). 3408 */ 3409 static unsigned int 3410 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 3411 { 3412 return cea_mode_alternate_clock(hdmi_mode); 3413 } 3414 3415 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 3416 unsigned int clock_tolerance) 3417 { 3418 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3419 u8 vic; 3420 3421 if (!to_match->clock) 3422 return 0; 3423 3424 if (to_match->picture_aspect_ratio) 3425 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3426 3427 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3428 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3429 unsigned int clock1, clock2; 3430 3431 /* Make sure to also match alternate clocks */ 3432 clock1 = hdmi_mode->clock; 3433 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3434 3435 if (abs(to_match->clock - clock1) > clock_tolerance && 3436 abs(to_match->clock - clock2) > clock_tolerance) 3437 continue; 3438 3439 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 3440 return vic; 3441 } 3442 3443 return 0; 3444 } 3445 3446 /* 3447 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 3448 * @to_match: display mode 3449 * 3450 * An HDMI mode is one defined in the HDMI vendor specific block. 3451 * 3452 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 3453 */ 3454 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 3455 { 3456 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 3457 u8 vic; 3458 3459 if (!to_match->clock) 3460 return 0; 3461 3462 if (to_match->picture_aspect_ratio) 3463 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 3464 3465 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 3466 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 3467 unsigned int clock1, clock2; 3468 3469 /* Make sure to also match alternate clocks */ 3470 clock1 = hdmi_mode->clock; 3471 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 3472 3473 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 3474 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 3475 drm_mode_match(to_match, hdmi_mode, match_flags)) 3476 return vic; 3477 } 3478 return 0; 3479 } 3480 3481 static bool drm_valid_hdmi_vic(u8 vic) 3482 { 3483 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 3484 } 3485 3486 static int 3487 add_alternate_cea_modes(struct drm_connector *connector, struct edid *edid) 3488 { 3489 struct drm_device *dev = connector->dev; 3490 struct drm_display_mode *mode, *tmp; 3491 LIST_HEAD(list); 3492 int modes = 0; 3493 3494 /* Don't add CEA modes if the CEA extension block is missing */ 3495 if (!drm_find_cea_extension(edid)) 3496 return 0; 3497 3498 /* 3499 * Go through all probed modes and create a new mode 3500 * with the alternate clock for certain CEA modes. 3501 */ 3502 list_for_each_entry(mode, &connector->probed_modes, head) { 3503 const struct drm_display_mode *cea_mode = NULL; 3504 struct drm_display_mode *newmode; 3505 u8 vic = drm_match_cea_mode(mode); 3506 unsigned int clock1, clock2; 3507 3508 if (drm_valid_cea_vic(vic)) { 3509 cea_mode = cea_mode_for_vic(vic); 3510 clock2 = cea_mode_alternate_clock(cea_mode); 3511 } else { 3512 vic = drm_match_hdmi_mode(mode); 3513 if (drm_valid_hdmi_vic(vic)) { 3514 cea_mode = &edid_4k_modes[vic]; 3515 clock2 = hdmi_mode_alternate_clock(cea_mode); 3516 } 3517 } 3518 3519 if (!cea_mode) 3520 continue; 3521 3522 clock1 = cea_mode->clock; 3523 3524 if (clock1 == clock2) 3525 continue; 3526 3527 if (mode->clock != clock1 && mode->clock != clock2) 3528 continue; 3529 3530 newmode = drm_mode_duplicate(dev, cea_mode); 3531 if (!newmode) 3532 continue; 3533 3534 /* Carry over the stereo flags */ 3535 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 3536 3537 /* 3538 * The current mode could be either variant. Make 3539 * sure to pick the "other" clock for the new mode. 3540 */ 3541 if (mode->clock != clock1) 3542 newmode->clock = clock1; 3543 else 3544 newmode->clock = clock2; 3545 3546 list_add_tail(&newmode->head, &list); 3547 } 3548 3549 list_for_each_entry_safe(mode, tmp, &list, head) { 3550 list_del(&mode->head); 3551 drm_mode_probed_add(connector, mode); 3552 modes++; 3553 } 3554 3555 return modes; 3556 } 3557 3558 static u8 svd_to_vic(u8 svd) 3559 { 3560 /* 0-6 bit vic, 7th bit native mode indicator */ 3561 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 3562 return svd & 127; 3563 3564 return svd; 3565 } 3566 3567 static struct drm_display_mode * 3568 drm_display_mode_from_vic_index(struct drm_connector *connector, 3569 const u8 *video_db, u8 video_len, 3570 u8 video_index) 3571 { 3572 struct drm_device *dev = connector->dev; 3573 struct drm_display_mode *newmode; 3574 u8 vic; 3575 3576 if (video_db == NULL || video_index >= video_len) 3577 return NULL; 3578 3579 /* CEA modes are numbered 1..127 */ 3580 vic = svd_to_vic(video_db[video_index]); 3581 if (!drm_valid_cea_vic(vic)) 3582 return NULL; 3583 3584 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3585 if (!newmode) 3586 return NULL; 3587 3588 newmode->vrefresh = 0; 3589 3590 return newmode; 3591 } 3592 3593 /* 3594 * do_y420vdb_modes - Parse YCBCR 420 only modes 3595 * @connector: connector corresponding to the HDMI sink 3596 * @svds: start of the data block of CEA YCBCR 420 VDB 3597 * @len: length of the CEA YCBCR 420 VDB 3598 * 3599 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 3600 * which contains modes which can be supported in YCBCR 420 3601 * output format only. 3602 */ 3603 static int do_y420vdb_modes(struct drm_connector *connector, 3604 const u8 *svds, u8 svds_len) 3605 { 3606 int modes = 0, i; 3607 struct drm_device *dev = connector->dev; 3608 struct drm_display_info *info = &connector->display_info; 3609 struct drm_hdmi_info *hdmi = &info->hdmi; 3610 3611 for (i = 0; i < svds_len; i++) { 3612 u8 vic = svd_to_vic(svds[i]); 3613 struct drm_display_mode *newmode; 3614 3615 if (!drm_valid_cea_vic(vic)) 3616 continue; 3617 3618 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 3619 if (!newmode) 3620 break; 3621 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 3622 drm_mode_probed_add(connector, newmode); 3623 modes++; 3624 } 3625 3626 if (modes > 0) 3627 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 3628 return modes; 3629 } 3630 3631 /* 3632 * drm_add_cmdb_modes - Add a YCBCR 420 mode into bitmap 3633 * @connector: connector corresponding to the HDMI sink 3634 * @vic: CEA vic for the video mode to be added in the map 3635 * 3636 * Makes an entry for a videomode in the YCBCR 420 bitmap 3637 */ 3638 static void 3639 drm_add_cmdb_modes(struct drm_connector *connector, u8 svd) 3640 { 3641 u8 vic = svd_to_vic(svd); 3642 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3643 3644 if (!drm_valid_cea_vic(vic)) 3645 return; 3646 3647 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 3648 } 3649 3650 static int 3651 do_cea_modes(struct drm_connector *connector, const u8 *db, u8 len) 3652 { 3653 int i, modes = 0; 3654 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3655 3656 for (i = 0; i < len; i++) { 3657 struct drm_display_mode *mode; 3658 mode = drm_display_mode_from_vic_index(connector, db, len, i); 3659 if (mode) { 3660 /* 3661 * YCBCR420 capability block contains a bitmap which 3662 * gives the index of CEA modes from CEA VDB, which 3663 * can support YCBCR 420 sampling output also (apart 3664 * from RGB/YCBCR444 etc). 3665 * For example, if the bit 0 in bitmap is set, 3666 * first mode in VDB can support YCBCR420 output too. 3667 * Add YCBCR420 modes only if sink is HDMI 2.0 capable. 3668 */ 3669 if (i < 64 && hdmi->y420_cmdb_map & (1ULL << i)) 3670 drm_add_cmdb_modes(connector, db[i]); 3671 3672 drm_mode_probed_add(connector, mode); 3673 modes++; 3674 } 3675 } 3676 3677 return modes; 3678 } 3679 3680 struct stereo_mandatory_mode { 3681 int width, height, vrefresh; 3682 unsigned int flags; 3683 }; 3684 3685 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 3686 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3687 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3688 { 1920, 1080, 50, 3689 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3690 { 1920, 1080, 60, 3691 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 3692 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3693 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 3694 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 3695 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 3696 }; 3697 3698 static bool 3699 stereo_match_mandatory(const struct drm_display_mode *mode, 3700 const struct stereo_mandatory_mode *stereo_mode) 3701 { 3702 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 3703 3704 return mode->hdisplay == stereo_mode->width && 3705 mode->vdisplay == stereo_mode->height && 3706 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 3707 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 3708 } 3709 3710 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 3711 { 3712 struct drm_device *dev = connector->dev; 3713 const struct drm_display_mode *mode; 3714 struct list_head stereo_modes; 3715 int modes = 0, i; 3716 3717 INIT_LIST_HEAD(&stereo_modes); 3718 3719 list_for_each_entry(mode, &connector->probed_modes, head) { 3720 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 3721 const struct stereo_mandatory_mode *mandatory; 3722 struct drm_display_mode *new_mode; 3723 3724 if (!stereo_match_mandatory(mode, 3725 &stereo_mandatory_modes[i])) 3726 continue; 3727 3728 mandatory = &stereo_mandatory_modes[i]; 3729 new_mode = drm_mode_duplicate(dev, mode); 3730 if (!new_mode) 3731 continue; 3732 3733 new_mode->flags |= mandatory->flags; 3734 list_add_tail(&new_mode->head, &stereo_modes); 3735 modes++; 3736 } 3737 } 3738 3739 list_splice_tail(&stereo_modes, &connector->probed_modes); 3740 3741 return modes; 3742 } 3743 3744 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 3745 { 3746 struct drm_device *dev = connector->dev; 3747 struct drm_display_mode *newmode; 3748 3749 if (!drm_valid_hdmi_vic(vic)) { 3750 DRM_ERROR("Unknown HDMI VIC: %d\n", vic); 3751 return 0; 3752 } 3753 3754 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 3755 if (!newmode) 3756 return 0; 3757 3758 drm_mode_probed_add(connector, newmode); 3759 3760 return 1; 3761 } 3762 3763 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 3764 const u8 *video_db, u8 video_len, u8 video_index) 3765 { 3766 struct drm_display_mode *newmode; 3767 int modes = 0; 3768 3769 if (structure & (1 << 0)) { 3770 newmode = drm_display_mode_from_vic_index(connector, video_db, 3771 video_len, 3772 video_index); 3773 if (newmode) { 3774 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 3775 drm_mode_probed_add(connector, newmode); 3776 modes++; 3777 } 3778 } 3779 if (structure & (1 << 6)) { 3780 newmode = drm_display_mode_from_vic_index(connector, video_db, 3781 video_len, 3782 video_index); 3783 if (newmode) { 3784 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3785 drm_mode_probed_add(connector, newmode); 3786 modes++; 3787 } 3788 } 3789 if (structure & (1 << 8)) { 3790 newmode = drm_display_mode_from_vic_index(connector, video_db, 3791 video_len, 3792 video_index); 3793 if (newmode) { 3794 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3795 drm_mode_probed_add(connector, newmode); 3796 modes++; 3797 } 3798 } 3799 3800 return modes; 3801 } 3802 3803 /* 3804 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 3805 * @connector: connector corresponding to the HDMI sink 3806 * @db: start of the CEA vendor specific block 3807 * @len: length of the CEA block payload, ie. one can access up to db[len] 3808 * 3809 * Parses the HDMI VSDB looking for modes to add to @connector. This function 3810 * also adds the stereo 3d modes when applicable. 3811 */ 3812 static int 3813 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len, 3814 const u8 *video_db, u8 video_len) 3815 { 3816 struct drm_display_info *info = &connector->display_info; 3817 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 3818 u8 vic_len, hdmi_3d_len = 0; 3819 u16 mask; 3820 u16 structure_all; 3821 3822 if (len < 8) 3823 goto out; 3824 3825 /* no HDMI_Video_Present */ 3826 if (!(db[8] & (1 << 5))) 3827 goto out; 3828 3829 /* Latency_Fields_Present */ 3830 if (db[8] & (1 << 7)) 3831 offset += 2; 3832 3833 /* I_Latency_Fields_Present */ 3834 if (db[8] & (1 << 6)) 3835 offset += 2; 3836 3837 /* the declared length is not long enough for the 2 first bytes 3838 * of additional video format capabilities */ 3839 if (len < (8 + offset + 2)) 3840 goto out; 3841 3842 /* 3D_Present */ 3843 offset++; 3844 if (db[8 + offset] & (1 << 7)) { 3845 modes += add_hdmi_mandatory_stereo_modes(connector); 3846 3847 /* 3D_Multi_present */ 3848 multi_present = (db[8 + offset] & 0x60) >> 5; 3849 } 3850 3851 offset++; 3852 vic_len = db[8 + offset] >> 5; 3853 hdmi_3d_len = db[8 + offset] & 0x1f; 3854 3855 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 3856 u8 vic; 3857 3858 vic = db[9 + offset + i]; 3859 modes += add_hdmi_mode(connector, vic); 3860 } 3861 offset += 1 + vic_len; 3862 3863 if (multi_present == 1) 3864 multi_len = 2; 3865 else if (multi_present == 2) 3866 multi_len = 4; 3867 else 3868 multi_len = 0; 3869 3870 if (len < (8 + offset + hdmi_3d_len - 1)) 3871 goto out; 3872 3873 if (hdmi_3d_len < multi_len) 3874 goto out; 3875 3876 if (multi_present == 1 || multi_present == 2) { 3877 /* 3D_Structure_ALL */ 3878 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 3879 3880 /* check if 3D_MASK is present */ 3881 if (multi_present == 2) 3882 mask = (db[10 + offset] << 8) | db[11 + offset]; 3883 else 3884 mask = 0xffff; 3885 3886 for (i = 0; i < 16; i++) { 3887 if (mask & (1 << i)) 3888 modes += add_3d_struct_modes(connector, 3889 structure_all, 3890 video_db, 3891 video_len, i); 3892 } 3893 } 3894 3895 offset += multi_len; 3896 3897 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 3898 int vic_index; 3899 struct drm_display_mode *newmode = NULL; 3900 unsigned int newflag = 0; 3901 bool detail_present; 3902 3903 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 3904 3905 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 3906 break; 3907 3908 /* 2D_VIC_order_X */ 3909 vic_index = db[8 + offset + i] >> 4; 3910 3911 /* 3D_Structure_X */ 3912 switch (db[8 + offset + i] & 0x0f) { 3913 case 0: 3914 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 3915 break; 3916 case 6: 3917 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 3918 break; 3919 case 8: 3920 /* 3D_Detail_X */ 3921 if ((db[9 + offset + i] >> 4) == 1) 3922 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 3923 break; 3924 } 3925 3926 if (newflag != 0) { 3927 newmode = drm_display_mode_from_vic_index(connector, 3928 video_db, 3929 video_len, 3930 vic_index); 3931 3932 if (newmode) { 3933 newmode->flags |= newflag; 3934 drm_mode_probed_add(connector, newmode); 3935 modes++; 3936 } 3937 } 3938 3939 if (detail_present) 3940 i++; 3941 } 3942 3943 out: 3944 if (modes > 0) 3945 info->has_hdmi_infoframe = true; 3946 return modes; 3947 } 3948 3949 static int 3950 cea_db_payload_len(const u8 *db) 3951 { 3952 return db[0] & 0x1f; 3953 } 3954 3955 static int 3956 cea_db_extended_tag(const u8 *db) 3957 { 3958 return db[1]; 3959 } 3960 3961 static int 3962 cea_db_tag(const u8 *db) 3963 { 3964 return db[0] >> 5; 3965 } 3966 3967 static int 3968 cea_revision(const u8 *cea) 3969 { 3970 return cea[1]; 3971 } 3972 3973 static int 3974 cea_db_offsets(const u8 *cea, int *start, int *end) 3975 { 3976 /* DisplayID CTA extension blocks and top-level CEA EDID 3977 * block header definitions differ in the following bytes: 3978 * 1) Byte 2 of the header specifies length differently, 3979 * 2) Byte 3 is only present in the CEA top level block. 3980 * 3981 * The different definitions for byte 2 follow. 3982 * 3983 * DisplayID CTA extension block defines byte 2 as: 3984 * Number of payload bytes 3985 * 3986 * CEA EDID block defines byte 2 as: 3987 * Byte number (decimal) within this block where the 18-byte 3988 * DTDs begin. If no non-DTD data is present in this extension 3989 * block, the value should be set to 04h (the byte after next). 3990 * If set to 00h, there are no DTDs present in this block and 3991 * no non-DTD data. 3992 */ 3993 if (cea[0] == DATA_BLOCK_CTA) { 3994 *start = 3; 3995 *end = *start + cea[2]; 3996 } else if (cea[0] == CEA_EXT) { 3997 /* Data block offset in CEA extension block */ 3998 *start = 4; 3999 *end = cea[2]; 4000 if (*end == 0) 4001 *end = 127; 4002 if (*end < 4 || *end > 127) 4003 return -ERANGE; 4004 } else { 4005 return -EOPNOTSUPP; 4006 } 4007 4008 return 0; 4009 } 4010 4011 static bool cea_db_is_hdmi_vsdb(const u8 *db) 4012 { 4013 int hdmi_id; 4014 4015 if (cea_db_tag(db) != VENDOR_BLOCK) 4016 return false; 4017 4018 if (cea_db_payload_len(db) < 5) 4019 return false; 4020 4021 hdmi_id = db[1] | (db[2] << 8) | (db[3] << 16); 4022 4023 return hdmi_id == HDMI_IEEE_OUI; 4024 } 4025 4026 static bool cea_db_is_hdmi_forum_vsdb(const u8 *db) 4027 { 4028 unsigned int oui; 4029 4030 if (cea_db_tag(db) != VENDOR_BLOCK) 4031 return false; 4032 4033 if (cea_db_payload_len(db) < 7) 4034 return false; 4035 4036 oui = db[3] << 16 | db[2] << 8 | db[1]; 4037 4038 return oui == HDMI_FORUM_IEEE_OUI; 4039 } 4040 4041 static bool cea_db_is_vcdb(const u8 *db) 4042 { 4043 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4044 return false; 4045 4046 if (cea_db_payload_len(db) != 2) 4047 return false; 4048 4049 if (cea_db_extended_tag(db) != EXT_VIDEO_CAPABILITY_BLOCK) 4050 return false; 4051 4052 return true; 4053 } 4054 4055 static bool cea_db_is_y420cmdb(const u8 *db) 4056 { 4057 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4058 return false; 4059 4060 if (!cea_db_payload_len(db)) 4061 return false; 4062 4063 if (cea_db_extended_tag(db) != EXT_VIDEO_CAP_BLOCK_Y420CMDB) 4064 return false; 4065 4066 return true; 4067 } 4068 4069 static bool cea_db_is_y420vdb(const u8 *db) 4070 { 4071 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4072 return false; 4073 4074 if (!cea_db_payload_len(db)) 4075 return false; 4076 4077 if (cea_db_extended_tag(db) != EXT_VIDEO_DATA_BLOCK_420) 4078 return false; 4079 4080 return true; 4081 } 4082 4083 #define for_each_cea_db(cea, i, start, end) \ 4084 for ((i) = (start); (i) < (end) && (i) + cea_db_payload_len(&(cea)[(i)]) < (end); (i) += cea_db_payload_len(&(cea)[(i)]) + 1) 4085 4086 static void drm_parse_y420cmdb_bitmap(struct drm_connector *connector, 4087 const u8 *db) 4088 { 4089 struct drm_display_info *info = &connector->display_info; 4090 struct drm_hdmi_info *hdmi = &info->hdmi; 4091 u8 map_len = cea_db_payload_len(db) - 1; 4092 u8 count; 4093 u64 map = 0; 4094 4095 if (map_len == 0) { 4096 /* All CEA modes support ycbcr420 sampling also.*/ 4097 hdmi->y420_cmdb_map = U64_MAX; 4098 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4099 return; 4100 } 4101 4102 /* 4103 * This map indicates which of the existing CEA block modes 4104 * from VDB can support YCBCR420 output too. So if bit=0 is 4105 * set, first mode from VDB can support YCBCR420 output too. 4106 * We will parse and keep this map, before parsing VDB itself 4107 * to avoid going through the same block again and again. 4108 * 4109 * Spec is not clear about max possible size of this block. 4110 * Clamping max bitmap block size at 8 bytes. Every byte can 4111 * address 8 CEA modes, in this way this map can address 4112 * 8*8 = first 64 SVDs. 4113 */ 4114 if (WARN_ON_ONCE(map_len > 8)) 4115 map_len = 8; 4116 4117 for (count = 0; count < map_len; count++) 4118 map |= (u64)db[2 + count] << (8 * count); 4119 4120 if (map) 4121 info->color_formats |= DRM_COLOR_FORMAT_YCRCB420; 4122 4123 hdmi->y420_cmdb_map = map; 4124 } 4125 4126 static int 4127 add_cea_modes(struct drm_connector *connector, struct edid *edid) 4128 { 4129 const u8 *cea = drm_find_cea_extension(edid); 4130 const u8 *db, *hdmi = NULL, *video = NULL; 4131 u8 dbl, hdmi_len, video_len = 0; 4132 int modes = 0; 4133 4134 if (cea && cea_revision(cea) >= 3) { 4135 int i, start, end; 4136 4137 if (cea_db_offsets(cea, &start, &end)) 4138 return 0; 4139 4140 for_each_cea_db(cea, i, start, end) { 4141 db = &cea[i]; 4142 dbl = cea_db_payload_len(db); 4143 4144 if (cea_db_tag(db) == VIDEO_BLOCK) { 4145 video = db + 1; 4146 video_len = dbl; 4147 modes += do_cea_modes(connector, video, dbl); 4148 } else if (cea_db_is_hdmi_vsdb(db)) { 4149 hdmi = db; 4150 hdmi_len = dbl; 4151 } else if (cea_db_is_y420vdb(db)) { 4152 const u8 *vdb420 = &db[2]; 4153 4154 /* Add 4:2:0(only) modes present in EDID */ 4155 modes += do_y420vdb_modes(connector, 4156 vdb420, 4157 dbl - 1); 4158 } 4159 } 4160 } 4161 4162 /* 4163 * We parse the HDMI VSDB after having added the cea modes as we will 4164 * be patching their flags when the sink supports stereo 3D. 4165 */ 4166 if (hdmi) 4167 modes += do_hdmi_vsdb_modes(connector, hdmi, hdmi_len, video, 4168 video_len); 4169 4170 return modes; 4171 } 4172 4173 static void fixup_detailed_cea_mode_clock(struct drm_display_mode *mode) 4174 { 4175 const struct drm_display_mode *cea_mode; 4176 int clock1, clock2, clock; 4177 u8 vic; 4178 const char *type; 4179 4180 /* 4181 * allow 5kHz clock difference either way to account for 4182 * the 10kHz clock resolution limit of detailed timings. 4183 */ 4184 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 4185 if (drm_valid_cea_vic(vic)) { 4186 type = "CEA"; 4187 cea_mode = cea_mode_for_vic(vic); 4188 clock1 = cea_mode->clock; 4189 clock2 = cea_mode_alternate_clock(cea_mode); 4190 } else { 4191 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 4192 if (drm_valid_hdmi_vic(vic)) { 4193 type = "HDMI"; 4194 cea_mode = &edid_4k_modes[vic]; 4195 clock1 = cea_mode->clock; 4196 clock2 = hdmi_mode_alternate_clock(cea_mode); 4197 } else { 4198 return; 4199 } 4200 } 4201 4202 /* pick whichever is closest */ 4203 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 4204 clock = clock1; 4205 else 4206 clock = clock2; 4207 4208 if (mode->clock == clock) 4209 return; 4210 4211 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 4212 type, vic, mode->clock, clock); 4213 mode->clock = clock; 4214 } 4215 4216 static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db) 4217 { 4218 if (cea_db_tag(db) != USE_EXTENDED_TAG) 4219 return false; 4220 4221 if (db[1] != HDR_STATIC_METADATA_BLOCK) 4222 return false; 4223 4224 if (cea_db_payload_len(db) < 3) 4225 return false; 4226 4227 return true; 4228 } 4229 4230 static uint8_t eotf_supported(const u8 *edid_ext) 4231 { 4232 return edid_ext[2] & 4233 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 4234 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 4235 BIT(HDMI_EOTF_SMPTE_ST2084) | 4236 BIT(HDMI_EOTF_BT_2100_HLG)); 4237 } 4238 4239 static uint8_t hdr_metadata_type(const u8 *edid_ext) 4240 { 4241 return edid_ext[3] & 4242 BIT(HDMI_STATIC_METADATA_TYPE1); 4243 } 4244 4245 static void 4246 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 4247 { 4248 u16 len; 4249 4250 len = cea_db_payload_len(db); 4251 4252 connector->hdr_sink_metadata.hdmi_type1.eotf = 4253 eotf_supported(db); 4254 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 4255 hdr_metadata_type(db); 4256 4257 if (len >= 4) 4258 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 4259 if (len >= 5) 4260 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 4261 if (len >= 6) 4262 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 4263 } 4264 4265 static void 4266 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 4267 { 4268 u8 len = cea_db_payload_len(db); 4269 4270 if (len >= 5) { 4271 connector->physical_address = (db[4] << 8) | db[5]; 4272 } 4273 if (len >= 6 && (db[6] & (1 << 7))) 4274 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 4275 if (len >= 8) { 4276 connector->latency_present[0] = db[8] >> 7; 4277 connector->latency_present[1] = (db[8] >> 6) & 1; 4278 } 4279 if (len >= 9) 4280 connector->video_latency[0] = db[9]; 4281 if (len >= 10) 4282 connector->audio_latency[0] = db[10]; 4283 if (len >= 11) 4284 connector->video_latency[1] = db[11]; 4285 if (len >= 12) 4286 connector->audio_latency[1] = db[12]; 4287 4288 DRM_DEBUG_KMS("HDMI: latency present %d %d, " 4289 "video latency %d %d, " 4290 "audio latency %d %d\n", 4291 connector->latency_present[0], 4292 connector->latency_present[1], 4293 connector->video_latency[0], 4294 connector->video_latency[1], 4295 connector->audio_latency[0], 4296 connector->audio_latency[1]); 4297 } 4298 4299 static void 4300 monitor_name(struct detailed_timing *t, void *data) 4301 { 4302 if (t->data.other_data.type == EDID_DETAIL_MONITOR_NAME) 4303 *(u8 **)data = t->data.other_data.data.str.str; 4304 } 4305 4306 static int get_monitor_name(struct edid *edid, char name[13]) 4307 { 4308 char *edid_name = NULL; 4309 int mnl; 4310 4311 if (!edid || !name) 4312 return 0; 4313 4314 drm_for_each_detailed_block((u8 *)edid, monitor_name, &edid_name); 4315 for (mnl = 0; edid_name && mnl < 13; mnl++) { 4316 if (edid_name[mnl] == 0x0a) 4317 break; 4318 4319 name[mnl] = edid_name[mnl]; 4320 } 4321 4322 return mnl; 4323 } 4324 4325 /** 4326 * drm_edid_get_monitor_name - fetch the monitor name from the edid 4327 * @edid: monitor EDID information 4328 * @name: pointer to a character array to hold the name of the monitor 4329 * @bufsize: The size of the name buffer (should be at least 14 chars.) 4330 * 4331 */ 4332 void drm_edid_get_monitor_name(struct edid *edid, char *name, int bufsize) 4333 { 4334 int name_length; 4335 char buf[13]; 4336 4337 if (bufsize <= 0) 4338 return; 4339 4340 name_length = min(get_monitor_name(edid, buf), bufsize - 1); 4341 memcpy(name, buf, name_length); 4342 name[name_length] = '\0'; 4343 } 4344 EXPORT_SYMBOL(drm_edid_get_monitor_name); 4345 4346 static void clear_eld(struct drm_connector *connector) 4347 { 4348 memset(connector->eld, 0, sizeof(connector->eld)); 4349 4350 connector->latency_present[0] = false; 4351 connector->latency_present[1] = false; 4352 connector->video_latency[0] = 0; 4353 connector->audio_latency[0] = 0; 4354 connector->video_latency[1] = 0; 4355 connector->audio_latency[1] = 0; 4356 } 4357 4358 /* 4359 * drm_edid_to_eld - build ELD from EDID 4360 * @connector: connector corresponding to the HDMI/DP sink 4361 * @edid: EDID to parse 4362 * 4363 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 4364 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 4365 */ 4366 static void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) 4367 { 4368 uint8_t *eld = connector->eld; 4369 const u8 *cea; 4370 const u8 *db; 4371 int total_sad_count = 0; 4372 int mnl; 4373 int dbl; 4374 4375 clear_eld(connector); 4376 4377 if (!edid) 4378 return; 4379 4380 cea = drm_find_cea_extension(edid); 4381 if (!cea) { 4382 DRM_DEBUG_KMS("ELD: no CEA Extension found\n"); 4383 return; 4384 } 4385 4386 mnl = get_monitor_name(edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 4387 DRM_DEBUG_KMS("ELD monitor %s\n", &eld[DRM_ELD_MONITOR_NAME_STRING]); 4388 4389 eld[DRM_ELD_CEA_EDID_VER_MNL] = cea[1] << DRM_ELD_CEA_EDID_VER_SHIFT; 4390 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 4391 4392 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 4393 4394 eld[DRM_ELD_MANUFACTURER_NAME0] = edid->mfg_id[0]; 4395 eld[DRM_ELD_MANUFACTURER_NAME1] = edid->mfg_id[1]; 4396 eld[DRM_ELD_PRODUCT_CODE0] = edid->prod_code[0]; 4397 eld[DRM_ELD_PRODUCT_CODE1] = edid->prod_code[1]; 4398 4399 if (cea_revision(cea) >= 3) { 4400 int i, start, end; 4401 4402 if (cea_db_offsets(cea, &start, &end)) { 4403 start = 0; 4404 end = 0; 4405 } 4406 4407 for_each_cea_db(cea, i, start, end) { 4408 db = &cea[i]; 4409 dbl = cea_db_payload_len(db); 4410 4411 switch (cea_db_tag(db)) { 4412 int sad_count; 4413 4414 case AUDIO_BLOCK: 4415 /* Audio Data Block, contains SADs */ 4416 sad_count = min(dbl / 3, 15 - total_sad_count); 4417 if (sad_count >= 1) 4418 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 4419 &db[1], sad_count * 3); 4420 total_sad_count += sad_count; 4421 break; 4422 case SPEAKER_BLOCK: 4423 /* Speaker Allocation Data Block */ 4424 if (dbl >= 1) 4425 eld[DRM_ELD_SPEAKER] = db[1]; 4426 break; 4427 case VENDOR_BLOCK: 4428 /* HDMI Vendor-Specific Data Block */ 4429 if (cea_db_is_hdmi_vsdb(db)) 4430 drm_parse_hdmi_vsdb_audio(connector, db); 4431 break; 4432 default: 4433 break; 4434 } 4435 } 4436 } 4437 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 4438 4439 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 4440 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 4441 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 4442 else 4443 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 4444 4445 eld[DRM_ELD_BASELINE_ELD_LEN] = 4446 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 4447 4448 DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", 4449 drm_eld_size(eld), total_sad_count); 4450 } 4451 4452 /** 4453 * drm_edid_to_sad - extracts SADs from EDID 4454 * @edid: EDID to parse 4455 * @sads: pointer that will be set to the extracted SADs 4456 * 4457 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 4458 * 4459 * Note: The returned pointer needs to be freed using kfree(). 4460 * 4461 * Return: The number of found SADs or negative number on error. 4462 */ 4463 int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads) 4464 { 4465 int count = 0; 4466 int i, start, end, dbl; 4467 const u8 *cea; 4468 4469 cea = drm_find_cea_extension(edid); 4470 if (!cea) { 4471 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4472 return 0; 4473 } 4474 4475 if (cea_revision(cea) < 3) { 4476 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4477 return 0; 4478 } 4479 4480 if (cea_db_offsets(cea, &start, &end)) { 4481 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4482 return -EPROTO; 4483 } 4484 4485 for_each_cea_db(cea, i, start, end) { 4486 const u8 *db = &cea[i]; 4487 4488 if (cea_db_tag(db) == AUDIO_BLOCK) { 4489 int j; 4490 dbl = cea_db_payload_len(db); 4491 4492 count = dbl / 3; /* SAD is 3B */ 4493 *sads = kcalloc(count, sizeof(**sads), GFP_KERNEL); 4494 if (!*sads) 4495 return -ENOMEM; 4496 for (j = 0; j < count; j++) { 4497 const u8 *sad = &db[1 + j * 3]; 4498 4499 (*sads)[j].format = (sad[0] & 0x78) >> 3; 4500 (*sads)[j].channels = sad[0] & 0x7; 4501 (*sads)[j].freq = sad[1] & 0x7F; 4502 (*sads)[j].byte2 = sad[2]; 4503 } 4504 break; 4505 } 4506 } 4507 4508 return count; 4509 } 4510 EXPORT_SYMBOL(drm_edid_to_sad); 4511 4512 /** 4513 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 4514 * @edid: EDID to parse 4515 * @sadb: pointer to the speaker block 4516 * 4517 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 4518 * 4519 * Note: The returned pointer needs to be freed using kfree(). 4520 * 4521 * Return: The number of found Speaker Allocation Blocks or negative number on 4522 * error. 4523 */ 4524 int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb) 4525 { 4526 int count = 0; 4527 int i, start, end, dbl; 4528 const u8 *cea; 4529 4530 cea = drm_find_cea_extension(edid); 4531 if (!cea) { 4532 DRM_DEBUG_KMS("SAD: no CEA Extension found\n"); 4533 return 0; 4534 } 4535 4536 if (cea_revision(cea) < 3) { 4537 DRM_DEBUG_KMS("SAD: wrong CEA revision\n"); 4538 return 0; 4539 } 4540 4541 if (cea_db_offsets(cea, &start, &end)) { 4542 DRM_DEBUG_KMS("SAD: invalid data block offsets\n"); 4543 return -EPROTO; 4544 } 4545 4546 for_each_cea_db(cea, i, start, end) { 4547 const u8 *db = &cea[i]; 4548 4549 if (cea_db_tag(db) == SPEAKER_BLOCK) { 4550 dbl = cea_db_payload_len(db); 4551 4552 /* Speaker Allocation Data Block */ 4553 if (dbl == 3) { 4554 *sadb = kmemdup(&db[1], dbl, GFP_KERNEL); 4555 if (!*sadb) 4556 return -ENOMEM; 4557 count = dbl; 4558 break; 4559 } 4560 } 4561 } 4562 4563 return count; 4564 } 4565 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 4566 4567 /** 4568 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 4569 * @connector: connector associated with the HDMI/DP sink 4570 * @mode: the display mode 4571 * 4572 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 4573 * the sink doesn't support audio or video. 4574 */ 4575 int drm_av_sync_delay(struct drm_connector *connector, 4576 const struct drm_display_mode *mode) 4577 { 4578 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 4579 int a, v; 4580 4581 if (!connector->latency_present[0]) 4582 return 0; 4583 if (!connector->latency_present[1]) 4584 i = 0; 4585 4586 a = connector->audio_latency[i]; 4587 v = connector->video_latency[i]; 4588 4589 /* 4590 * HDMI/DP sink doesn't support audio or video? 4591 */ 4592 if (a == 255 || v == 255) 4593 return 0; 4594 4595 /* 4596 * Convert raw EDID values to millisecond. 4597 * Treat unknown latency as 0ms. 4598 */ 4599 if (a) 4600 a = min(2 * (a - 1), 500); 4601 if (v) 4602 v = min(2 * (v - 1), 500); 4603 4604 return max(v - a, 0); 4605 } 4606 EXPORT_SYMBOL(drm_av_sync_delay); 4607 4608 /** 4609 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 4610 * @edid: monitor EDID information 4611 * 4612 * Parse the CEA extension according to CEA-861-B. 4613 * 4614 * Return: True if the monitor is HDMI, false if not or unknown. 4615 */ 4616 bool drm_detect_hdmi_monitor(struct edid *edid) 4617 { 4618 const u8 *edid_ext; 4619 int i; 4620 int start_offset, end_offset; 4621 4622 edid_ext = drm_find_cea_extension(edid); 4623 if (!edid_ext) 4624 return false; 4625 4626 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4627 return false; 4628 4629 /* 4630 * Because HDMI identifier is in Vendor Specific Block, 4631 * search it from all data blocks of CEA extension. 4632 */ 4633 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4634 if (cea_db_is_hdmi_vsdb(&edid_ext[i])) 4635 return true; 4636 } 4637 4638 return false; 4639 } 4640 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 4641 4642 /** 4643 * drm_detect_monitor_audio - check monitor audio capability 4644 * @edid: EDID block to scan 4645 * 4646 * Monitor should have CEA extension block. 4647 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 4648 * audio' only. If there is any audio extension block and supported 4649 * audio format, assume at least 'basic audio' support, even if 'basic 4650 * audio' is not defined in EDID. 4651 * 4652 * Return: True if the monitor supports audio, false otherwise. 4653 */ 4654 bool drm_detect_monitor_audio(struct edid *edid) 4655 { 4656 const u8 *edid_ext; 4657 int i, j; 4658 bool has_audio = false; 4659 int start_offset, end_offset; 4660 4661 edid_ext = drm_find_cea_extension(edid); 4662 if (!edid_ext) 4663 goto end; 4664 4665 has_audio = ((edid_ext[3] & EDID_BASIC_AUDIO) != 0); 4666 4667 if (has_audio) { 4668 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 4669 goto end; 4670 } 4671 4672 if (cea_db_offsets(edid_ext, &start_offset, &end_offset)) 4673 goto end; 4674 4675 for_each_cea_db(edid_ext, i, start_offset, end_offset) { 4676 if (cea_db_tag(&edid_ext[i]) == AUDIO_BLOCK) { 4677 has_audio = true; 4678 for (j = 1; j < cea_db_payload_len(&edid_ext[i]) + 1; j += 3) 4679 DRM_DEBUG_KMS("CEA audio format %d\n", 4680 (edid_ext[i + j] >> 3) & 0xf); 4681 goto end; 4682 } 4683 } 4684 end: 4685 return has_audio; 4686 } 4687 EXPORT_SYMBOL(drm_detect_monitor_audio); 4688 4689 4690 /** 4691 * drm_default_rgb_quant_range - default RGB quantization range 4692 * @mode: display mode 4693 * 4694 * Determine the default RGB quantization range for the mode, 4695 * as specified in CEA-861. 4696 * 4697 * Return: The default RGB quantization range for the mode 4698 */ 4699 enum hdmi_quantization_range 4700 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 4701 { 4702 /* All CEA modes other than VIC 1 use limited quantization range. */ 4703 return drm_match_cea_mode(mode) > 1 ? 4704 HDMI_QUANTIZATION_RANGE_LIMITED : 4705 HDMI_QUANTIZATION_RANGE_FULL; 4706 } 4707 EXPORT_SYMBOL(drm_default_rgb_quant_range); 4708 4709 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 4710 { 4711 struct drm_display_info *info = &connector->display_info; 4712 4713 DRM_DEBUG_KMS("CEA VCDB 0x%02x\n", db[2]); 4714 4715 if (db[2] & EDID_CEA_VCDB_QS) 4716 info->rgb_quant_range_selectable = true; 4717 } 4718 4719 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 4720 const u8 *db) 4721 { 4722 u8 dc_mask; 4723 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 4724 4725 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 4726 hdmi->y420_dc_modes = dc_mask; 4727 } 4728 4729 static void drm_parse_hdmi_forum_vsdb(struct drm_connector *connector, 4730 const u8 *hf_vsdb) 4731 { 4732 struct drm_display_info *display = &connector->display_info; 4733 struct drm_hdmi_info *hdmi = &display->hdmi; 4734 4735 display->has_hdmi_infoframe = true; 4736 4737 if (hf_vsdb[6] & 0x80) { 4738 hdmi->scdc.supported = true; 4739 if (hf_vsdb[6] & 0x40) 4740 hdmi->scdc.read_request = true; 4741 } 4742 4743 /* 4744 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 4745 * And as per the spec, three factors confirm this: 4746 * * Availability of a HF-VSDB block in EDID (check) 4747 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 4748 * * SCDC support available (let's check) 4749 * Lets check it out. 4750 */ 4751 4752 if (hf_vsdb[5]) { 4753 /* max clock is 5000 KHz times block value */ 4754 u32 max_tmds_clock = hf_vsdb[5] * 5000; 4755 struct drm_scdc *scdc = &hdmi->scdc; 4756 4757 if (max_tmds_clock > 340000) { 4758 display->max_tmds_clock = max_tmds_clock; 4759 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n", 4760 display->max_tmds_clock); 4761 } 4762 4763 if (scdc->supported) { 4764 scdc->scrambling.supported = true; 4765 4766 /* Few sinks support scrambling for clocks < 340M */ 4767 if ((hf_vsdb[6] & 0x8)) 4768 scdc->scrambling.low_rates = true; 4769 } 4770 } 4771 4772 drm_parse_ycbcr420_deep_color_info(connector, hf_vsdb); 4773 } 4774 4775 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 4776 const u8 *hdmi) 4777 { 4778 struct drm_display_info *info = &connector->display_info; 4779 unsigned int dc_bpc = 0; 4780 4781 /* HDMI supports at least 8 bpc */ 4782 info->bpc = 8; 4783 4784 if (cea_db_payload_len(hdmi) < 6) 4785 return; 4786 4787 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 4788 dc_bpc = 10; 4789 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_30; 4790 DRM_DEBUG("%s: HDMI sink does deep color 30.\n", 4791 connector->name); 4792 } 4793 4794 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 4795 dc_bpc = 12; 4796 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_36; 4797 DRM_DEBUG("%s: HDMI sink does deep color 36.\n", 4798 connector->name); 4799 } 4800 4801 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 4802 dc_bpc = 16; 4803 info->edid_hdmi_dc_modes |= DRM_EDID_HDMI_DC_48; 4804 DRM_DEBUG("%s: HDMI sink does deep color 48.\n", 4805 connector->name); 4806 } 4807 4808 if (dc_bpc == 0) { 4809 DRM_DEBUG("%s: No deep color support on this HDMI sink.\n", 4810 connector->name); 4811 return; 4812 } 4813 4814 DRM_DEBUG("%s: Assigning HDMI sink color depth as %d bpc.\n", 4815 connector->name, dc_bpc); 4816 info->bpc = dc_bpc; 4817 4818 /* 4819 * Deep color support mandates RGB444 support for all video 4820 * modes and forbids YCRCB422 support for all video modes per 4821 * HDMI 1.3 spec. 4822 */ 4823 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4824 4825 /* YCRCB444 is optional according to spec. */ 4826 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 4827 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4828 DRM_DEBUG("%s: HDMI sink does YCRCB444 in deep color.\n", 4829 connector->name); 4830 } 4831 4832 /* 4833 * Spec says that if any deep color mode is supported at all, 4834 * then deep color 36 bit must be supported. 4835 */ 4836 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 4837 DRM_DEBUG("%s: HDMI sink should do DC_36, but does not!\n", 4838 connector->name); 4839 } 4840 } 4841 4842 static void 4843 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 4844 { 4845 struct drm_display_info *info = &connector->display_info; 4846 u8 len = cea_db_payload_len(db); 4847 4848 if (len >= 6) 4849 info->dvi_dual = db[6] & 1; 4850 if (len >= 7) 4851 info->max_tmds_clock = db[7] * 5000; 4852 4853 DRM_DEBUG_KMS("HDMI: DVI dual %d, " 4854 "max TMDS clock %d kHz\n", 4855 info->dvi_dual, 4856 info->max_tmds_clock); 4857 4858 drm_parse_hdmi_deep_color_info(connector, db); 4859 } 4860 4861 static void drm_parse_cea_ext(struct drm_connector *connector, 4862 const struct edid *edid) 4863 { 4864 struct drm_display_info *info = &connector->display_info; 4865 const u8 *edid_ext; 4866 int i, start, end; 4867 4868 edid_ext = drm_find_cea_extension(edid); 4869 if (!edid_ext) 4870 return; 4871 4872 info->cea_rev = edid_ext[1]; 4873 4874 /* The existence of a CEA block should imply RGB support */ 4875 info->color_formats = DRM_COLOR_FORMAT_RGB444; 4876 if (edid_ext[3] & EDID_CEA_YCRCB444) 4877 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4878 if (edid_ext[3] & EDID_CEA_YCRCB422) 4879 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4880 4881 if (cea_db_offsets(edid_ext, &start, &end)) 4882 return; 4883 4884 for_each_cea_db(edid_ext, i, start, end) { 4885 const u8 *db = &edid_ext[i]; 4886 4887 if (cea_db_is_hdmi_vsdb(db)) 4888 drm_parse_hdmi_vsdb_video(connector, db); 4889 if (cea_db_is_hdmi_forum_vsdb(db)) 4890 drm_parse_hdmi_forum_vsdb(connector, db); 4891 if (cea_db_is_y420cmdb(db)) 4892 drm_parse_y420cmdb_bitmap(connector, db); 4893 if (cea_db_is_vcdb(db)) 4894 drm_parse_vcdb(connector, db); 4895 if (cea_db_is_hdmi_hdr_metadata_block(db)) 4896 drm_parse_hdr_metadata_block(connector, db); 4897 } 4898 } 4899 4900 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 4901 * all of the values which would have been set from EDID 4902 */ 4903 void 4904 drm_reset_display_info(struct drm_connector *connector) 4905 { 4906 struct drm_display_info *info = &connector->display_info; 4907 4908 info->width_mm = 0; 4909 info->height_mm = 0; 4910 4911 info->bpc = 0; 4912 info->color_formats = 0; 4913 info->cea_rev = 0; 4914 info->max_tmds_clock = 0; 4915 info->dvi_dual = false; 4916 info->has_hdmi_infoframe = false; 4917 info->rgb_quant_range_selectable = false; 4918 memset(&info->hdmi, 0, sizeof(info->hdmi)); 4919 4920 info->non_desktop = 0; 4921 } 4922 4923 u32 drm_add_display_info(struct drm_connector *connector, const struct edid *edid) 4924 { 4925 struct drm_display_info *info = &connector->display_info; 4926 4927 u32 quirks = edid_get_quirks(edid); 4928 4929 drm_reset_display_info(connector); 4930 4931 info->width_mm = edid->width_cm * 10; 4932 info->height_mm = edid->height_cm * 10; 4933 4934 info->non_desktop = !!(quirks & EDID_QUIRK_NON_DESKTOP); 4935 4936 DRM_DEBUG_KMS("non_desktop set to %d\n", info->non_desktop); 4937 4938 if (edid->revision < 3) 4939 return quirks; 4940 4941 if (!(edid->input & DRM_EDID_INPUT_DIGITAL)) 4942 return quirks; 4943 4944 drm_parse_cea_ext(connector, edid); 4945 4946 /* 4947 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 4948 * 4949 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 4950 * tells us to assume 8 bpc color depth if the EDID doesn't have 4951 * extensions which tell otherwise. 4952 */ 4953 if (info->bpc == 0 && edid->revision == 3 && 4954 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 4955 info->bpc = 8; 4956 DRM_DEBUG("%s: Assigning DFP sink color depth as %d bpc.\n", 4957 connector->name, info->bpc); 4958 } 4959 4960 /* Only defined for 1.4 with digital displays */ 4961 if (edid->revision < 4) 4962 return quirks; 4963 4964 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 4965 case DRM_EDID_DIGITAL_DEPTH_6: 4966 info->bpc = 6; 4967 break; 4968 case DRM_EDID_DIGITAL_DEPTH_8: 4969 info->bpc = 8; 4970 break; 4971 case DRM_EDID_DIGITAL_DEPTH_10: 4972 info->bpc = 10; 4973 break; 4974 case DRM_EDID_DIGITAL_DEPTH_12: 4975 info->bpc = 12; 4976 break; 4977 case DRM_EDID_DIGITAL_DEPTH_14: 4978 info->bpc = 14; 4979 break; 4980 case DRM_EDID_DIGITAL_DEPTH_16: 4981 info->bpc = 16; 4982 break; 4983 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 4984 default: 4985 info->bpc = 0; 4986 break; 4987 } 4988 4989 DRM_DEBUG("%s: Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 4990 connector->name, info->bpc); 4991 4992 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 4993 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 4994 info->color_formats |= DRM_COLOR_FORMAT_YCRCB444; 4995 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 4996 info->color_formats |= DRM_COLOR_FORMAT_YCRCB422; 4997 return quirks; 4998 } 4999 5000 static int validate_displayid(const u8 *displayid, int length, int idx) 5001 { 5002 int i; 5003 u8 csum = 0; 5004 const struct displayid_hdr *base; 5005 5006 base = (const struct displayid_hdr *)&displayid[idx]; 5007 5008 DRM_DEBUG_KMS("base revision 0x%x, length %d, %d %d\n", 5009 base->rev, base->bytes, base->prod_id, base->ext_count); 5010 5011 if (base->bytes + 5 > length - idx) 5012 return -EINVAL; 5013 for (i = idx; i <= base->bytes + 5; i++) { 5014 csum += displayid[i]; 5015 } 5016 if (csum) { 5017 DRM_NOTE("DisplayID checksum invalid, remainder is %d\n", csum); 5018 return -EINVAL; 5019 } 5020 return 0; 5021 } 5022 5023 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 5024 const struct displayid_detailed_timings_1 *timings) 5025 { 5026 struct drm_display_mode *mode; 5027 unsigned pixel_clock = (timings->pixel_clock[0] | 5028 (timings->pixel_clock[1] << 8) | 5029 (timings->pixel_clock[2] << 16)); 5030 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 5031 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 5032 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 5033 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 5034 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 5035 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 5036 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 5037 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 5038 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 5039 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 5040 mode = drm_mode_create(dev); 5041 if (!mode) 5042 return NULL; 5043 5044 mode->clock = pixel_clock * 10; 5045 mode->hdisplay = hactive; 5046 mode->hsync_start = mode->hdisplay + hsync; 5047 mode->hsync_end = mode->hsync_start + hsync_width; 5048 mode->htotal = mode->hdisplay + hblank; 5049 5050 mode->vdisplay = vactive; 5051 mode->vsync_start = mode->vdisplay + vsync; 5052 mode->vsync_end = mode->vsync_start + vsync_width; 5053 mode->vtotal = mode->vdisplay + vblank; 5054 5055 mode->flags = 0; 5056 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 5057 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 5058 mode->type = DRM_MODE_TYPE_DRIVER; 5059 5060 if (timings->flags & 0x80) 5061 mode->type |= DRM_MODE_TYPE_PREFERRED; 5062 mode->vrefresh = drm_mode_vrefresh(mode); 5063 drm_mode_set_name(mode); 5064 5065 return mode; 5066 } 5067 5068 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 5069 const struct displayid_block *block) 5070 { 5071 const struct displayid_detailed_timing_block *det = (const struct displayid_detailed_timing_block *)block; 5072 int i; 5073 int num_timings; 5074 struct drm_display_mode *newmode; 5075 int num_modes = 0; 5076 /* blocks must be multiple of 20 bytes length */ 5077 if (block->num_bytes % 20) 5078 return 0; 5079 5080 num_timings = block->num_bytes / 20; 5081 for (i = 0; i < num_timings; i++) { 5082 const struct displayid_detailed_timings_1 *timings = &det->timings[i]; 5083 5084 newmode = drm_mode_displayid_detailed(connector->dev, timings); 5085 if (!newmode) 5086 continue; 5087 5088 drm_mode_probed_add(connector, newmode); 5089 num_modes++; 5090 } 5091 return num_modes; 5092 } 5093 5094 static int add_displayid_detailed_modes(struct drm_connector *connector, 5095 struct edid *edid) 5096 { 5097 const u8 *displayid; 5098 int ret; 5099 int idx = 1; 5100 int length = EDID_LENGTH; 5101 const struct displayid_block *block; 5102 int num_modes = 0; 5103 5104 displayid = drm_find_displayid_extension(edid); 5105 if (!displayid) 5106 return 0; 5107 5108 ret = validate_displayid(displayid, length, idx); 5109 if (ret) 5110 return 0; 5111 5112 idx += sizeof(struct displayid_hdr); 5113 for_each_displayid_db(displayid, block, idx, length) { 5114 switch (block->tag) { 5115 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5116 num_modes += add_displayid_detailed_1_modes(connector, block); 5117 break; 5118 } 5119 } 5120 return num_modes; 5121 } 5122 5123 /** 5124 * drm_add_edid_modes - add modes from EDID data, if available 5125 * @connector: connector we're probing 5126 * @edid: EDID data 5127 * 5128 * Add the specified modes to the connector's mode list. Also fills out the 5129 * &drm_display_info structure and ELD in @connector with any information which 5130 * can be derived from the edid. 5131 * 5132 * Return: The number of modes added or 0 if we couldn't find any. 5133 */ 5134 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 5135 { 5136 int num_modes = 0; 5137 u32 quirks; 5138 5139 if (edid == NULL) { 5140 clear_eld(connector); 5141 return 0; 5142 } 5143 if (!drm_edid_is_valid(edid)) { 5144 clear_eld(connector); 5145 dev_warn(connector->dev->dev, "%s: EDID invalid.\n", 5146 connector->name); 5147 return 0; 5148 } 5149 5150 drm_edid_to_eld(connector, edid); 5151 5152 /* 5153 * CEA-861-F adds ycbcr capability map block, for HDMI 2.0 sinks. 5154 * To avoid multiple parsing of same block, lets parse that map 5155 * from sink info, before parsing CEA modes. 5156 */ 5157 quirks = drm_add_display_info(connector, edid); 5158 5159 /* 5160 * EDID spec says modes should be preferred in this order: 5161 * - preferred detailed mode 5162 * - other detailed modes from base block 5163 * - detailed modes from extension blocks 5164 * - CVT 3-byte code modes 5165 * - standard timing codes 5166 * - established timing codes 5167 * - modes inferred from GTF or CVT range information 5168 * 5169 * We get this pretty much right. 5170 * 5171 * XXX order for additional mode types in extension blocks? 5172 */ 5173 num_modes += add_detailed_modes(connector, edid, quirks); 5174 num_modes += add_cvt_modes(connector, edid); 5175 num_modes += add_standard_modes(connector, edid); 5176 num_modes += add_established_modes(connector, edid); 5177 num_modes += add_cea_modes(connector, edid); 5178 num_modes += add_alternate_cea_modes(connector, edid); 5179 num_modes += add_displayid_detailed_modes(connector, edid); 5180 if (edid->features & DRM_EDID_FEATURE_DEFAULT_GTF) 5181 num_modes += add_inferred_modes(connector, edid); 5182 5183 if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 5184 edid_fixup_preferred(connector, quirks); 5185 5186 if (quirks & EDID_QUIRK_FORCE_6BPC) 5187 connector->display_info.bpc = 6; 5188 5189 if (quirks & EDID_QUIRK_FORCE_8BPC) 5190 connector->display_info.bpc = 8; 5191 5192 if (quirks & EDID_QUIRK_FORCE_10BPC) 5193 connector->display_info.bpc = 10; 5194 5195 if (quirks & EDID_QUIRK_FORCE_12BPC) 5196 connector->display_info.bpc = 12; 5197 5198 return num_modes; 5199 } 5200 EXPORT_SYMBOL(drm_add_edid_modes); 5201 5202 /** 5203 * drm_add_modes_noedid - add modes for the connectors without EDID 5204 * @connector: connector we're probing 5205 * @hdisplay: the horizontal display limit 5206 * @vdisplay: the vertical display limit 5207 * 5208 * Add the specified modes to the connector's mode list. Only when the 5209 * hdisplay/vdisplay is not beyond the given limit, it will be added. 5210 * 5211 * Return: The number of modes added or 0 if we couldn't find any. 5212 */ 5213 int drm_add_modes_noedid(struct drm_connector *connector, 5214 int hdisplay, int vdisplay) 5215 { 5216 int i, count, num_modes = 0; 5217 struct drm_display_mode *mode; 5218 struct drm_device *dev = connector->dev; 5219 5220 count = ARRAY_SIZE(drm_dmt_modes); 5221 if (hdisplay < 0) 5222 hdisplay = 0; 5223 if (vdisplay < 0) 5224 vdisplay = 0; 5225 5226 for (i = 0; i < count; i++) { 5227 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 5228 if (hdisplay && vdisplay) { 5229 /* 5230 * Only when two are valid, they will be used to check 5231 * whether the mode should be added to the mode list of 5232 * the connector. 5233 */ 5234 if (ptr->hdisplay > hdisplay || 5235 ptr->vdisplay > vdisplay) 5236 continue; 5237 } 5238 if (drm_mode_vrefresh(ptr) > 61) 5239 continue; 5240 mode = drm_mode_duplicate(dev, ptr); 5241 if (mode) { 5242 drm_mode_probed_add(connector, mode); 5243 num_modes++; 5244 } 5245 } 5246 return num_modes; 5247 } 5248 EXPORT_SYMBOL(drm_add_modes_noedid); 5249 5250 /** 5251 * drm_set_preferred_mode - Sets the preferred mode of a connector 5252 * @connector: connector whose mode list should be processed 5253 * @hpref: horizontal resolution of preferred mode 5254 * @vpref: vertical resolution of preferred mode 5255 * 5256 * Marks a mode as preferred if it matches the resolution specified by @hpref 5257 * and @vpref. 5258 */ 5259 void drm_set_preferred_mode(struct drm_connector *connector, 5260 int hpref, int vpref) 5261 { 5262 struct drm_display_mode *mode; 5263 5264 list_for_each_entry(mode, &connector->probed_modes, head) { 5265 if (mode->hdisplay == hpref && 5266 mode->vdisplay == vpref) 5267 mode->type |= DRM_MODE_TYPE_PREFERRED; 5268 } 5269 } 5270 EXPORT_SYMBOL(drm_set_preferred_mode); 5271 5272 static bool is_hdmi2_sink(struct drm_connector *connector) 5273 { 5274 /* 5275 * FIXME: sil-sii8620 doesn't have a connector around when 5276 * we need one, so we have to be prepared for a NULL connector. 5277 */ 5278 if (!connector) 5279 return true; 5280 5281 return connector->display_info.hdmi.scdc.supported || 5282 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB420; 5283 } 5284 5285 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 5286 { 5287 return sink_eotf & BIT(output_eotf); 5288 } 5289 5290 /** 5291 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 5292 * HDR metadata from userspace 5293 * @frame: HDMI DRM infoframe 5294 * @conn_state: Connector state containing HDR metadata 5295 * 5296 * Return: 0 on success or a negative error code on failure. 5297 */ 5298 int 5299 drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 5300 const struct drm_connector_state *conn_state) 5301 { 5302 struct drm_connector *connector; 5303 struct hdr_output_metadata *hdr_metadata; 5304 int err; 5305 5306 if (!frame || !conn_state) 5307 return -EINVAL; 5308 5309 connector = conn_state->connector; 5310 5311 if (!conn_state->hdr_output_metadata) 5312 return -EINVAL; 5313 5314 hdr_metadata = conn_state->hdr_output_metadata->data; 5315 5316 if (!hdr_metadata || !connector) 5317 return -EINVAL; 5318 5319 /* Sink EOTF is Bit map while infoframe is absolute values */ 5320 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 5321 connector->hdr_sink_metadata.hdmi_type1.eotf)) { 5322 DRM_DEBUG_KMS("EOTF Not Supported\n"); 5323 return -EINVAL; 5324 } 5325 5326 err = hdmi_drm_infoframe_init(frame); 5327 if (err < 0) 5328 return err; 5329 5330 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 5331 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 5332 5333 BUILD_BUG_ON(sizeof(frame->display_primaries) != 5334 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 5335 BUILD_BUG_ON(sizeof(frame->white_point) != 5336 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 5337 5338 memcpy(&frame->display_primaries, 5339 &hdr_metadata->hdmi_metadata_type1.display_primaries, 5340 sizeof(frame->display_primaries)); 5341 5342 memcpy(&frame->white_point, 5343 &hdr_metadata->hdmi_metadata_type1.white_point, 5344 sizeof(frame->white_point)); 5345 5346 frame->max_display_mastering_luminance = 5347 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 5348 frame->min_display_mastering_luminance = 5349 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 5350 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 5351 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 5352 5353 return 0; 5354 } 5355 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 5356 5357 static u8 drm_mode_hdmi_vic(struct drm_connector *connector, 5358 const struct drm_display_mode *mode) 5359 { 5360 bool has_hdmi_infoframe = connector ? 5361 connector->display_info.has_hdmi_infoframe : false; 5362 5363 if (!has_hdmi_infoframe) 5364 return 0; 5365 5366 /* No HDMI VIC when signalling 3D video format */ 5367 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 5368 return 0; 5369 5370 return drm_match_hdmi_mode(mode); 5371 } 5372 5373 static u8 drm_mode_cea_vic(struct drm_connector *connector, 5374 const struct drm_display_mode *mode) 5375 { 5376 u8 vic; 5377 5378 /* 5379 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 5380 * we should send its VIC in vendor infoframes, else send the 5381 * VIC in AVI infoframes. Lets check if this mode is present in 5382 * HDMI 1.4b 4K modes 5383 */ 5384 if (drm_mode_hdmi_vic(connector, mode)) 5385 return 0; 5386 5387 vic = drm_match_cea_mode(mode); 5388 5389 /* 5390 * HDMI 1.4 VIC range: 1 <= VIC <= 64 (CEA-861-D) but 5391 * HDMI 2.0 VIC range: 1 <= VIC <= 107 (CEA-861-F). So we 5392 * have to make sure we dont break HDMI 1.4 sinks. 5393 */ 5394 if (!is_hdmi2_sink(connector) && vic > 64) 5395 return 0; 5396 5397 return vic; 5398 } 5399 5400 /** 5401 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 5402 * data from a DRM display mode 5403 * @frame: HDMI AVI infoframe 5404 * @connector: the connector 5405 * @mode: DRM display mode 5406 * 5407 * Return: 0 on success or a negative error code on failure. 5408 */ 5409 int 5410 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 5411 struct drm_connector *connector, 5412 const struct drm_display_mode *mode) 5413 { 5414 enum hdmi_picture_aspect picture_aspect; 5415 u8 vic, hdmi_vic; 5416 int err; 5417 5418 if (!frame || !mode) 5419 return -EINVAL; 5420 5421 err = hdmi_avi_infoframe_init(frame); 5422 if (err < 0) 5423 return err; 5424 5425 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 5426 frame->pixel_repeat = 1; 5427 5428 vic = drm_mode_cea_vic(connector, mode); 5429 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 5430 5431 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5432 5433 /* 5434 * As some drivers don't support atomic, we can't use connector state. 5435 * So just initialize the frame with default values, just the same way 5436 * as it's done with other properties here. 5437 */ 5438 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 5439 frame->itc = 0; 5440 5441 /* 5442 * Populate picture aspect ratio from either 5443 * user input (if specified) or from the CEA/HDMI mode lists. 5444 */ 5445 picture_aspect = mode->picture_aspect_ratio; 5446 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 5447 if (vic) 5448 picture_aspect = drm_get_cea_aspect_ratio(vic); 5449 else if (hdmi_vic) 5450 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 5451 } 5452 5453 /* 5454 * The infoframe can't convey anything but none, 4:3 5455 * and 16:9, so if the user has asked for anything else 5456 * we can only satisfy it by specifying the right VIC. 5457 */ 5458 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 5459 if (vic) { 5460 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 5461 return -EINVAL; 5462 } else if (hdmi_vic) { 5463 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 5464 return -EINVAL; 5465 } else { 5466 return -EINVAL; 5467 } 5468 5469 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 5470 } 5471 5472 frame->video_code = vic; 5473 frame->picture_aspect = picture_aspect; 5474 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 5475 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 5476 5477 return 0; 5478 } 5479 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 5480 5481 /* HDMI Colorspace Spec Definitions */ 5482 #define FULL_COLORIMETRY_MASK 0x1FF 5483 #define NORMAL_COLORIMETRY_MASK 0x3 5484 #define EXTENDED_COLORIMETRY_MASK 0x7 5485 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 5486 5487 #define C(x) ((x) << 0) 5488 #define EC(x) ((x) << 2) 5489 #define ACE(x) ((x) << 5) 5490 5491 #define HDMI_COLORIMETRY_NO_DATA 0x0 5492 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 5493 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 5494 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 5495 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 5496 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 5497 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 5498 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 5499 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 5500 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 5501 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 5502 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 5503 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 5504 5505 static const u32 hdmi_colorimetry_val[] = { 5506 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 5507 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 5508 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 5509 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 5510 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 5511 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 5512 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 5513 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 5514 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 5515 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 5516 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 5517 }; 5518 5519 #undef C 5520 #undef EC 5521 #undef ACE 5522 5523 /** 5524 * drm_hdmi_avi_infoframe_colorspace() - fill the HDMI AVI infoframe 5525 * colorspace information 5526 * @frame: HDMI AVI infoframe 5527 * @conn_state: connector state 5528 */ 5529 void 5530 drm_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 5531 const struct drm_connector_state *conn_state) 5532 { 5533 u32 colorimetry_val; 5534 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 5535 5536 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 5537 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 5538 else 5539 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 5540 5541 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 5542 /* 5543 * ToDo: Extend it for ACE formats as well. Modify the infoframe 5544 * structure and extend it in drivers/video/hdmi 5545 */ 5546 frame->extended_colorimetry = (colorimetry_val >> 2) & 5547 EXTENDED_COLORIMETRY_MASK; 5548 } 5549 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorspace); 5550 5551 /** 5552 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 5553 * quantization range information 5554 * @frame: HDMI AVI infoframe 5555 * @connector: the connector 5556 * @mode: DRM display mode 5557 * @rgb_quant_range: RGB quantization range (Q) 5558 */ 5559 void 5560 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 5561 struct drm_connector *connector, 5562 const struct drm_display_mode *mode, 5563 enum hdmi_quantization_range rgb_quant_range) 5564 { 5565 const struct drm_display_info *info = &connector->display_info; 5566 5567 /* 5568 * CEA-861: 5569 * "A Source shall not send a non-zero Q value that does not correspond 5570 * to the default RGB Quantization Range for the transmitted Picture 5571 * unless the Sink indicates support for the Q bit in a Video 5572 * Capabilities Data Block." 5573 * 5574 * HDMI 2.0 recommends sending non-zero Q when it does match the 5575 * default RGB quantization range for the mode, even when QS=0. 5576 */ 5577 if (info->rgb_quant_range_selectable || 5578 rgb_quant_range == drm_default_rgb_quant_range(mode)) 5579 frame->quantization_range = rgb_quant_range; 5580 else 5581 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 5582 5583 /* 5584 * CEA-861-F: 5585 * "When transmitting any RGB colorimetry, the Source should set the 5586 * YQ-field to match the RGB Quantization Range being transmitted 5587 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 5588 * set YQ=1) and the Sink shall ignore the YQ-field." 5589 * 5590 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 5591 * by non-zero YQ when receiving RGB. There doesn't seem to be any 5592 * good way to tell which version of CEA-861 the sink supports, so 5593 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 5594 * on on CEA-861-F. 5595 */ 5596 if (!is_hdmi2_sink(connector) || 5597 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 5598 frame->ycc_quantization_range = 5599 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 5600 else 5601 frame->ycc_quantization_range = 5602 HDMI_YCC_QUANTIZATION_RANGE_FULL; 5603 } 5604 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 5605 5606 /** 5607 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 5608 * bar information 5609 * @frame: HDMI AVI infoframe 5610 * @conn_state: connector state 5611 */ 5612 void 5613 drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 5614 const struct drm_connector_state *conn_state) 5615 { 5616 frame->right_bar = conn_state->tv.margins.right; 5617 frame->left_bar = conn_state->tv.margins.left; 5618 frame->top_bar = conn_state->tv.margins.top; 5619 frame->bottom_bar = conn_state->tv.margins.bottom; 5620 } 5621 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 5622 5623 static enum hdmi_3d_structure 5624 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 5625 { 5626 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 5627 5628 switch (layout) { 5629 case DRM_MODE_FLAG_3D_FRAME_PACKING: 5630 return HDMI_3D_STRUCTURE_FRAME_PACKING; 5631 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 5632 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 5633 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 5634 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 5635 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 5636 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 5637 case DRM_MODE_FLAG_3D_L_DEPTH: 5638 return HDMI_3D_STRUCTURE_L_DEPTH; 5639 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 5640 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 5641 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 5642 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 5643 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 5644 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 5645 default: 5646 return HDMI_3D_STRUCTURE_INVALID; 5647 } 5648 } 5649 5650 /** 5651 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 5652 * data from a DRM display mode 5653 * @frame: HDMI vendor infoframe 5654 * @connector: the connector 5655 * @mode: DRM display mode 5656 * 5657 * Note that there's is a need to send HDMI vendor infoframes only when using a 5658 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 5659 * function will return -EINVAL, error that can be safely ignored. 5660 * 5661 * Return: 0 on success or a negative error code on failure. 5662 */ 5663 int 5664 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 5665 struct drm_connector *connector, 5666 const struct drm_display_mode *mode) 5667 { 5668 /* 5669 * FIXME: sil-sii8620 doesn't have a connector around when 5670 * we need one, so we have to be prepared for a NULL connector. 5671 */ 5672 bool has_hdmi_infoframe = connector ? 5673 connector->display_info.has_hdmi_infoframe : false; 5674 int err; 5675 5676 if (!frame || !mode) 5677 return -EINVAL; 5678 5679 if (!has_hdmi_infoframe) 5680 return -EINVAL; 5681 5682 err = hdmi_vendor_infoframe_init(frame); 5683 if (err < 0) 5684 return err; 5685 5686 /* 5687 * Even if it's not absolutely necessary to send the infoframe 5688 * (ie.vic==0 and s3d_struct==0) we will still send it if we 5689 * know that the sink can handle it. This is based on a 5690 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 5691 * have trouble realizing that they shuld switch from 3D to 2D 5692 * mode if the source simply stops sending the infoframe when 5693 * it wants to switch from 3D to 2D. 5694 */ 5695 frame->vic = drm_mode_hdmi_vic(connector, mode); 5696 frame->s3d_struct = s3d_structure_from_display_mode(mode); 5697 5698 return 0; 5699 } 5700 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 5701 5702 static int drm_parse_tiled_block(struct drm_connector *connector, 5703 const struct displayid_block *block) 5704 { 5705 const struct displayid_tiled_block *tile = (const struct displayid_tiled_block *)block; 5706 u16 w, h; 5707 u8 tile_v_loc, tile_h_loc; 5708 u8 num_v_tile, num_h_tile; 5709 struct drm_tile_group *tg; 5710 5711 w = tile->tile_size[0] | tile->tile_size[1] << 8; 5712 h = tile->tile_size[2] | tile->tile_size[3] << 8; 5713 5714 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 5715 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 5716 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 5717 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 5718 5719 connector->has_tile = true; 5720 if (tile->tile_cap & 0x80) 5721 connector->tile_is_single_monitor = true; 5722 5723 connector->num_h_tile = num_h_tile + 1; 5724 connector->num_v_tile = num_v_tile + 1; 5725 connector->tile_h_loc = tile_h_loc; 5726 connector->tile_v_loc = tile_v_loc; 5727 connector->tile_h_size = w + 1; 5728 connector->tile_v_size = h + 1; 5729 5730 DRM_DEBUG_KMS("tile cap 0x%x\n", tile->tile_cap); 5731 DRM_DEBUG_KMS("tile_size %d x %d\n", w + 1, h + 1); 5732 DRM_DEBUG_KMS("topo num tiles %dx%d, location %dx%d\n", 5733 num_h_tile + 1, num_v_tile + 1, tile_h_loc, tile_v_loc); 5734 DRM_DEBUG_KMS("vend %c%c%c\n", tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 5735 5736 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 5737 if (!tg) { 5738 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 5739 } 5740 if (!tg) 5741 return -ENOMEM; 5742 5743 if (connector->tile_group != tg) { 5744 /* if we haven't got a pointer, 5745 take the reference, drop ref to old tile group */ 5746 if (connector->tile_group) { 5747 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5748 } 5749 connector->tile_group = tg; 5750 } else 5751 /* if same tile group, then release the ref we just took. */ 5752 drm_mode_put_tile_group(connector->dev, tg); 5753 return 0; 5754 } 5755 5756 static int drm_parse_display_id(struct drm_connector *connector, 5757 const u8 *displayid, int length, 5758 bool is_edid_extension) 5759 { 5760 /* if this is an EDID extension the first byte will be 0x70 */ 5761 int idx = 0; 5762 const struct displayid_block *block; 5763 int ret; 5764 5765 if (is_edid_extension) 5766 idx = 1; 5767 5768 ret = validate_displayid(displayid, length, idx); 5769 if (ret) 5770 return ret; 5771 5772 idx += sizeof(struct displayid_hdr); 5773 for_each_displayid_db(displayid, block, idx, length) { 5774 DRM_DEBUG_KMS("block id 0x%x, rev %d, len %d\n", 5775 block->tag, block->rev, block->num_bytes); 5776 5777 switch (block->tag) { 5778 case DATA_BLOCK_TILED_DISPLAY: 5779 ret = drm_parse_tiled_block(connector, block); 5780 if (ret) 5781 return ret; 5782 break; 5783 case DATA_BLOCK_TYPE_1_DETAILED_TIMING: 5784 /* handled in mode gathering code. */ 5785 break; 5786 case DATA_BLOCK_CTA: 5787 /* handled in the cea parser code. */ 5788 break; 5789 default: 5790 DRM_DEBUG_KMS("found DisplayID tag 0x%x, unhandled\n", block->tag); 5791 break; 5792 } 5793 } 5794 return 0; 5795 } 5796 5797 static void drm_get_displayid(struct drm_connector *connector, 5798 struct edid *edid) 5799 { 5800 const void *displayid = NULL; 5801 int ret; 5802 connector->has_tile = false; 5803 displayid = drm_find_displayid_extension(edid); 5804 if (!displayid) { 5805 /* drop reference to any tile group we had */ 5806 goto out_drop_ref; 5807 } 5808 5809 ret = drm_parse_display_id(connector, displayid, EDID_LENGTH, true); 5810 if (ret < 0) 5811 goto out_drop_ref; 5812 if (!connector->has_tile) 5813 goto out_drop_ref; 5814 return; 5815 out_drop_ref: 5816 if (connector->tile_group) { 5817 drm_mode_put_tile_group(connector->dev, connector->tile_group); 5818 connector->tile_group = NULL; 5819 } 5820 return; 5821 } 5822
Indexes created Sat Sep 20 22:09:52 GMT 2025