1 /* $NetBSD: virtgpu_drm.h,v 1.2 2021/12/18 23:45:46 riastradh Exp $ */ 2 3 /* 4 * Copyright 2013 Red Hat 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), 9 * to deal in the Software without restriction, including without limitation 10 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 11 * and/or sell copies of the Software, and to permit persons to whom the 12 * Software is furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the next 15 * paragraph) shall be included in all copies or substantial portions of the 16 * Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 24 * OTHER DEALINGS IN THE SOFTWARE. 25 */ 26 #ifndef VIRTGPU_DRM_H 27 #define VIRTGPU_DRM_H 28 29 #include "drm.h" 30 31 #if defined(__cplusplus) 32 extern "C" { 33 #endif 34 35 /* Please note that modifications to all structs defined here are 36 * subject to backwards-compatibility constraints. 37 * 38 * Do not use pointers, use __u64 instead for 32 bit / 64 bit user/kernel 39 * compatibility Keep fields aligned to their size 40 */ 41 42 #define DRM_VIRTGPU_MAP 0x01 43 #define DRM_VIRTGPU_EXECBUFFER 0x02 44 #define DRM_VIRTGPU_GETPARAM 0x03 45 #define DRM_VIRTGPU_RESOURCE_CREATE 0x04 46 #define DRM_VIRTGPU_RESOURCE_INFO 0x05 47 #define DRM_VIRTGPU_TRANSFER_FROM_HOST 0x06 48 #define DRM_VIRTGPU_TRANSFER_TO_HOST 0x07 49 #define DRM_VIRTGPU_WAIT 0x08 50 #define DRM_VIRTGPU_GET_CAPS 0x09 51 52 #define VIRTGPU_EXECBUF_FENCE_FD_IN 0x01 53 #define VIRTGPU_EXECBUF_FENCE_FD_OUT 0x02 54 #define VIRTGPU_EXECBUF_FLAGS (\ 55 VIRTGPU_EXECBUF_FENCE_FD_IN |\ 56 VIRTGPU_EXECBUF_FENCE_FD_OUT |\ 57 0) 58 59 struct drm_virtgpu_map { 60 __u64 offset; /* use for mmap system call */ 61 __u32 handle; 62 __u32 pad; 63 }; 64 65 struct drm_virtgpu_execbuffer { 66 __u32 flags; 67 __u32 size; 68 __u64 command; /* void* */ 69 __u64 bo_handles; 70 __u32 num_bo_handles; 71 __s32 fence_fd; /* in/out fence fd (see VIRTGPU_EXECBUF_FENCE_FD_IN/OUT) */ 72 }; 73 74 #define VIRTGPU_PARAM_3D_FEATURES 1 /* do we have 3D features in the hw */ 75 #define VIRTGPU_PARAM_CAPSET_QUERY_FIX 2 /* do we have the capset fix */ 76 77 struct drm_virtgpu_getparam { 78 __u64 param; 79 __u64 value; 80 }; 81 82 /* NO_BO flags? NO resource flag? */ 83 /* resource flag for y_0_top */ 84 struct drm_virtgpu_resource_create { 85 __u32 target; 86 __u32 format; 87 __u32 bind; 88 __u32 width; 89 __u32 height; 90 __u32 depth; 91 __u32 array_size; 92 __u32 last_level; 93 __u32 nr_samples; 94 __u32 flags; 95 __u32 bo_handle; /* if this is set - recreate a new resource attached to this bo ? */ 96 __u32 res_handle; /* returned by kernel */ 97 __u32 size; /* validate transfer in the host */ 98 __u32 stride; /* validate transfer in the host */ 99 }; 100 101 struct drm_virtgpu_resource_info { 102 __u32 bo_handle; 103 __u32 res_handle; 104 __u32 size; 105 __u32 stride; 106 }; 107 108 struct drm_virtgpu_3d_box { 109 __u32 x; 110 __u32 y; 111 __u32 z; 112 __u32 w; 113 __u32 h; 114 __u32 d; 115 }; 116 117 struct drm_virtgpu_3d_transfer_to_host { 118 __u32 bo_handle; 119 struct drm_virtgpu_3d_box box; 120 __u32 level; 121 __u32 offset; 122 }; 123 124 struct drm_virtgpu_3d_transfer_from_host { 125 __u32 bo_handle; 126 struct drm_virtgpu_3d_box box; 127 __u32 level; 128 __u32 offset; 129 }; 130 131 #define VIRTGPU_WAIT_NOWAIT 1 /* like it */ 132 struct drm_virtgpu_3d_wait { 133 __u32 handle; /* 0 is an invalid handle */ 134 __u32 flags; 135 }; 136 137 struct drm_virtgpu_get_caps { 138 __u32 cap_set_id; 139 __u32 cap_set_ver; 140 __u64 addr; 141 __u32 size; 142 __u32 pad; 143 }; 144 145 #define DRM_IOCTL_VIRTGPU_MAP \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_MAP, struct drm_virtgpu_map) 147 148 #define DRM_IOCTL_VIRTGPU_EXECBUFFER \ 149 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_EXECBUFFER,\ 150 struct drm_virtgpu_execbuffer) 151 152 #define DRM_IOCTL_VIRTGPU_GETPARAM \ 153 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GETPARAM,\ 154 struct drm_virtgpu_getparam) 155 156 #define DRM_IOCTL_VIRTGPU_RESOURCE_CREATE \ 157 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_CREATE, \ 158 struct drm_virtgpu_resource_create) 159 160 #define DRM_IOCTL_VIRTGPU_RESOURCE_INFO \ 161 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_RESOURCE_INFO, \ 162 struct drm_virtgpu_resource_info) 163 164 #define DRM_IOCTL_VIRTGPU_TRANSFER_FROM_HOST \ 165 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_FROM_HOST, \ 166 struct drm_virtgpu_3d_transfer_from_host) 167 168 #define DRM_IOCTL_VIRTGPU_TRANSFER_TO_HOST \ 169 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_TRANSFER_TO_HOST, \ 170 struct drm_virtgpu_3d_transfer_to_host) 171 172 #define DRM_IOCTL_VIRTGPU_WAIT \ 173 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_WAIT, \ 174 struct drm_virtgpu_3d_wait) 175 176 #define DRM_IOCTL_VIRTGPU_GET_CAPS \ 177 DRM_IOWR(DRM_COMMAND_BASE + DRM_VIRTGPU_GET_CAPS, \ 178 struct drm_virtgpu_get_caps) 179 180 #if defined(__cplusplus) 181 } 182 #endif 183 184 #endif 185
Indexes created Sun Sep 21 20:09:37 GMT 2025