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    Searched defs:ds_info (Results 1 - 7 of 7) sorted by relevancy

  /xsrc/external/mit/MesaLib/dist/src/gallium/drivers/freedreno/a6xx/
fd6_draw.c 178 struct shader_info *ds_info = ir3_get_shader_info(emit.key.ds); variable in typeref:struct:shader_info
179 emit.key.key.tessellation = ir3_tess_mode(ds_info->tess.primitive_mode);
184 BITSET_TEST(ds_info->system_values_read, SYSTEM_VALUE_PRIMITIVE_ID) ||
255 shader_info *ds_info = &emit.ds->shader->nir->info; variable
258 switch (ds_info->tess.primitive_mode) {
fd6_program.c 718 shader_info *ds_info = &ds->shader->nir->info; variable
721 if (ds_info->tess.point_mode)
723 else if (ds_info->tess.primitive_mode == GL_ISOLINES)
725 else if (ds_info->tess.ccw)
731 fd6_gl2spacing(ds_info->tess.spacing)) |
  /xsrc/external/mit/MesaLib/dist/src/broadcom/vulkan/
v3dv_pipeline.c 2817 const VkPipelineDepthStencilStateCreateInfo *ds_info)
2819 if (!ds_info || !ds_info->depthTestEnable) {
2824 switch (ds_info->depthCompareOp) {
2843 if (ds_info->stencilTestEnable &&
2844 (!stencil_op_is_no_op(&ds_info->front) ||
2845 !stencil_op_is_no_op(&ds_info->back))) {
2962 const VkPipelineDepthStencilStateCreateInfo *ds_info = local
2987 vp_info, ds_info, cb_info, rs_info, cw_info);
2992 assert(!ds_info || !ds_info->depthBoundsTestEnable)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/intel/vulkan/
genX_pipeline.c 2526 const VkPipelineDepthStencilStateCreateInfo *ds_info = local
2545 emit_ds_state(pipeline, ds_info, dynamic_states, pass, subpass);
  /xsrc/external/mit/MesaLib.old/dist/src/freedreno/vulkan/
tu_pipeline.c 1161 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1163 assert(!ds_info->depthBoundsTestEnable);
1166 if (ds_info->depthTestEnable) {
1169 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
1172 if (ds_info->depthWriteEnable)
1182 const VkPipelineDepthStencilStateCreateInfo *ds_info)
1185 if (ds_info->stencilTestEnable) {
1186 const VkStencilOpState *front = &ds_info->front;
1187 const VkStencilOpState *back = &ds_info->back;
1634 const VkPipelineDepthStencilStateCreateInfo *ds_info local
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/freedreno/vulkan/
tu_pipeline.c 2864 const VkPipelineDepthStencilStateCreateInfo *ds_info = local
2873 if (ds_info->depthTestEnable) {
2876 A6XX_RB_DEPTH_CNTL_ZFUNC(tu6_compare_func(ds_info->depthCompareOp)) |
2882 if (ds_info->depthWriteEnable)
2886 if (ds_info->depthBoundsTestEnable)
2889 if (ds_info->depthBoundsTestEnable && !ds_info->depthTestEnable)
2901 const VkStencilOpState *front = &ds_info->front;
2902 const VkStencilOpState *back = &ds_info->back;
2914 if (ds_info->stencilTestEnable)
    [all...]
  /xsrc/external/mit/MesaLib/dist/src/amd/vulkan/
radv_pipeline.c 1793 const VkPipelineDepthStencilStateCreateInfo *ds_info = local
1806 if (ds_info) {
1808 db_depth_control = S_028800_Z_ENABLE(ds_info->depthTestEnable ? 1 : 0) |
1809 S_028800_Z_WRITE_ENABLE(ds_info->depthWriteEnable ? 1 : 0) |
1810 S_028800_ZFUNC(ds_info->depthCompareOp) |
1811 S_028800_DEPTH_BOUNDS_ENABLE(ds_info->depthBoundsTestEnable ? 1 : 0);
1814 if (has_stencil_attachment && ds_info->stencilTestEnable) {
1816 db_depth_control |= S_028800_STENCILFUNC(ds_info->front.compareOp);
1817 db_depth_control |= S_028800_STENCILFUNC_BF(ds_info->back.compareOp);

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